JPS58219638A - Interface device - Google Patents

Abstract

PURPOSE:To simplify a program and to supply a clock signal for a test to a control signal generation part, by providing a channel change part capable of change according to the number of channels of analog signals in the 1st interface part. CONSTITUTION:Analog signals from an analog input part 1 are applied to an analog multiplexer 2, which is controlled by the output of the 1st photocoupler part 11 connected to the 1st interface part 5 to select and input a specific signal to a sample holding part 3. The output of this holding part 3 is applied to an A/D converter 4, which is controlled by the start signal ST of the photocoupler part 11. The digital signal from this converter part 4 is inputted to the 2nd interface part 6 through the 2nd photocoupler part 13. This interface part 5 is provided with the channel change part which has switches, FF, etc., changed according to the number of the channels of the analog signals. Then, the program is simplified and the testing clock signal to a control signal generation part to facilitate a test adjustment.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interface device used for processing analog signals by a computer. A conventional example of this type of interface device was constructed as shown in FIG. In FIG. 1, reference numeral 1 denotes an analog signal input section into which an analog signal A 1 =An is input;

This multiplexer 2 has a first bus interface section 5.
A predetermined signal is selected from the manually inputted analog signals and manually inputted to the sample hold section 3. A control signal is also input to the sample hold unit 3 from the first bus interface unit 5, and in response to this control signal, an analog signal is input from the sample hold unit 3 to an analog-to-digital (hereinafter referred to as) converter unit l.

The A/D converter section q is also given a control signal from the first path interface section 5, and a digital signal is sent to the output of the converter section q. This digital signal is manually input to, for example, a computer (not shown) via the second path interface section 6. The first bus interface unit 5 is connected to, for example, a computer (not shown).

The first and second path interface sections 5 and 6 as described above
In particular, the first bus interface section 5 needs to use a program such as a computer to obtain control signals to be applied to the first multiplexer section 3 and the second converter section. For this reason, there is a drawback that programs for computers and the like become complicated. In addition, when controlling each of the above-mentioned parts 2 to q with control signals, it is necessary to use a computer to manage the time it takes for each part to wait until the analog signal settles down, which has the disadvantage that the combiator's programming method becomes sophisticated. be.

Furthermore, although the interface device shown in FIG. 1 is usually formed on a single printed board, it is difficult to test this device using only one printed board.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an interface device that eliminates the above-mentioned drawbacks, simplifies programming, and facilitates testing and adjustment.

An embodiment of the present invention will be described below with reference to the drawings.
Components that are the same as those in FIG. 1 are denoted by the same reference numerals. In FIG. The first photocoupler section 11 electrically isolates the control signal and supplies it to the analog multiplexer 2 and sample hold section 3, respectively. Note that the control signal supplied to the ψ converter section is given from the first photocoupler section 11 via the waveform correction section I2. When the output of the waveform correction section 12 is supplied to the ψconno (-Yube da), it sends out a digital signal to the output, but this signal is transmitted to the second photocoupler section 1.
3 (from which the digital signal is electrically isolated and input to the second interface section 6. The digital signal input to the second interface section 6 is supplied to a computer (not shown) and processed. When a digital signal is sent from the 2 interface section 6, the output display section 14 made of a light emitting diode emits light to identify that a digital signal is being sent out.

15 is a flip-flop, and this 7-lip prop 15
A start signal for the ψ converter unit q sent from the first photocoupler unit 11 and a control end signal output from the converter unit d are supplied to the first photocoupler unit 11.

When the flip 70 plug 15 receives the control end signal, it inputs its output to the first interface section 5 via the second photocoupler section 13. Note that the first interface section 5
Data latch signal DL and ready signal R sent from
Y and channel selection signal OH are supplied to the second interface section 6.

The specific configuration of the first interface circuit 5 will now be described with reference to Figure 3. In FIG. 3, reference numeral 31 denotes a read data input section, into which upper and lower data UDR and LDR are input from a computer (not shown) or the like. The data supplied to the input section 31 is input to the control signal generation section X formed from a flip-flop, and the output thereof is a start signal BT of the converter section - and a sample hold signal SH supplied to the sample hold section 3. Sent out. The signal generator is a clock signal generator, and the output of the clock signal generator Ω is supplied to the data input unit. This clock signal is sent out by turning on switch 33a only during testing. M is an initialization signal and external reset signal input section, and the output of this input section y is supplied to the control signal generation section Ω. 5 is φ comparator
Completion signal E to notify that the signal processing of the data section has been completed
A signal input to this human power section χ is supplied from the second photocoupler section 13 at the input section 111D. The output of the termination signal input section 5 is supplied to the control signal generation section 321.
One part of the signal is supplied to the second interface unit 6 as a data latch signal DL. X is a channel update section, and this update section X can be set according to the number of analog signal channels manually.
a comparator 36b to which the output of a is supplied, and a flip-flop 36a to which the sample hold signal SR is input.
The output of the flip-flop 360 is supplied to the comparator 36b, and the output is connected to the switch 3Ba.
If it matches the value set in , the number of channels will be reset.

FIG. 4 is a specific configuration diagram of the second interface section 6, which is formed from a prip 70 tube.

Next, the operation of the above embodiment will be described. Analog signal input section 1
The analog signal input to analog multiplexer 2
supplied to This multiplexer 2 receives channel numbers OHo to OHn, which are control signals for the number of channels set by the channel update section X of the first interface section 5.
is supplied. According to the channel numbers OHo to OHn, analog signals are input from the multiplexer 2 to the sample and hold section 3, and are sequentially input to the φ converter section according to the sample and hold signals. The start signal date T is also supplied to the ψ converter section from the first interface section 5 via the first photocoupler section 11, and a digital signal is obtained at its output. This digital signal is input to the second interface section 6 via the second photocoupler section 13. The second interface unit 6 supplies the input digital signal to a computer or the like for signal processing.

As described above, since the control signal of the first interface section 5 is supplied to each section via the photocoupler, malfunctions due to noise etc. are extremely reduced.

As described above, according to the present invention, since a channel update section that can be changed according to the number of analog signal channels is provided in the first interface section, it is no longer necessary to create a change signal by a program, thereby simplifying the program. In addition, since the clock signal for testing can be supplied to the control signal generating section, there are advantages such as ease of test adjustment by using this clock signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIGS. 3 and 4 are specific configuration diagrams of the main parts of FIG. 5... First interface section, 6... Second interface section, 11... First photocoupler section, 13.
...Second photocoupler section, X...Control signal generation section, n.
...Test clock signal generation section, X...channel update section.

Claims (1)

[Claims] (1) An analog multiplexer to which an analog signal is manually input, a sample-and-hold circuit section to which the output of this multiplexer is supplied, and an output of this circuit section to which the output is supplied,
an analog-to-digital converter that obtains a digital signal as an output; a first interface to which program commands from a computer are supplied and which provide control signals to the multiplexer, sample-and-hold circuit, and analog-to-digital converter; and a second interface section that inputs a digital signal controlled by the control signal t from the first interface section and output to the analog-to-digital converter section into a computer, wherein the first interface section A channel updating section that can update the number of analog signal input channels is provided in the device, and a clock signal generating section for testing is also provided, so that the clock signal generating section can be manually operated as the control signal generating section. interface device.