JP3430575B2 - Electronic music signal synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tone signal synthesizer.
Circulates the signal, especially in the loop circuit,
The pitch is basically controlled by the delay time
The present invention relates to a tone signal synthesizing apparatus which controls a tone color by using the same. [0002] 2. Description of the Related Art Vibration of a vibrating body such as a tube, a string, or a membrane is disclosed.
In the instrument to be used, these parts
Stimulation is given and various vibrations are generated.
Those that match the standing wave remain and continue the vibration. Vibrator
Shape, physical properties, etc. determine the standing wave frequency distribution, attenuation rate, etc.
You. [0003] Using a loop circuit having a predetermined delay time
This electronically realizes this tone generation mechanism.
Can be. Impulse etc. as initial stimulation in loop circuit
When this signal waveform is injected, this signal waveform
It turns and returns to its original position. Here, the signal waveform
The time required to circulate through the loop circuit is τ.
Signal waveform appears. That is, the constant corresponding to the frequency 1 / τ
A standing wave occurs. The frequency (frequency) of the generated standing wave is
Is governed by the delay time in the loop circuit. Tone of desired pitch
In order to cause delay, it is necessary to change the delay time arbitrarily.
Is desired. The tone of the generated tone is
By controlling the frequency distribution and attenuation rate with a filter
Can be changed. [0005] Japanese Patent Publication No. 58-48109 discloses this
Music signal synthesizer with such a loop circuit
You. The loop circuit has a shift resistor that controls the delay time.
Other filters that can control the tone and envelope.
Has been continued. [0006] To generate musical tones having various pitches and tones
In this case, the characteristics of the delay circuit and filter in the loop
Various changes need to be made. Dedicated hardware circuit
To meet these requirements, the tone generator circuit
It becomes complicated. In recent years, with the progress of digital signal processing circuits,
And realize such a loop circuit by software
It became possible to do. In particular, digital signal pro
By using Sessa (DSP), such a
Delay circuits and filters in loop circuits
Can be controlled in various ways. Generally, in an electronic musical instrument, a plurality of musical tones are
Can be generated simultaneously, using a loop circuit.
Electronic musical instruments can produce multiple musical tones simultaneously.
Is required. In a tone signal synthesizing circuit using a loop circuit,
However, the processing is complicated and enormous, and LSI
Even if you use a digital signal processor
One chip is needed to form one generated channel
Yes, if you try to perform a little complicated processing,
Two chips are required per channel. [0010] In a loop circuit type tone signal synthesizing apparatus,
If you try to generate multiple tones at the same time,
You need a channel. In this case,
It is important to supply an excitation waveform as described above. The system control CPU has a dedicated memory.
Then, various excitation waveforms are stored in this memory,
Excitation waveform is supplied to each tone signal synthesis channel according to
It is possible to do. If you store one set of excitation waveforms,
Therefore, the memory capacity can be small. However, in each channel,
If the CPU supplies the excitation waveform whenever necessary,
Transfer excitation waveform from PU to each tone signal synthesis channel
Transfer time, which is difficult to implement in practice.
You. As a more feasible system configuration, each channel
In this configuration, an excitation waveform memory is provided for each channel. FIG. 6 shows a conventional loop circuit.
1 shows a configuration in which a tone signal synthesizing device that performs sound generation is made into a double tone. System
System bus 102 is connected to a system control CPU 102.
Then, the tone signal synthesizing program is executed. This tone signal synthesizing program is stored in a ROM 1
03 and are required during program execution.
The registers are supplied by the RAM 104. Also the keyboard
Various controls such as the pitch bend wheel and the various I / O
It is connected to the system bus 101 via 105. A plurality of loop circuit type tone generators 108 are connected in parallel.
Are connected to the system bus 101. Each sound source circuit 1
08 is a digital signal processor (DSP) 11
1. Store registers and the like used for DSP processing
A RAM 112 and an initial waveform memory 113 are included. Note that R
OM103 also stores initial waveform data, and if necessary
It may be supplied to the initial waveform memory 113. Each loop circuit type tone generator circuit 108 has, for example,
For example, it is composed of a one-chip semiconductor device. Multiple tone generator circuits
The output of the adder 108 is added by an adder 116,
The signal is converted to an analog signal through the analog converter 117.
Output. Each of the tone generator circuits 108 is provided with a loop shown in FIG.
A loop circuit type sound source circuit is configured. Excitation waveform memory 121
Is controlled by the readout control circuit 122 and the excitation wave
The shape is read and supplied to the adder 123. Adder 123
The excitation waveform injected by the filter 124 and the delay 1
Circulate through a loop circuit including Filter 124
Controls and generates the frequency distribution of the circulating signal waveform
Adjust the tone of the musical tone. The delay 125 circulates in a loop circuit.
Determines the delay time of the signal and mainly determines the pitch of the generated tone.
dominate. Any position in the loop circuit,
An output 126 is derived behind the filter 124. According to such a configuration, each tone generator circuit 10
8 is based on a command given from the CPU 102,
A tone signal can be formed independently of each other. Accordingly
Loop-type circuit tone signal synthesizer with
An arrangement is formed. [0020] The structure as shown in FIG.
According to, it is possible to create multiple tone signals simultaneously
A loop-type tone signal synthesizer is provided,
Path requires a large amount of excitation waveform memory,
Leads to An object of the present invention is to provide a plurality of loop-type tone signals.
Includes a synthesis circuit, and uses only one set of excitation waveform memory
The excitation waveform can be supplied to the loop-type tone synthesis circuit of
Transfer the excitation waveform from the system control CPU to each loop circuit
It is also necessary to provide an electronic musical tone signal synthesizer that is unnecessary.
You. [0022] Means for Solving the Problems According to one aspect of the present invention,
For example, the electronic musical tone signal synthesizing device may include a delay unit and a filter.
Loop circuit type tone signal synthesizing circuit including
Multiple tone signal pro
Sessa and memorize multiple excitation waveforms, all the above pronunciations
A memory means common to the channels and the memory means
Read the excitation waveform independently for each sound channel
And a corresponding one of the plurality of tone signal processors.
Memory read means that can be selectively supplied
An excitation waveform generator including the plurality of tone signal processors.
And a control unit for controlling the excitation waveform generation unit in synchronization with the control unit.
including. [0023] In the double tone electronic musical tone signal synthesizer, each sound is generated.
The channel is composed of a tone signal synthesis circuit of the loop circuit type.
If necessary, supply an excitation waveform to each loop circuit.
However, the excitation waveform may be common to each channel. Memory means for storing a plurality of excitation waveforms;
The excitation waveform is read from this memory means, and any sound
An excitation waveform generator that can be supplied to the channel
Excitation waveforms on multiple sounding channels
Can be supplied. The control unit forms a plurality of tone generation channels.
The tone signal processor and the excitation waveform generator are synchronized and controlled.
Control, each of the multiple sound channels
Operate as if equipped with an excitation waveform generator
be able to. [0026] FIG. 1 shows an electronic musical tone signal according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a functional configuration of the synthesizing device. When the control unit 2 is connected to the system bus 1,
Control of the entire system. In system bus 1,
An excitation waveform reading section 4 is connected, and a waveform memory 5
Of the excitation waveform from the control unit 2 under the control of the control unit 2.
U. Excitation waveform supplied by excitation waveform readout unit 4
Are provided for a plurality of sound channels 6a, 6b,.
Be paid. Select the number of pronunciation channels as needed
be able to. Each sound channel has a delay D
A loop circuit 7 including a filter F is provided. An adder 8 is connected in the loop circuit 7.
And the excitation waveform supplied by the excitation waveform reading unit 4 is
receive. In addition, a predetermined position of the loop circuit 7 (in the illustrated case)
Output signal OUT is derived from immediately after the adder 8).
I have. The plurality of sound channels 6a, 6b,
, 6h control the control unit 2 via the system bus 1.
receive. The system bus 1 also has a keyboard and tone switch.
I / O 9 connected to the switch
When a key or key operation on the keyboard is performed, the detection signal
Is sent to the control unit 2. The control unit 2 sends a performance operation signal from the I / O 9
When received, generates a control signal according to the performance operation
And specify a vacant channel among the sounding channels
And instructs the excitation waveform readout unit 4 to read the waveform
Read the waveform signal and assign it to the assigned sounding channel 6.
Supply. The sound channel 6 supplied with the excitation waveform
Is obtained by circulating the excitation waveform through the loop circuit 7.
A tone signal is formed, and an output signal OUT is formed. In addition,
The output signal OUT from each sounding channel is
Sent to the round system to generate multiple musical tones. FIG. 2 shows a functional circuit as shown in FIG.
An example of a hardware configuration for realizing this will be described. System bar
A CPU 12 for controlling the entire system;
ROM 13 for storing programs such as
RAM 14 for forming a variety of circuits, performance controls, tone colors
Various I / Os 15 for connection with various controls such as switches
Connected to drive multiple sound channels, described below
Then, a plurality of tone signals are generated. The system bus 11 generates one initial waveform.
Raw part 16 and a plurality of sounding channels 18a, 18b, 18
.., 18h are connected. Initial waveform generator 16
To each of the plurality of sounding channels 18
Clock signal φ_sK and each pronunciation channel
The excitation waveforms W1, W2, W3,..., Wh are supplied. A plurality of sound channels 18a, 18b, 1
, 18h are added by the accumulator 19
Digital / analog
The signal is sent to the converter 20 and output as an analog signal.
If this analog signal is supplied to the sound system,
A musical tone is generated. In the initial waveform generator 16, the system
Receives commands and data from the CPU 12 via the bus 11
Control unit 21 reads the excitation waveform from the waveform memory
A readout control unit 22 for generating an address for
Have been killed. The waveform memory stores excitation waveforms at addresses 0 to R.
ROM23 and rewritable excitation of address R + 1 or more
A waveform RAM 24 is included. The excitation waveform RAM 24 has a CPU
It is also possible to store the excitation waveform sent from the controller 12. The control unit 21 receives the excitation from the excitation waveform ROM 23.
Read the excitation waveform or read the excitation waveform from the excitation waveform RAM 24
Selection signal SEL for selecting whether or not to read
Supply to 12S. The selector 25 is an excitation waveform ROM 2
3. Connected to the excitation waveform RAM 24 and the selection signal S = 0
At the time, the excitation waveform from the excitation waveform ROM 23 is supplied, and S =
At the time of 1, the excitation waveform from the excitation waveform RAM 24 is supplied.
You. Note that the waveform read control unit 22 reads the waveform
Generates an integer part and a decimal part as a read address, and outputs an integer part.
Is supplied to the excitation waveform ROM 23 or the excitation waveform RAM 24
Then, the decimal part FRAC is supplied to the interpolation unit 26. Interpolator 2
6 designates the excitation waveform supplied from the selector 25 as a target value.
Then, an interpolation operation according to the decimal part FRAC is performed. An excitation waveform interpolated through the interpolation unit 26
Is supplied to the waveform distribution unit 29, and the
After that, multiple pronunciation channels are simultaneously
, Wh are supplied to the excitation waveforms W1, W2, W3,.
The circuits from the control unit 21 to the interpolation unit 26 are time-divisionally
Operate and supply h-channel excitation waveforms in time division
You. The timing clock generator 28 has a predetermined
Timing signal φ_sIs generated, and the control unit 21 reads the waveform.
Control unit 22, waveform distribution unit 29 and each sounding channel
18. Multiple sound channels 18a, 18
, 18h have the same configuration. And
For example, in the sounding channel 18a, a digital sig
Null processor DSP 32a and signal processing RAM 33
a is connected. The DSP 32a is controlled from the system bus 11.
Control signal, and a waveform distribution unit 29 is connected to an external input terminal EXIN.
Receiving the excitation waveform W1 from the clock signal input terminal CL
K is the clock signal φ_sReceive. In addition, DSP32a
Is connected to the signal processing RAM 33a,
Provides registers and other information necessary for microprogram execution
You. For example, when a key on the keyboard is operated,
Key code and key on to CPU 12 via I / O 15
A signal or the like is supplied. The CPU 12 generates the sound channel 1
Assign a vacant channel from 8a to 18h
And controls the initial waveform generator 16 to generate a corresponding excitation waveform.
Read and assign the excitation waveform to the assigned sound channel.
Pay. In this way, the assigned pronunciation channel
In this case, a tone signal corresponding to the performance operation is formed. FIG. 3 shows the control section 21 and the control section 21 in the circuit of FIG.
3 shows a more detailed configuration of the waveform readout control unit 22.
In the figure, the part below the one-dot chain line indicates the control unit 21,
The portion above the chain line indicates the waveform read control unit 22. Commands and data from the CPU 12 are
Frequency number register provided for each channel
41, key-on register 42, waveform start address register
Data 43 and the waveform end address register 44.
You. Each of these registers 41 to 44 has a timing clock.
Signal φ_sThe timing is controlled by
It operates in synchronization with the switching signal. The waveform start address register 43 stores the waveform
Stores the address indicating the beginning of the waveform to be read from the memory
Register. Also, the waveform end address register
The data 44 stores a final address of the waveform to be read.
It is a Gista. In the configuration shown in FIG.
And the address R +
It is divided into one or more excitation waveform RAMs 24. others
Therefore, the waveform start address register 43 stores the start address T
OP is supplied to a comparator 46 to compare with the address R.
U. If the start address TOP is larger than R,
A selection signal for reading the excitation waveform from the waveform RAM 24
Generates SEL = 1. The key-on register 42 stores the key-on
Generates a key-on signal KON that rises at
The signal is supplied to the address detection unit 47 and the AND circuit 53. En
The address detector 47 detects the address read from the current memory.
Part (A) of the address and the waveform end address register 44
Receive the end address END (B) supplied by
When they match, a signal E for stopping waveform reading
NDP = 1 is generated, and AND is generated via the inverter INV.
It is supplied to the circuit 51. That is, the end of the read waveform
Until the address is reached, ENDP is "0" and
"1" is supplied to the command circuit 51. The AND circuit 51 operates while ENDP = 0.
The frequency number FN supplied by the wave number register 41 is
It passes through and is supplied to the adder 52. The adder 52 has a key
While the ON signal KON exists, its output signal is ANDed.
The signal is supplied to the register 56 via the path 53. Register 56
Are output to the adder 52. That is, the read address up to the previous time is
The signal supplied from the channel register 56 to the adder 52 is
Frequency number F supplied from wave number register 41
N is added and a new read address is
Stored in the register 56. Channel register 56
Registers for the number of channels
_sOperates in a time-sharing manner. Read address supplied by adder 52
Is added to the top address TOP by the adder 54,
The integer part INT becomes the address and the excitation waveform ROM2
3 or the excitation waveform RAM 24, and the fractional part F
The RAC is supplied to the interpolation unit 26. That is, the waveform reading is performed at the frequency number.
This is performed for each frequency number FN supplied by the
You. When a high tone is generated, the FN is large and a low temperature is generated.
Sometimes FN is small. The excitation waveform has a fixed length,
After reading the shape, the reading of the excitation waveform stops.
You. The waveform end address register 44 stores the end of the excitation waveform.
Generates END indicating end address and detects end address
To the unit 47. Integer of physical address formed by adder 54
When the unit reaches the end address, the end address detection
The output unit 47 detects a match, sets ENDP = 1, and performs an AND operation.
The function of the road 51 is stopped. The circuit shown in FIG. 3 basically operates in a time division manner.
As if there were independent circuits for multiple channels.
Operate. Therefore, each register is reserved for the number of channels.
Has been obtained. Referring to FIG. 4, the circuit shown in FIGS.
The operation will be described. In FIG. 4, the timing
Lock signal φ_sIt is shown. Timing clock signal
No.φ _sIn synchronization with channel slot signals 1 to N
Vary between. When the channel slot signal is "1"
The first sounding channel is assigned, and the channel slot
When the reset signal is N, the Nth channel is assigned. In the figure, the key-on signal KON is shown at the third stage.
Have been. In the state shown, the second channel
This shows a case where a key-on signal has been assigned. Top ad
Corresponding to the address TOP and end address END
Corresponds to the tone assigned to this second channel.
This shows the start address and the end address of the excitation waveform. What
If the key-on signal is also present on other channels,
Is the part corresponding to each channel
The corresponding start address and end address are displayed simultaneously.
You. The frequency number FN is the sound of the musical tone to be generated.
Data corresponding to high frequency.
Given by percent. And based on this frequency number FN
The integer part and the decimal part of the relative address signal.
You. Add the prior application address TOP to the relative address
The integer part INT and the decimal part FRAC of the physical address are formed.
You. The integer part INT of the physical address is an end address.
When the signal becomes equal to the dress END, the signal ENDP rises.
Rise up. After ENDP = 1, new excitation waveform
Is not read. When key-off is performed, key-on signal K
ON becomes "0". After KON = 0, the signal E
NDP becomes "0". Silence processing according to key-off
Need to set ENDP to "1" disappears
That's why. The selection signal SEL is a waveform read address.
Is the top address TOP of the address greater than the address R?
Changes the signal. As shown in the timing chart of FIG.
Control signals for N channels are formed in a time-division manner,
And the waveform reading control unit is operated. FIG.
The excitation waveform read out in time division
In a timing chart that shows how
is there. In the figure, the timing clock signal φ_sShows
The next row shows the channel slot signal, and each
Excitation waveform signals W1, W2, ..., W corresponding to the channels
n. Read in the first slot of a certain cycle
The excitation waveform is stored in the waveform distribution unit shown in FIG.
With the excitation waveform read from other slots in the cycle
Is supplied to the sound channel corresponding to. The period of the timing clock signal is Tφ_sWhen
Then, in the case of N channels, the sampling period is N ·
Tφ_sBecomes In this way, multiple sound channels
A new waveform is given for each sampling period,
The synthesis of the tone signal is performed. Each sound channel 18 is, for example, one
It can be constituted by a semiconductor integrated circuit chip.
This sound channel chip stores a large amount of excitation waveforms
Because it is not necessary to do so,
P can perform more complicated arithmetic processing. In the above description, the CPU
Control signal passes through the initial waveform generator 16 and
Channel, but an initial waveform is generated from each sounding channel.
It is also possible to pass control signals to live parts.
You. The CPU 12 has an initial waveform generator 16 and
What timing and what
You only need to give an instruction on whether to extract the excitation waveform
Data transfer time.
Wear. In addition, tone changes can be easily changed by address switching.
Can be performed at the same time as
Dynamic voice to set meter to assigned channel
Easy allocation (DVA)
You. The initial waveform generator 16 outputs a large amount of excitation waveform data.
Data must be stored, but the process is
It is mainly extruded and its contents are simple and small. each
The sound channel has a simple configuration consisting only of DSP and RAM.
Although feasible, the process is complex and bulky. As described above, a plurality of tone signals are combined.
The circuit that forms the excitation waveform generator and a loop circuit type arithmetic processor
The structure of the excitation waveform generator is
Can be shared and simplify hardware configuration
You. In addition, in the arithmetic processing unit, the burden is reduced.
Therefore, more complicated arithmetic processing can be performed. The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example,
Those skilled in the art can make various changes, improvements, combinations, and the like.
Would be obvious. [0070] As described above, according to the present invention,
Quickly combine multiple tone signals with a simple hardware configuration
Loop-type electronic musical tone signal synthesizer
Is provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a functional configuration of an electronic musical tone signal synthesizing apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram showing a hardware configuration for realizing the functional configuration of FIG. FIG. 3 is a block diagram illustrating a more detailed configuration of a control unit and a waveform readout control unit in the configuration of FIG. 2; FIG. 4 is a timing chart for explaining the operation of the circuits shown in FIGS. 2 and 3; FIG. 5 is a timing chart for explaining the operation of the circuits shown in FIGS. 2 and 3; FIG. 6 is a block diagram showing a configuration of an electronic musical tone signal synthesizing device according to a conventional technique. [Description of Signs] 1 system bus, 2 control unit, 4 excitation waveform readout unit, 5 waveform memory, 6 sounding channels, 7 loop circuit, 8 adder, 9 I /
O, 11 system bus, 12 CPU, 1
3 ROM, 14 RAM, 15 I / O,
16 Initial waveform generator, 18 sound channels,
19 adder, 20 digital / analog converter, 21 control unit, 22 waveform readout control unit,
23 excitation waveform ROM, 24 excitation waveform RAM,
25 selector, 26 interpolation unit, 28 timing clock generation unit, 29 waveform distribution unit, 32
DSP, 33 RAM, 41 frequency number register, 42 key-on register, 43 waveform start address register, 44 waveform end address register, 46 comparator, 47 end address detector, 51, 53 AND circuit, 52, 54
Adder, 56 registers

Claims (1)

(57) [Claims 1] A plurality of tone signal processors each constituting a loop circuit type tone signal synthesizing circuit including a delay means and a filter means as independent sounding channels, and a plurality of excitations A memory means for storing waveforms, which is common to all the sounding channels, and an excitation waveform which is independently read out for each sounding channel from the memory means, and selectively read out by a corresponding one of the plurality of tone signal processors. An electronic tone signal synthesizing apparatus, comprising: an excitation waveform generating unit including a memory reading unit that can be supplied; and a control unit that controls the plurality of tone signal processors and the excitation waveform generating unit in synchronization with each other.