JPS58218173A - Bidirectional power high speed mosfet element - Google Patents

Bidirectional power high speed mosfet element

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Publication number
JPS58218173A
JPS58218173A JP58080252A JP8025283A JPS58218173A JP S58218173 A JPS58218173 A JP S58218173A JP 58080252 A JP58080252 A JP 58080252A JP 8025283 A JP8025283 A JP 8025283A JP S58218173 A JPS58218173 A JP S58218173A
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JP
Japan
Prior art keywords
region
base
base region
main
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58080252A
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Japanese (ja)
Other versions
JPH0612823B2 (en
Inventor
ミツチエル・スチユア−ト・アドラ−
ピ−タ−・バンズ・グレイ
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General Electric Co
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General Electric Co
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Publication of JPS58218173A publication Critical patent/JPS58218173A/en
Publication of JPH0612823B2 publication Critical patent/JPH0612823B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】[Detailed description of the invention]

発  明  の  背  娼 本発明は電力用p金属−酸化物−半導体電界効果トラン
ジスタ(MO3FLIに関Jるもので、更に詳しく舊え
ば、同期整流回路用途におい°C有用でありかつ低いオ
ン抵抗、早いスイッチング速度、高い耐電圧性能および
交流回路用の二方向性を示づような上記素子に関する。 電力用M Q S F E T素子は、高いゲートイン
ピーダンス、低いオン抵抗(従って低い順方向電圧降下
)、高い耐電圧性能J3よび早いスイッチング速度をは
じめとJる数多くの有利な特性を有し−Cいる。適当な
ゲートを設
BACKGROUND OF THE INVENTION The present invention relates to a p-metal-oxide-semiconductor field effect transistor (MO3FLI) for power use. The above device exhibits switching speed, high voltage withstand performance and bidirectionality for AC circuits. Power MQS FET devices have high gate impedance, low on-resistance (and therefore low forward voltage drop). It has many advantageous properties, including high withstand voltage performance and fast switching speed.

【ノれば、通常のl) N整合形整流器、シ
ョットキー接合形整流器またはバイポーラ1〜ランジス
タ同期整流器のごとき素子が従未使用されでいた同期整
流回路用途においてミノj、:1::1゜ 用M OS F−E l’素子牽使用りることができる
。電力用M OS F E T素子は、上記素子のいず
れと比     )べ°Cも幾つかの利点を有しCいる
。たとえば[)N接合形整流器は、極性の逆転に際して
蓄積電荷が完全に除去されなりれはη油状態が終わらな
い/jめ、比較的高い順り自重圧降下(0,75V以上
)および比較的遅いスイッチング速葭を右づる。ショッ
1〜キー接合形整流器ぐはメイツゾング速度の問題は実
質的に解決されるが、順り自重圧降干の問題は僅かしか
緩和されない。実際、大電流−トにおりるショットキー
接合形シリ丁1ン素子の順り自重圧降下は約0.5V以
上r:ある。ショク1〜キー接合形の素子はまた、逆バ
イアス111に比較的大ぎい漏れ電流を生じるため、一
般に逆目1止能力が欠如しCいる。 公知の電力用M OS Fド1構造におい(は、一般的
に菖って単一の半導体ウェーハ」−に多数の中位ヒルが
形成されでいる。その場合各素子は300ミル(0,3
インチ)平乃稈度の\J法を右づ“るのが通例ぐあって
、各素子中の全(のセルは電気的に並列接続され−Cい
る。個々の単位セルに関しては各種の幾何学的形状が用
いられるが、相7iに入り組んだくし形構造を成゛すの
が通例である。典型的な電力用MO8FEI−は二重拡
散構造の−bのCあって、これはたとえばN形半心体月
利の共通ドレイン領域を含んぐいる。トレイン領域の内
部には、好ましくは拡散によって1〕形のベース領域が
形成されている。次いで、ベース領域の内部に完全に含
まれるようにしくソース領域が形成されている。このソ
ース領域はドレイン領域と同じにN形ぐある。素子の表
面においCは、ベース領域はN形のソース領域とドレイ
ン領域との間にP形半導体材料の帯状部として存在して
いる。かかる帯状部を覆うようにしで、MO8FETゲ
ート絶縁層および導電性ゲート電極が配置されCいる。 動作に際しては、適当な極性(N形チャンネルMOS 
I= E−rの場合には正)のゲート電圧をグー1〜電
極に印加すると、ゲート絶縁層を貫通してベース領域内
に広がる電界が発生づる。その結果、ベース領域の表面
の直下には薄いN形導電層が誘起され、それによってソ
ース領域とドレイン領域との間には連続した低抵抗のN
形心電チャンネルが形成される。実際のソース端子およ
びトレイン端子は素子の上方および下りの主面上に設置
された金属被膜から成っ(い(、トレイン端子は全(の
単位レルに対しく共通である。イれ故、かかる素子は縦
形素子と見なりことがC゛きる。ただし、ゲート電極の
制御上にある穫電チ1/ンネルの部分Cは電流は水平方
向に流れるのひある。 このJ、うな電力用MO3I−m+構造の場合、ソース
、ベースおよびドレイン領域は寄生的バイポーラ1−ラ
ンジスタのエミッタ、ベースおよび薯しクタに(れそれ
該当づる。公知の通り、電力用MO81−E ’Iの動
作中にこのような奇住的バイポーラ1〜ランジスタが導
通状態になると、電力用MO8F−F−「の阻止電圧J
3よびターンオフ速度は実質的に低下する。電力用MO
8FEIの動作中に寄生的バイポーラトランジスタが導
通状態になるのを防止り“るためには、ソτ;、スおよ
びベース領域を構成する層同士をオームml続手段にJ
、つ−(電気的□ に接続(りなわら短絡)、シ、イれによっtMOsトE
1の阻止電圧およびターンオノ速度の維持を図るのが通
例である。しかしながら、かかる短絡部のli tlは
ある種の回路中にお4Jる素子の利用を制限りる。なt
!′なら、このような素子構造においでは、M OS 
F E−1−の主端子(づなわらソースJ5よびドレイ
ン端子)間に直接に接続された奇生的なPN接合形ダイ
A−ドが木質的に含まれることになるからである。たと
えば、上記に略述したJ、うなN形チVンネルエンハン
スメントh式のMOS F [E l構造の場合には、
P形ベース領域が素子のドレイン領域との間にPN接合
面を形成づる。 ソース−ベース間短絡部の存在により、事実上、P形ベ
ース領域は素子のソース端子に対して電気的に接続され
る。勿論、N形ドレイン領域は素子のトレイン端子に接
続されている。その結果、陽極がM OS I−E I
のソース端子に接続されかつ陰極がMO8FEI−のド
レイン端子に接続された寄生的なP N接合パ′形ダイ
オードが存在覆ることにな8゜     ・会、。 電気回路中に□゛するN形チャンネルMO8F[王の通
常の動作に際しては、ドレイン端子はソー   1ス端
子に対しで正にバイアスされる。エンハンスメント6式
のMOSFETについで述べれば、グー1−電L「が印
加されない場合にM OS F l−’l素子は田止状
態にあり、従っCソース端子とトレイン端子との間には
ほとんど電流が流れ4rい。正のグー1へ電圧の印加に
J、っC素子をターンオンさt!IC場合、N形のチャ
ンネルが誘起され、従−)(ソース端子とドレイン端子
との間には素子を貫通しく連続的なN形の導電路が形成
される。このような情況の下Cは、ベースd3よびドレ
イン領域から成る奇生ダイオートは常に逆バイアスされ
るためにいかなる影響も及ぼさない。りなわt5、タイ
Δ−ドの陰極(MO8Fト1のドレイン領域)はダイA
−トの陽極(MOS F E l’(7)ヘ−)、a3
J、ヒソース領域)に対して常に正に保lこれる。しか
るに□、ソース端子とトレイン端子どの間に印加される
電圧の極性が逆転し、それによつCベース+I5よびド
レイン領域から成るダイオードが順バイアスされた場合
、(当業者には自明のごとくに印加電圧がダイオードの
順lj向導電曲線の屈曲貞に相当りる約0.6Vより高
ければ)ゲート電圧が存在しなく(−も素子を通って電
流の伝専が起こる。そのJ、うな場合には、事実上、M
 OS F、E 1索了は逆り向の供給電圧に対づ−る
短絡路を成す。従来のMO3F[I素子がこ、のような
公知の特性を有する結果、ある種の回路(特に交流回路
)においCそれらを使用りることは容易ぐない。いずれ
の極性の供′給電圧に対しCも動作し宥るMO8Fトl
素子が存在ηれば、それらは実際の回路用途にJ3いて
極めてh’ Jll ”rあろうと考えられる。 片−J−Jと一監−J− そこで本発明の目的の1つは、M OS F Elの高
速スイッチング動作に際してバイポーラトランジスタを
はじめどりる内部の寄生素子の動作が抑制され、しかも
二方向性(1なわちソース端子とドレイン端rとの間に
いfれの極性の供給型F[が印加され(も動作し得る性
質)を示づような電力111 M OS F E T素
子を提供J−ることにある。 また、ゲー]〜端子が極性には関係なく素子の導電性を
完全に制御し1qるような電力用M OS F ET素
子を提供づることも本発明の目的の1つぐある。 更にはだ、いずれの極性の動作に関しくb耐電J、t、
オン抵抗およびスイッチングj*度が同じ(″あるよう
な完全な対称性を示す二I)向性の電力用MOSトド−
1−素子を提供りることも本発明の目的の1つである。 本ti明の第1の特徴に従っ(簡単にjホベれば、従来
のM OS Fトドにおいてこれまで心数とされ−Cき
Iこソースーヘース間短絡部が1)1除8れる結果、従
来の電力用M OS F E 1−にJ5い(ソース端
子とドレイン端子との間に実効的に接わCされCい!ご
寄生的なP N接合形ダイA−ドが排除されることにな
る。これまで使用され′Cきtc9.υ組部が存在し4
cい状態において寄生的パイポニラトランジスタの動作
を抑制するため、M OS F++ 1晃了の内部には
過剰の多数キャリA7に対し・そ比較的短かいスf命を
付与Jる11J結合領域が含ま適る。一実施態様に従え
ば、かかる再結合領域は゛Z−ス領域の内部に形成され
る。当業者には自明のごとくバイポーラトランジスタの
通常の動作に際しCは、ベース領域内の過剰キャリヤが
長い寿命を右Jることが要求される。たとえばN I’
) N形バイポーラ1−ランジスタの通常の動作に際し
く−は、■ミッタの空間電荷層を横切っCべ、−ス領域
内に電子が注入される。 これらの電子の大部分は、へ−ス領域の多数キVす−7
(正孔)と再結合りることなく、ベース領域を横切って
=ルクタ領域に流入づる。とは言え、多少の再結合は起
こるから、素子を通る電流の伝導を維持するためにはベ
ース領域の多数キャリヤ(正孔)を連続的に供給覆るこ
とが必要である。 本発明の場合のように、たとえば短かい寿命を石りる結
果としCベース領域の多数キャリ翫7の総数が制限され
ると、NPN形バイポーラ1〜ランジスタの動作は抑制
される。要するに、本発明は寄生的バイポーラトランジ
スタを排除覆るのではなくそれを導電性の極? tJs
さい素子に変えようとするものである。  、・ □ 特に重要なりob?E1素子、のターンオフ時には、電
子なだれ現象およびソース端子とドレイン端子どの間の
電圧の急、激な]−冒により、ベース領域内に多数キャ
リヤ(正孔)が生成される傾向がある。このような場合
にも、寿命を一1分に短かく(lことえば所望されるM
(、)j;II+素子のターン37時間の115稈度に
)づれば、それらの多数キレリ\7(正孔)は/1−成
されるのと実質的に同じ速度で消滅(づなわら電子とr
l+ Nr1合)りることになる。 I[J結合領域内にdハノる寿命を短かくりるには、当
業者にとって公知である任意適宜の手段を使用りればよ
い。一般的な手段の1つは、深い準11′)の不純物(
たとえば金や白金)を添加りることである。別の一般的
な手段は、放射線傷害の使用に1、−)でシリコンの結
晶格子構造中に欠陥を生じさけることである。いずれの
場合にも、多数二I tす\ンの寿命のみが変化する心
電形および濃度は実r1的に変化さけなくC湾むのであ
る□。 本発明の第2の特徴に従−)’C簡単に述べれば、−3
9電形(たとえばN形)を承り1対の主端子領域および
それらを隔離する反対導電形の半導体ベース領域を含む
半導体基板から成り、しかし上記のベース領域によっ−
C規定されたM OS l−E ’lチトンネネル面、
にJ5いCはベース領域が主端子領域の間(こ反対導電
形の帯状部としC存在りるよう4家二力向性の電力i 
M OS F L: l−素子が提供される。 かかる素子は、拡散技術によっ−(′#A造された完全
に対称的なシレー火影素子ぐあることが好ましい。 詳しく述べれば、ベース領域は主面を右りるーh、Hい
に離隔した主端子領域はベース領域の内部に形成されか
つ(れJ、りも小さい横方内床がりおよび深さをhしC
いる。また、主端子領域は主面内に終端を持った外周面
を有し−Cいる。M OS F E]チャンネル面上に
はベース領域を覆うようにしてグー1〜絶縁層が配置さ
れ、またグー1〜絶縁層上には導電性のグーミル電極が
配置される結果、グー1〜電圧の印加時には主端子領域
間に広がる導電チャンネルが誘起きれることになる。主
端子領域間に位@りるベー ス領域の内部に含まれた再
結合領域がベース領域の多数キャリ17に対し゛C比較
的短かい寿命を付与することにより、多数キャリ〜7の
濃度が過大になることが防止される。その結果、主端子
領域およびベース領域が寄生的バイボーラI−ンンジス
タどしC動作することは抑制され、また゛電力用MO8
t−F+素TのターンAノに際しくはl\−ス領域内の
過剰の多数キVす\’ hXX連速再結合づることによ
って素子の迅速なターンAノが達成される。かかる好適
4jシレーノー形(ず4造の揚台、I11重合鎖域(,
1主端子領域の深ひに少なくとも近似した深さまe広が
るように形成される。 本発明の別の実施態様に従っ(筒中に述l\れば一導電
形の中間端子領域を含/uだ半導体基板から成る二方向
性かつ対称性の電力用M OS 1−IE l素子が提
供される。かかる中間端子領域は従来のごとき二重拡散
構造の縦形電力用MO3ILI素了のドレイン領域にほ
ぼ該当するものであり(、主面を右しくいる。中間端子
領域内には、イれより−し小さい横り内焦がりa3よび
深さを有しかつ反対導電形を承り1対の互いに離隔した
ベース領域が□七:1゜ 形成され(’iljす、そし゛にれらのベース領域は主
面内に終端を持った外周面を右しCいる。ベース領域内
には、1記の一導電形をポリ一対の主端子F、ji M
がそれぞれ形成されCいる。主端子領域の各々は主面内
に一終端を持ちかつ対応するベース領域の外周面の内側
に離隔して位置りる外周面を有りる結果、主面内に(I
:liい(G、!、ベース領域がその各々に対応りる主
端子領域ど中間端子領域との間に反対導電形の帯状部ど
しく存在り゛ることになる。 各々の主端子領域とぞれに対応゛りるベース領域との間
にはオーム短絡部が形成され(いる結果、各々の主端子
領域、それに対応りるベース領域、および中間端子領域
が寄生的バイポーラトランジスタとし−C動作りること
は抑制される。 互いに離隔しI(ベース領域の間においCは中間端子領
域の内部に1tJ結合領域が含まれ−(い“C、ベース
領域の深さに少なくとも近似した深さまで広がっている
。かかる再結合領域は、中間端子領域の多数キャリA7
′、に対し゛C比較的短い寿命をイ」与ず□ るv 、h c 、、h vv り一数1゛ノー11度
h゛過人14′るのを防止する。そ、の結果としC1互
いに離隔したベース領域J3よび中間端子領域が寄生的
バイボー   4ラトランジスタとして動作りることが
抑制されるから、中間端子領j或内の過剰の多数キVす
17は急速LL、 11j結合し、従っ4電力用MO8
lil素fのターンオフに際しC迅速なターンAノが達
成されることになる。 r適な貿IM ”l  ノ+t2 開 本発明の新規な特徴は前記特許請求の範囲中に詳細に示
され(いる。とは8え、本発明の構成a5J、ぴ内容は
添f=Jの図面に関連しく述べられる以下の詳細な説明
を読むことによつC−Ni良く理解されよう。 以後の説明におい(は、使宜土、本発明の電力用M O
S F E l素子はN形シリJン半19体ソース領域
およびドレイン領域と1)形シリー1ン21′導体のベ
ース領域とをイjFlるN形チャンネルM OS I−
E1′奉子どしC記載される。どはbえ、全ての活性領
域が記載の場合と反対の導電形を承りものであってしよ
いことは勿論である。史にまlご、本明細書中に記載さ
れる特定の素子はブレ〜す拡散技術によっ−CWA造さ
れたものであることが好;)、しいが、−どの他の素子
構造(たとえばV−MO8形素子椙造)を有するものも
本発明の範囲内に包Cされることを理w1リベさく・あ
る。 先ず第1図を見ると、1)形のベース領域12を含みか
つ主面14.を右り−る半導体基板上に形成されIこ二
方向性かつ対称性の電力用MO3F[+素子10が示さ
れ(いる。ベース領域12の内部には、それよりも小さ
い横方自店がりおよび深さを有する1対のhいに離隔し
たN+形主端子領域16および18が形成され−(いる
。主端子領域16d3よび18が主面14内に終端を持
った外周面20および22をそれぞれ石りる結果、主面
14内におい−Cは、ベース領域12の一部がくいずれ
もN″形の)主端子領域16おJζび18の間に1〕形
の帯状部24としC存在りることになる。主端子領1[
16a3よび1ε3には金属被膜から成る1対の主端子
電極26d3よび28がそれぞれオーム接触しCおり、
かつ素子の主端子30おJ、び32にそれぞれ接続され
Cいる。 MOSトE−l素子の基本構造を完成Jるため、主面1
4−Fには帯状部24を覆うようにし−((たとえば二
酸化シリ−]ンから成る)ゲート絶縁層34が配置され
、またグー1〜絶縁h′り3 /I−1には少なくとも
横1ノ向に沿いながらベース領域の帯状部24を覆うよ
−)にしく(たどえば蒸着アルミ−ラムま/Sは高淵麿
の不純物が添加されl、:置型率の高い多結晶′itシ
リ二1ンから成る)導電111のゲート電極36が配置
8れ−Cいる。このグー1へ電極、′36は素子のゲー
ト端子38に接続され(いる。 以上の結果としUN形チャンネル−」ンハンスメン1−
ツノ式のMOS「[l素子 b<規定されることになる
。ここまぐに記載されたよ・)な基本的MO81−1:
、 I素子の動作につぃく述べれば、ゲート電極36に
正のグー1〜電圧が印加された場合、グー1−絶縁層3
4を貴通しでl\−スgi城12内に広がる電界が発生
り−る。その結果、’4...−1−絶縁層34 J>
よびゲート導電4fi36の下方にイ年、置する主面1
4の直下に薄い反転層(づなゎらN″形の脣電ヂ鵞・ン
ネル)が誘起される。この上う1・しC誘起されlこチ
I7ンネルは、N1形の主端子領域16および18の間
に導電路を形成りる。正のグー1〜電圧が印加されな【
ノれば反転層は存在μず、従っC対称的な主端子領域1
6および18の間に位置りる部分のベース領域12は阻
止領域を構成】る。 第1図かられが、る通り、素子1oは主端子領域16お
よび1Bに関し−C完全に対称的ひあり、従っC素子の
主端子30および32に関し−Cも完全に対称的である
。素r1oは、主端子領域16または18とベース領w
t12との間にオーム短絡部を全く含んでいないから、
二方向性の動作用とし“C適し−(いる。すなわら、素
子1oの主端子30     ゛および32間にはいり
゛れの極性の動作電圧も印加することが可能である。従
来のM OS F E T−に関する命名法との一員、
性を保つため、端子3oはソース/ドレイン(S、 /
 D ) N子と呼び、また端子32はドレイン/ソー
ス(D/S)端子と呼ぶこ) とにづる。すなわら、第2図の等何回路を参照づ1) ればわかる通り、端1:子32が端子3oに対し−C正
□ である場合には、端−i’、、30をMOS にE1の
ソース端子と見なしかつ端子32をM OS F [E
 ’rのド     ルイン端子と見なり−ことができ
る。逆に、端子30が端子32に対して正ぐある場合に
は、端子3Oをドレイン錫;了と見なしかつ暢:イ32
をソース端子と見なりことがぐきる。なJ5、ベース領
l或12に対りる直接の電気的接続」段は存在しくいな
い。 第1図の素子構造(こJ3い(は1り・1の奇9的4j
1〕N接合形ダイA−ドが存在づ゛るが、これらのタイ
オードは第2図中においC−f、れで゛れ40および4
2としC示されCいる。ダイA−ト40は、グイA−ド
の陰極領域を構成するN″形の主端子領域16およびタ
イオードの陽極領域を構成りる1−)形のベース領域1
2によって形成されCいる。同様にダイオード42は、
ダイオードの陰極領域を構成りるN+形の主端子領域1
8djJ、びダイオードの陽極領域を構成り−るベース
領1戟12によ−)−(形成され(いる。このように、
ベース領域12は両方の奇生ダイオード40および42
の陽極を構成しCいる。 素子10の動作に際しCは、奇生ダイA−ト40 J>
よび42は素子10のソース娼;了とトレイン端子どの
間に短絡路を形成しない。’tL ’IL”lら、それ
らのタイオードは背中合Uに接続されCいるl〔め同時
に尋通状態となることがないからである。 第1図に示され、IC素子10の主端子領域16、ベー
ス領域12および主端子領域18が寄生的なN 11 
N形バイポーラトランジスタの1−ミッタ、ベースa3
よびコレクタ領域とし−Cそれぞれ作用し/jす、ある
いは奇(ト的なNPN形バイポーラ1〜ランジスタのコ
レクタ、ベースおよび1ミツタ領域とじ一〇それぞれ作
用したりりるのを防止りるため、主端子領域16J3よ
び18の間にa5い−Cはベース領域12の内部に再結
合領域44が含まれCいる。 かかる再結合領域44は、破線46によって示されるご
とく、主面14から主端子領域16および18の深さに
少なくとも近似した深さまで広がっている。(主端子領
域の深さが・等しくない場合には各々の主端子’?jf
A域の位置において再結合領域は隣接づる主端子領域の
深さに少なくとも近似した深さまで広がるようにづれば
よい。)再結合領域 。 44内の再結合中心はX印によって示されている。 これらの再結合中心は金や白金のごとき深い単位の不純
物の原子ノ〕口ら成つCいC1:1J、いし、あるいは
故銅線傷害にJ、つCシリ゛−1ン21′導体の結晶格
子811 iM中に生じた欠陥から成つ−CいCもよい
。fの結果、III結合領域/I4はベース領域の多@
Aレリレ(P形ベース領域12の揚台には正孔)に対し
て比較的短かい心向をイ」与し、従つC多数キセリA7
の濃度が過大になるのを防止りるために役分つ=ぞれに
より、主端子領域16J3J、び1ε3どべ〜ス卯1或
12とが’に7牛的なバイポーTl71−ランジスタと
しく動作りることは抑制される1、史にまた、電力用M
 OS Fト1素子10のターンΔノ時には、電子なだ
れ減少や主端了領bib’ 16 d3 J、び1B間
の電圧の悠激なF胃によ−>’C/IE’成されるベー
ス領域内の過剰の多数キャリ\・は急;速にlj結合ま
たは消滅。、□□、よ−) −U i 71 cal)
□・1(7) i’B iI tl、−アオ、が):i
′呂 達成される。      :、ll’l’i。 素子の迅速なターンオンを達成りるためには、町結合領
域44内における多数キー・すAlの寿命を所望のター
ンオフ時間の115程度にりることが必要ぐある。たと
えば、M OS F E ’I素子10を50ナノ秒で
ターンオンさけるためには、再結合領域44内の寿命を
10ツノ秒以下にまC低減させる必要がある。史に高速
の素子を得るためには、再結合領域44内の寿命を1ナ
ノ秒にまC低減さけることも意図される。かかる寿命を
所望のレベルに調節りるICめには、金や白金のごとき
重金属を添加づるか、あるいは電子線やガンマ線のこと
き放射線を使用すればよい。 動作につい−C述l\れば、第1および2図の素子10
の主端子領域16および18間における導電性は、いず
れかの極性の電圧をグーh端子38に印加することによ
つ−C制御される。素子10は、交流サイクル中の任意
の時点において、素子に対りる極性にかかわりなくター
ンオンおよびターンオ/ ’t’ 6 ;l t h、
IC、、!6’、 ’ *−Fl 0 ’i” * ’
93+j3 V ftiI k:、<、、 するlこめには1.:・7− l一端子38に印加され
る電圧が主端子30およ1び32のいずれに対しくも正
とならなくりればよい。また、素子10を導通状態  
 □1にりるIこめには、主端子30および32のうら
で負の側の端子に対しで止どなるようなグー1〜電圧を
印加りれ(、C゛よい。 ′;81 a3よび2図の素子10は /J向竹か′〕
対象性の電ツノ用MO3fL−1素子を侶成りるとは言
え、ベース領域12内の阻止領域が完争に1端子領域1
Gおよび18の間に位置しCJ>す、しかbぞの距離が
素子の導通時に誘起されるN形尊゛市ヂレンネルの良さ
に一致づるという事実が不利益をもたら1可能性もある
。すなわら、所望の耐電圧性能を索fにイリ与づるため
には主端子領域16J>よひ18の間隔を一1分に人さ
くしなりれば’eK 1−If;いが、この要請を満た
(うとりればグー1〜電t4+、 36の下ツノに位置
りるMO8F−Elチレンネル領域が過大4fものどな
ることムある。 次に第343よび4図を見ると、別の実/11!i態様
に基づく二方向性かつ対称性の゛電力用M OS l−
ヒ1素子50が小され−Cいるが、これは第143よび
2図の素子が杓づる上記の欠点を解消りるもの(゛ある
。素子50は、従来のごとさ13・1の縦形MO8FE
I−単イ*、1ル52 J>よび54を背中合せの状態
で対称的に配置前しかつドレイン領域56を共イ1する
ように形成したしのと見なりことがCきる。なお、ドレ
イン領域5Gは中間端子領域として役立つだけCあって
1.いかなる端子にも白接には接続され−(いない。M
O8FET単位セル52 J−3よび54の各々は、上
記に略述しIこJ、うな電力用MO8F E 1−素子
に関りる公知技術に従っ(ソース領域とベース領域どの
間にオーム短絡部を有している。 更に詳しく)ホベれば、N形の中間端子領域5〕6の内
部には、それよりも小ざい横方自店がりおよび深さをイ
Jりる1対のUいに離隔したP形ベース領域58および
60が2つの単位セル52および54に3・1応して形
成されている。ベース領域58および60は、中間端子
領域の主面内に終端を有する外周1iii 62および
64をそれぞれ右し℃いる。 ベース領域58および60の内部には1対の主端子領域
66J3よび67が形成されCいるが、その各々は従来
のごとき二重拡散構造の縦形電力用 。 M OS FE Tのソース領域にほぼ該当している。 しかしながら、主端子領域66および67は素子の主端
子70および71に交れそれ接続されIこ金属被膜の電
々→l6(3おJ、び60を個別にイJりる点に顕茗な
相違がある。(従来の電力用M OS F L ’Iに
おいCは、電極68および691ii1 ’、1が電気
的に接続されて甲−のソース端子を構成りるの(′ある
。 )主端子領域66J3よび67の各々はNl形のものC
あり、しかも主面65内に終端を持らかつイれそれに対
応りるベース領域b 8 (13J、び60の外周面6
2および64の内側に離隔しく位置りる外周面72およ
び73をそれぞれ+JCJる結果、主面65内において
【ま、ベース領域5)8および60がその各々に対応り
る主端子領域66および67と中間端子領[56との間
に反対心電形の帯状部としC存/l IJることになる
。このJ、・う4f椛造の揚台には、主端子領域66ま
/jは67、ベース領llA38まだは6,0、および
中間端で領域5(5が1対の奇生的なN r) N形バ
イポーラ・、、、’llr’l、’v、ンジスタの」−
ミッタ、ベースおよび=ルクタ領1iにぞれそ゛れ該当
りることがわかる。更にまlC1これらの領域は主端子
電極68および69の間に位(?78Jる奇生的なN 
P N l) N形五層スイッチング素子よI〔はリイ
リスタを規定りることもわかる。寄生的リーイリスタは
導通状態にラッ、ブされる傾向があるから、第3図のM
 OS l= E ’T’素子の動作にλ・jす゛るそ
れの効果は寄生的バイポーラ1〜ランジスタの効果より
も一層有害となる場合がある。 第3図の素子中におりる」−記のごとき奇生的バイポー
ラトランジスタまたは寄生的り゛イリスタの動作を抑制
りるため、主端子領域66および67とその各々に対応
りるベース領域58および60どの間に1対のA−ム短
組部74d3よび75が形成されている。かかる:t−
1,s短絡部74および75は任意所望の方法によって
形成り−ればよい。第3図は通常の形成方法を例示づる
ものであって、ベース領域58およl′び60のそれぞ
れの延長部7、・: 6および78が主面(35にまで達して主端子電極・1
1゜ 68および69にそむぞれ接触し、その結果として主端
子領域66・および67に(れぞれオーム接     
11触しCいる。延長部76および7Bを形成1−るに
は、従来通り、先ずアクしブタ形の不純物を中間端子領
域56内に拡散さけ(1)形のベース領域58 C3よ
び(ジ0を形成し、延I(部76おj、び78の位置に
C5りる表面655Fに拡散ンスク用の小さなス1〜リ
ップ(図小t!f)を配置し、1〜ノー形の不純物を拡
散さl!’U N+形の主端r領域66J5よび67を
形成し、それから拡散マスク用のス1〜リップを除去り
ればよい。 ベース領域の延長部76および7と3の形成を必要とし
ないよ・うな種類のオーム短絡部7’lおよび7F)を
使用りることもぐきる。−例を挙(yれば、金属被膜の
主端子電極68および(59から主端子領域66おJ、
び67をそれぞれ貫通し−(部分的にl\−ス領域58
および60内にまCそれぞれ達りるマイク[1ア11イ
ースパイク(mlCr0al IOV Sp!ke)を
使用することかぐきる。あるいはまた、主端子領域66
J3よび67をイれぞれ貫通し−CCペースbりi58
および60内にま′c(れぞれ達づるV字溝選択的1ツ
ブングによって形成し、次いC両fjの領域とオーム接
触するようにしC金属被膜の主端子領域68および69
をV字溝の内部にそれぞれ形成しでもよa)oこれら2
つの方法は、1982年1月4[1に提出されかつ本発
明の場合と同じ譲受人に譲渡された「一体化され!ごソ
ース−ベース間短絡部を具備゛りる自己整合形電力用M
O8FL−]およびイの製造り法」と称りる米国特許出
願第336.972号明細書中に一層訂しく記載されC
いる。 M OS F lヨー1−レル52および54の構造を
完成りるため、主面65上にはベース領域の帯状部を覆
うにうにしCグー1〜絶縁層80および82がそれぞれ
配置され、まI〔ゲート絶縁層80および82上にはベ
ース領域の帯状部を覆うようにして導電性のゲート電極
84および86がそれぞれ配置されている。導電性のグ
ー1〜電極および86は共通のゲート端子88に対して
電気的に接続されている。 第3図かられかる通り、ベース領域58、中間端子領域
56およびベース領b:i!60は寄生的なP  。 N +)形バイポーラトランジスタを構成づるが、これ
が動作りると電力用M OS E I= T素子50の
特性(特にターンΔ)速1身)が低1・りる。その上、
かかる奇lL的な1.) N P形バイポーン1〜ラン
ジスタは主端子領域66または67ど結合してR「生白
なN r3 N +)形四層スイッヂング素子を形成り
ることらあるが、これはオン状態まA: 4eL導通状
態にラッチされることがある。これらの奇生素子の動作
を抑制りるため、!lいに離隔したベース領域5E′)
、および60の間におい(は中間端子領域56の内部に
第1図の再結台頭1t44とほば同等な再結台頭1或9
0が形成されCいる。かかる111結合領域90は、破
線92によつ−C示されるごとく、ベース領域5)8お
よび60の深さに少なくとも近似しIこ深さにまぐ広が
つCいる。再結合領域90内の714結合中心はX印に
よって示さ゛・れτいる。再結合領域90は中間端子領
域の多数□キ鵞・すA7(この場合には電子)に対し−
(比較的短・・かい寿命を付りし、従11 って多数キトす1)のil1度b<1人にtするのを防
止りるIこめに役立つ。それにより、−1−記の場合と
木質的に同様にし−C1互いに離隔しIごベース領域5
8および60と中間端子領域56とが寄生的なバイポー
ラ1〜ランジスタどして動fL Jることは抑制される
。これはまた、上記のごとぎN P N r)形四層ス
イッヂング素子q) #JJ作を抑制することにもなる
。 第4図の電気的等価回路を見ればわかる通り、第3図の
素子Jfii造は1対の奇生的なF) N接合形ダイオ
ード94および96を含んでいる。第2図の等価回路の
場合と同様にこれらのダイオード94および96は背中
合Uに接続されている。その結果、両りのダイオードが
同時に導通状態となることはないから、主端子70およ
び71間に印加される電ローの極性がいずれの場合であ
っても素子の動作が可能となる。詳しく述べれば、ダイ
オード94は[)形のベース領域58およびN形の中間
端子領域56により形成されていて、これらはダイオー
ドの陽極J已よび陰極領域をそt′それ構成6ている。 同様にJ′:1、ダイオード96は1−〕形のベース領
域60およびNj←の中間端子領域56により形成され
ている。このように、中間端子領域56は寄   ・1
生的なPN接合形ダイオード94および96対して共通
の陰極領域を構成しでいる。 第3図の九了中にJ)′()るM OS 1−[−”ル
ル52J3よび七)4のソース−ベース間知組部74 
i15 J、び75)は、第4図中では導線98 J5
よび100によっ(それぞれ表わされ(いる。λ(1絹
部7/1J3J、び75は、ベース領1iA58および
00内にそれぞれ存在する過剰の正孔を除去することに
より、ソース、ベースおよび中間端子領域が寄生的バイ
ポーラ1〜ランジスタどし−(動作りることを防止り°
るのに役立つ。また再結合領域90は、この領域内に存
在りろ過剰の電子を再結合ざけることにより、2つのベ
ース領域58および60と中間端f領域5)6とが奇生
的な1.) N l”形バイポーラl−ランラスタとし
て動作りることを防止づるのに役立゛つ。 その結果としC第3図の素子50は、いずれの極性の電
圧が印加され−(いl”b素子の導電性がグー1一端子
88によって効果的に制御Iされるような対称性のスイ
ッヂング素子とし−C動作りる。素子のゲート端子88
に印加される゛電圧が素−fのいずれかの主端子に印加
される負側よりも負ぐある限り、いずれのMOSFET
−チVンネルも導通状態にはならす゛、また背中合lの
タイオード9/Iおよび96によっC素子50中にJ5
りるその伯の電流伝導も防止される。。グー1一端j’
 88に印加される電圧を正のh向に十分なたりk W
u Qければ、素子50は導通状態と4する。 最後に、第5図は本発明のより一般的な着想に基づ〈実
施態様を示しCいる。図示され1=電力用MO8FET
・素子110は三方向性を示4が、対称性は示さない。 それぐも、第5図の非対称性素子110は第1図の対称
性素子10とほぼ同等のものである。全体的に見ると、
第5図の素子110は二重拡散構造の縦形電力用M O
S F [T素子に類似しているが、ソース−ベース間
短絡部が存在しない代りにベース領域内に再結合領域1
44が含まれる点e異なつCいる。 更に詳しく述べれば、素子110はそれの本体を成リド
レイン領域118とその内部に拡散形成されたN4形の
ソース領域116との間にP形のベース領域112を含
んぐいる。ドレイン領域118は、たとえば1ビタキシ
ヤル成長により、N1形の基根119圭に形成されCい
る。基&119は素子の]端子132に接続8れ(いる
が、この主情rはトレイン2/ソース端]′としく役立
つもの(゛ある。素r110のその他の41−1成要鋒
、は第1図の素子10の構成要素にほぼ対応し−(いる
3、それらの対応4る構成要素は、第5)図中C・は、
第1図中の参照数字に100を加えた参照数字によっ(
表わされている。 以上、バイポーラ1−ランジスタをはじめとリ−る内部
寄生累イの動作が抑制されるJ、うな−ニノ゛)向性の
電力用MO8FEI−素子を説明した。かかる素子は対
称性を承りから、耐電圧、オン抵抗おJ:びスイッヂン
グ速度がいずれの極性の動作に関しCも同じである。ゲ
、−1〜端子は、極性に関係なく素子の導電性を完全に
制御りる:′□ことが可能Cある。 :。 本明細害中には本発明の特定の実施例が記載さ□、2o
い。ヵ81.−□1.%。数’j”’、1や<、、)□
1.ヶ□122、可能であることは当業者にとつく自明
であろう。 それ故、前記特許請求の範囲は本発明の精神J5よび範
囲に反しない限り全てのかかる変形実施例をも包括する
ことが意図されている点を理解リベきである。
[If it is, it is normal l) In synchronous rectifier circuit applications where elements such as N matching rectifiers, Schottky junction rectifiers, or bipolar 1 to transistor synchronous rectifiers have not been used previously, mino j, :1::1° MOS F-E I' elements can be used. Power MOS FET devices have several advantages over any of the above devices. For example, an N-junction rectifier has a relatively high self-weight pressure drop (above 0.75 V) and a relatively Slow switching speed to the right. Although the Schott-Key junction rectifier substantially solves the speed problem, it only slightly alleviates the dead weight drop problem. In fact, the self-weight pressure drop of a Schottky junction type silicon element subjected to a large current is about 0.5 V or more. Key junction type devices also generally lack reverse locking capability due to relatively large leakage currents in the reverse bias 111. In known power MOSFET structures, a large number of medium hills are formed on a single semiconductor wafer (generally on a single semiconductor wafer), where each device is 300 mils (0,3
It is customary to use Hirano's \J method, in which all cells in each element are electrically connected in parallel. A typical power MO8FEI has a double-diffused structure, which is similar to, for example, an N-type. A common drain region of the semi-central body is formed inside the train region, preferably by diffusion.Then, a base region of the shape of 1 is formed, preferably by diffusion. A source region is formed in the same manner as the drain region.The source region is N-type like the drain region.C on the surface of the device is a base region of P-type semiconductor material between the N-type source region and the drain region. A MO8FET gate insulating layer and a conductive gate electrode are arranged so as to cover the strip. During operation, an appropriate polarity (N-channel MOS
When a gate voltage (positive if I=E-r) is applied to the electrode, an electric field is generated that penetrates the gate insulating layer and spreads into the base region. As a result, a thin N-type conductive layer is induced just below the surface of the base region, thereby forming a continuous low-resistance N-type conductive layer between the source and drain regions.
A shaped electrocardial channel is formed. The actual source and train terminals consist of metal coatings placed on the upper and lower main surfaces of the device (the train terminal is common to all unit rails of the device). can be regarded as a vertical element. However, the current flows horizontally in the part C of the power channel 1/channel that is under the control of the gate electrode. In the case of the structure, the source, base and drain regions are parasitic bipolar transistors (respectively). When the bipolar transistor 1~ transistor becomes conductive, the blocking voltage J of the power MO8F-F-
3 and the turn-off speed is substantially reduced. MO for power
In order to prevent the parasitic bipolar transistor from becoming conductive during operation of the 8FEI, it is necessary to connect the layers constituting the source, base and base regions to each other using ohmic connections.
, t-(electrical short-circuit), tMOst E
It is customary to maintain a blocking voltage of 1 and a turn-on speed of 1. However, such short circuits limit the use of 4J elements in certain circuits. What?
! ', then in such an element structure, M OS
This is because an anomalous PN junction diode A-de connected directly between the main terminals (source J5 and drain terminals) of F E-1- is included in a wooden manner. For example, in the case of the J, N-type channel enhancement h type MOS F [E I structure outlined above,
A P-type base region forms a PN junction with the drain region of the device. The presence of the source-to-base short effectively connects the P-type base region electrically to the source terminal of the device. Of course, the N-type drain region is connected to the train terminal of the device. As a result, the anode becomes MOS I-E I
There is now a parasitic PN-junction diode connected to the source terminal of MO8FEI- and whose cathode is connected to the drain terminal of MO8FEI-. During normal operation of an N-channel MO8F in an electrical circuit, the drain terminal is positively biased with respect to the source terminal. Regarding the MOSFET of Enhancement Type 6, when no current is applied, the MOSFET is in a static state, and therefore there is almost no current between the C source terminal and the train terminal. flows 4r.When a voltage is applied to the positive G1, the J,C element is turned on.If the IC is N-type channel is induced, and there is an element between the source and drain terminals. A continuous N-type conductive path is formed through C. Under these circumstances, C does not have any effect because the parasitic diode consisting of base d3 and drain region is always reverse biased. Wt5, the cathode of the tie Δ-de (drain region of MO8Ft1) is connected to die A
- anode (MOSF E l' (7)), a3
J, hysose region). However, if the polarity of the voltage applied between the source and train terminals is reversed, thereby forward biasing the diode consisting of C base + I5 and the drain region, then (as is obvious to those skilled in the art) If the voltage is higher than about 0.6 V, which corresponds to the curvature of the diode's forward conduction curve, then there is no gate voltage (-) and current conduction occurs through the element. is, in fact, M
The OS F, E1 lines form a short circuit to the opposite supply voltage. As a result of the known characteristics of conventional MO3F devices, it is not easy to use them in certain types of circuits (particularly AC circuits). MO8F transistor that C also operates for supply voltage of either polarity.
If such elements exist, it is conceivable that they would be extremely useful in actual circuit applications. Therefore, one of the objects of the present invention is to During the high-speed switching operation of F El, the operation of internal parasitic elements such as bipolar transistors is suppressed, and moreover, the supply type F The object of the present invention is to provide a power 111 MOS FET element which exhibits a property of being able to operate even when [is applied to it]. It is also an object of the present invention to provide a power MOSFET device that can be completely controlled.
Directional power MOS devices with the same on-resistance and switching degree (showing perfect symmetry)
It is also an object of the present invention to provide a 1-element. According to the first feature of this invention (simplified explanation), as a result of dividing the number of cores in the conventional MOSFET by dividing the number of cores by 1 (1), J5 is connected to the power MOSFET (effectively connected between the source terminal and the drain terminal)! The parasitic P-N junction type diode is eliminated. There is a set of 'Ctc9.υ that has been used so far, and 4
In order to suppress the operation of the parasitic piponilla transistor in a low state, there is a 11J coupling region inside the MOS F++ 1 which gives a relatively short lifetime to the excess majority carrier A7. Includes. According to one embodiment, such a recombination region is formed within the Z-space region. As will be appreciated by those skilled in the art, normal operation of a bipolar transistor requires that excess carriers in the base region provide a long lifetime. For example, N I'
) During normal operation of the N-type bipolar 1 transistor, electrons are injected across the space charge layer of the emitter into the C base region. Most of these electrons are located in the base region, where the majority of the electrons are located.
It crosses the base region and flows into the lucta region without recombining with (holes). However, some recombination does occur and a continuous supply of majority carriers (holes) in the base region is necessary to maintain current conduction through the device. If, as in the case of the present invention, the total number of multiple carry rods 7 in the C base region is limited, for example as a result of short life, the operation of the NPN bipolar transistors 1 to transistors is suppressed. In short, does the invention eliminate parasitic bipolar transistors rather than covering them with conductive poles? tJs
It is an attempt to change it to a small element. ,・ □ Particularly important ob? When the E1 element is turned off, majority carriers (holes) tend to be generated in the base region due to the electron avalanche phenomenon and the sudden and drastic change in voltage between the source terminal, drain terminal, etc. Even in this case, the lifespan can be shortened to 11 minutes (in other words, the desired M
According to the 115 culm degree of turn 37 hours of II+ element), those large numbers of holes are annihilated (and become electrons) at substantially the same rate as /1- are created. r
l + Nr1). Any suitable means known to those skilled in the art may be used to shorten the lifetime of d in the I[J bond region. One of the common measures is to introduce deep quasi-11′) impurities (
For example, adding gold or platinum). Another common approach is to use radiation damage to avoid creating defects in the crystal lattice structure of silicon at 1,-). In either case, the electrocardiogram shape and concentration, of which only the lifespan of the majority 2 I t \ \ \ \ , change, actually change r1 and become C □ . According to the second feature of the invention -)'C Briefly stated -3
9 conductivity type (for example, N type) and includes a pair of main terminal regions and a semiconductor base region of opposite conductivity type separating them;
C defined MOS l-E 'l chitunnel surface,
In J5C, the base region is between the main terminal regions (this is a strip of opposite conductivity type, and C exists in the 4-wire bidirectional power i).
MOS F L: l-element is provided. Such an element is preferably a perfectly symmetrical Schiller element constructed by diffusion techniques. In particular, the base region is spaced very far to the right of the principal surface. The main terminal area is formed inside the base area and has a small lateral internal floor and depth.
There is. Further, the main terminal region has an outer circumferential surface having an end within the main surface. MOS F E] On the channel surface, Goo 1 ~ insulating layer is arranged so as to cover the base region, and a conductive Goo mill electrode is placed on Goo 1 ~ insulating layer. As a result, Goo 1 ~ voltage When is applied, a conductive channel extending between the main terminal regions will be induced. The recombination region contained within the base region located between the main terminal regions provides a relatively short lifetime to the majority carriers 17 in the base region, thereby increasing the concentration of the majority carriers ~7. Excessive size is prevented. As a result, parasitic bipolar I-N transistor operation in the main terminal region and base region is suppressed, and the power MO8
When turning A of the t-F+ element T, a rapid turn A of the element is achieved by rapid recombination of an excess of multiple kisses in the l\- space region. Such a suitable 4j Sileno type (Z4 structure lifting platform, I11 polymer chain region (,
It is formed to extend to a depth e that is at least approximately the depth of one main terminal region. In accordance with another embodiment of the present invention, a bidirectional and symmetrical power MOS 1-IE element consisting of a semiconductor substrate (including an intermediate terminal region of one conductivity type in the cylinder) is provided. Such an intermediate terminal region almost corresponds to the drain region of a conventional vertical power MO3ILI with a double diffusion structure (with the main surface facing to the right). A pair of mutually spaced base regions having opposite conductivity types and having a lateral internal burnout a3 and depth smaller than that of the base region are formed □7:1°, and then their The base region has an outer circumferential surface with a terminal end in the main surface.In the base region, one conductivity type listed in 1 is connected to a pair of main terminals F, ji M.
are formed respectively. Each of the main terminal regions has an outer peripheral surface having one end in the main surface and spaced inwardly of the outer peripheral surface of the corresponding base region, so that (I
:li (G,!), the base region exists as a strip of opposite conductivity type between the corresponding main terminal region and intermediate terminal region. An ohmic short circuit is formed between each main terminal region, its corresponding base region, and the intermediate terminal region as a parasitic bipolar transistor, resulting in -C operation. A 1tJ coupling region is contained within the intermediate terminal region between the base regions I(I) and extends to a depth at least approximating the depth of the base region. This recombination region is the majority carrier A7 in the intermediate terminal region.
, which gives a relatively short life span to v , h c , h vv , and prevents overheating by 11 degrees. As a result, since the base region J3 and the intermediate terminal region separated from each other are suppressed from operating as parasitic bibolar transistors, the excessive number of transistors in the intermediate terminal region J is rapidly reduced. LL, 11j coupled, so MO8 for 4 power
Upon turn-off of lil element f, a rapid turn A will be achieved. The novel features of the disclosed invention are shown in detail in the claims. C-Ni will be better understood by reading the following detailed description given in conjunction with the drawings.
The S F E l element is an N type channel M OS I- which connects the source and drain regions of the N type silicon conductor and the base region of the 1) type silicon conductor.
E1'BengzidoshiC is described. However, it is of course possible for all active regions to have conductivity types opposite to those described. For the record, it is preferred that the particular devices described herein are fabricated by the Brass diffusion technique - CWA; however - any other device structure (e.g. It is understood that devices having a V-MO8 type element (Suzukuri) are also encompassed within the scope of the present invention. Turning first to FIG. 1, 1) a base region 12 of the shape and a major surface 14. A bidirectional and symmetrical power MO3F element 10 is shown formed on a semiconductor substrate with a smaller lateral self-containing structure inside the base region 12. A pair of closely spaced N+ type main terminal regions 16 and 18 are formed having a depth and depth. As a result, a part of the base region 12 is separated from the main terminal region 16 (both of which are N" shaped), and a strip-shaped portion 24 of the shape C exists between the main terminal regions 16 and 18 of the main surface 14. Main terminal area 1 [
A pair of main terminal electrodes 26d3 and 28 made of a metal film are in ohmic contact with 16a3 and 1ε3, respectively.
and are connected to main terminals 30, J and 32 of the element, respectively. In order to complete the basic structure of the MOS element, the main surface 1
A gate insulating layer 34 (made of silicon dioxide, for example) is disposed on the band 4-F so as to cover the strip 24, and at least a horizontal The vapor-deposited aluminum lamina/S is doped with Takabuchi's impurities, so that it covers the strip 24 of the base region along the direction of the base region. A gate electrode 36 of conductive conductor 111 (consisting of 21 electrodes) is arranged 8-C. The electrode '36 is connected to the gate terminal 38 of the element.
The basic MO81-1 of the horn-type MOS "[l element b< will be specified. It was described here]:
, To describe the operation of the I element in detail, when a positive Goo 1 to voltage is applied to the gate electrode 36, Goo 1 to the insulating layer 3
4 through you, an electric field is generated that spreads inside the l\-Sugi Castle 12. As a result, '4. .. .. -1- Insulating layer 34 J>
and the main surface 1 placed below the gate conductor 4fi36.
A thin inversion layer (N''-type electric current channel) is induced directly under the N1 type main terminal region 16 and the N1 type I7 channel. A conductive path is formed between positive goo 1 and no voltage applied.
If it is, there is no inversion layer μ, and therefore C-symmetrical main terminal region 1
The portion of the base region 12 located between 6 and 18 constitutes a blocking region. As can be seen from FIG. 1, element 1o is -C perfectly symmetrical with respect to main terminal regions 16 and 1B, and therefore -C is also perfectly symmetrical with respect to main terminals 30 and 32 of the C element. The element r1o has the main terminal region 16 or 18 and the base region w.
Since it does not include any ohmic short circuit between it and t12,
It is suitable for bidirectional operation. In other words, it is possible to apply operating voltages of both polarities between the main terminals 30 and 32 of the element 1o. Member with nomenclature regarding FET-
In order to maintain the
D) It is called the N-terminal, and the terminal 32 is called the drain/source (D/S) terminal. In other words, as can be seen by referring to the circuit shown in Fig. 2 (1), when terminal 1: child 32 is -C positive □ with respect to terminal 3o, terminals -i', , 30 are connected to MOS. , the terminal 32 is considered as the source terminal of E1 and the terminal 32 is considered as the source terminal of E1.
It can be viewed as a drop-in terminal for 'r. Conversely, if the terminal 30 is right with respect to the terminal 32, the terminal 3O is not considered to be the drain terminal and the terminal 32 is normal.
It can be seen as a source terminal. There is no direct electrical connection to the base region 1 or 12. The element structure in Figure 1 (this is
1] There are N-junction diodes A-, and these diodes are C-f in FIG.
2 and C are shown. The diode 40 has an N''-shaped main terminal region 16 constituting the cathode region of the diode and a base region 1 of the 1-) shape constituting the anode region of the diode.
2 formed by C. Similarly, the diode 42 is
N+ type main terminal area 1 that constitutes the cathode area of the diode
8djJ, and the base region 12 constituting the anode region of the diode.
Base region 12 includes both parasitic diodes 40 and 42
It constitutes the anode of C. During operation of the element 10, C is a strange die A-40 J>
and 42 do not form a short circuit between the source terminal and the train terminal of device 10. This is because these diodes are connected back to back and are not in the interrogation state at the same time. As shown in FIG. 16, base region 12 and main terminal region 18 are parasitic N 11
N-type bipolar transistor 1-mitter, base a3
In order to prevent the collector, base and collector regions of the NPN bipolar transistor 1 to act on the collector, base and collector regions, respectively, the main terminal Between the regions 16J3 and 18, a recombination region 44 is included within the base region 12. The recombination region 44 extends from the main surface 14 to the main terminal region 16, as shown by a broken line 46. and extends to a depth at least approximating the depth of 18 (if the depths of the main terminal regions are unequal, then
At the position of area A, the recombination area may extend to a depth that is at least close to the depth of the adjacent main terminal area. ) recombination region. The recombination center within 44 is indicated by an X. These recombination centers are composed of deep unit impurity atomic holes such as gold and platinum (C1:1J), or J,C series-1 (21') conductors due to damage to the old copper wire. -C which is made up of defects generated in the crystal lattice 811 iM is also good. As a result of f, the III binding region/I4 is the base region multi@
It gives a relatively short centering direction to the A current (holes on the platform of the P type base region 12), and therefore gives a relatively short center direction to the A current
In order to prevent the concentration of 1. In history, electric power M
At the time of turn Δ of OS F1 element 10, the electron avalanche decreases and the base formed by 'C/IE' is caused by the gradual increase of the voltage between the main terminal area bib' 16 d3 J and 1B. Excess majority carries in the region are rapidly combined with lj or annihilated. , □□, yo-) -U i 71 cal)
□・1(7) i'B iI tl, -ao, ga):i
'ro is achieved. :,ll'l'i. To achieve rapid turn-on of the device, it is necessary that the lifetime of the multi-key Al in the bond region 44 be on the order of 115 times the desired turn-off time. For example, in order to avoid turning on the MOS F E 'I device 10 in 50 nanoseconds, the lifetime within the recombination region 44 must be reduced to less than 10 nanoseconds. In order to obtain an extremely high speed device, it is also intended to reduce the lifetime in the recombination region 44 by as little as 1 nanosecond. To adjust the lifetime of the IC to a desired level, heavy metals such as gold or platinum may be added, or radiation such as electron beams or gamma rays may be used. Regarding the operation, the element 10 of FIGS. 1 and 2
The electrical conductivity between the main terminal regions 16 and 18 of is controlled by applying a voltage of either polarity to the terminal 38. The element 10 is turned on and turned off at any point during the AC cycle, regardless of the polarity to the element.
IC...! 6', ' *-Fl 0 'i' * '
93+j3 V ftiI k:,<,, 1. :・7- It is sufficient that the voltage applied to the l-terminal 38 is not positive to any of the main terminals 30 and 1 and 32. Also, the element 10 is in a conductive state.
□Apply a voltage of 1 to 1 to 1 to 1 which stops at the negative side terminal behind the main terminals 30 and 32. Element 10 in the figure is /J Mukaitake']
Although the MO3fL-1 element for electric horns is symmetrical, the blocking area in the base area 12 is completely limited to one terminal area 1.
The fact that the distance between CJ and B, located between G and 18, corresponds to the quality of the N-type electromagnetic wave induced during conduction of the element can also be disadvantageous. In other words, in order to obtain the desired withstand voltage performance, the distance between the main terminal regions 16J and 18 must be made as small as 11 minutes. (If you fill it up, the MO8F-El channel region located at the lower corner of 36 will be excessively 4f.) Next, looking at Figures 343 and 4, another real 11! Bidirectional and symmetrical power MOS l- based on the i aspect
The element 50 is made smaller in size, which eliminates the above-mentioned drawbacks of the elements in FIGS. 143 and 2.
It can be seen that the drain regions 56 are formed so that the drain regions 56 and 54 are symmetrically arranged back to back. Note that the drain region 5G serves as an intermediate terminal region and has 1. No terminals are connected to white junctions.
Each of the O8FET unit cells 52 J-3 and 54 is constructed in accordance with the known art related to power MO8F E1 devices as outlined above (with an ohmic short between the source region and the base region). In more detail), inside the N-shaped intermediate terminal area 5/6, there is a pair of U holes with smaller lateral openings and depth. P-shaped base regions 58 and 60 spaced apart are formed in 3.1 correspondence with the two unit cells 52 and 54. The base regions 58 and 60 have outer peripheries 62 and 64, respectively, which terminate in the major plane of the intermediate terminal region. A pair of main terminal regions 66J3 and 67 are formed within the base regions 58 and 60, each of which is a conventional double diffused vertical power terminal. This almost corresponds to the source region of the MOS FET. However, a notable difference is that the main terminal regions 66 and 67 are intersected and connected to the main terminals 70 and 71 of the device, and the metal-coated electrical terminals 66 and 67 are separately connected. (In the conventional power MOS F L'I, C is the main terminal area where the electrodes 68 and 691ii1', 1 are electrically connected to constitute the source terminal of A-). Each of 66J3 and 67 is of Nl type C
The base area b 8 (13J, and the outer circumferential surface 6 of 60
As a result of adding +JCJ to the outer circumferential surfaces 72 and 73, which are located at a distance inside the base regions 2 and 64, respectively, the main terminal regions 66 and 67 corresponding to the base regions 8 and 60 are formed within the main surface 65. A strip of opposite electrocardiogram shape is formed between the terminal area and the intermediate terminal area [56]. In this J, U4F Kakuzo's lifting platform, the main terminal area 66 or j is 67, the base area llA38 is 6,0, and the area 5 at the middle end (5 is a pair of paranormal N r) N-type bipolar...'llr'l,'v,indister'-
It can be seen that this corresponds to the mitta, base, and lucta regions 1i, respectively. Furthermore, these regions are located between the main terminal electrodes 68 and 69 (~78J).
P N l) It can also be seen that the N-type five-layer switching element I [defines the relay resistor. Since parasitic resistors tend to be latched conductive, M in FIG.
OS l=E 'T' Its effect on the operation of the device may be more detrimental than the effect of the parasitic bipolar transistor. In order to suppress the operation of parasitic bipolar transistors or parasitic iris transistors such as those shown in FIG. 60, a pair of A-me short assembly parts 74d3 and 75 are formed between them. Takes: t-
1, s short-circuit portions 74 and 75 may be formed by any desired method. FIG. 3 illustrates the usual method of formation, in which the extensions 7, . 1
1° 68 and 69 respectively, resulting in main terminal areas 66 and 67 (ohmic contact, respectively).
11 touches C. To form the extensions 76 and 7B, as is conventional, first active, pig-shaped impurities are diffused into the intermediate terminal region 56, the (1)-shaped base regions 58C3 and (J0) are formed, and the extensions are formed. A small slip (small t!f in the figure) for diffusion is placed on the surface 655F of C5 at the positions of portions 76, 78, and 78, and the impurities of type 1 and no are diffused. It is sufficient to form the main end r regions 66J5 and 67 of the U N+ shape, and then remove the slips 1 to 1 for the diffusion mask. It is also possible to use different types of ohmic short circuits 7'l and 7F).
and 67 respectively.
It is possible to use a microphone [1A11E spike (mlCr0al IOV Sp!ke) that reaches within 60 and 60 minutes respectively. Alternatively, the main terminal area 66
Pass through J3 and 67 respectively - CC pace bi58
and 60 are formed by V-shaped grooves selectively extending into each other, and are then brought into ohmic contact with the regions of both C and fj of the main terminal regions 68 and 69 of the metal coating.
may be formed inside the V-shaped groove respectively a) o These 2
One method is a self-aligned power source with an integrated source-to-base short circuit, filed on January 4, 1982 and assigned to the same assignee as the present invention.
08FL-] and C.
There is. To complete the structure of the MOSFl yaw 1-rels 52 and 54, insulating layers 80 and 82 are disposed on the main surface 65 to cover the strips of the base region, respectively. I [Conductive gate electrodes 84 and 86 are disposed on the gate insulating layers 80 and 82, respectively, so as to cover the strip-shaped portion of the base region. The conductive electrodes 1 to 86 are electrically connected to a common gate terminal 88 . As can be seen from FIG. 3, the base region 58, intermediate terminal region 56, and base region b:i! 60 is parasitic P. N+) type bipolar transistor is constructed, and when it operates, the characteristics of the power MOS E I=T element 50 (particularly the turn Δ speed) are low. On top of that,
Such a bizarre 1. ) The N P type bipone 1 to the transistor may be connected to the main terminal region 66 or 67 to form an R (N r3 N +) type four-layer switching element, but this is in the on state or A: 4eL may be latched in the conductive state.In order to suppress the operation of these parasitic elements, the base region 5E') is spaced very far apart.
, and 60 (inside the intermediate terminal area 56, there is a recombination pad 1 or 9 that is almost equivalent to the recombination pad 1t44 in FIG. 1).
0 is formed and C is present. Such 111 bonding region 90 extends to a depth that at least approximates the depth of base regions 5) 8 and 60, as indicated by dashed line 92. The 714 bond centers within the recombination region 90 are indicated by the X's. The recombination region 90 is - for a large number of intermediate terminal regions A7 (electrons in this case).
(It has a relatively short lifespan, and is used in large numbers.) It is useful for preventing people from becoming ill. As a result, the structure is similar to the case described in -1-.
8 and 60 and the intermediate terminal region 56 are suppressed from moving due to the parasitic bipolar transistor 1 to transistor. This also suppresses the N P N r) type four-layer switching element q) #JJ production as described above. As can be seen from the electrical equivalent circuit of FIG. 4, the device structure of FIG. 3 includes a pair of parasitic F)N junction diodes 94 and 96. As in the equivalent circuit of FIG. 2, these diodes 94 and 96 are connected back to back U. As a result, since both diodes are never rendered conductive at the same time, the device can operate regardless of the polarity of the low voltage applied between the main terminals 70 and 71. Specifically, the diode 94 is formed by a square-shaped base region 58 and an N-shaped intermediate terminal region 56, which define the anode and cathode regions of the diode. Similarly, J':1, the diode 96 is formed by the 1-] type base region 60 and the Nj← intermediate terminal region 56. In this way, the intermediate terminal region 56 is
A common cathode region is provided for natural PN junction diodes 94 and 96. The source-base knowledge assembly section 74 of M OS 1-[-"Lulu 52J3 and 7) 4 during the completion of FIG. 3
i15 J, and 75) are the conductor 98 J5 in Fig. 4.
and 100 (respectively. If the terminal area is parasitic bipolar 1 to transistor 2 (prevents operation)
It will help you. In addition, the recombination region 90 prevents the recombination of excess electrons that may exist in this region, so that the two base regions 58 and 60 and the intermediate end f region 5) 6 have a parasitic 1. ) N l''-type bipolar l-run raster. As a result, the element 50 of FIG. The switching element operates as a symmetrical switching element such that the conductivity of the element is effectively controlled by the gate terminal 88 of the element.
Any MOSFET as long as the voltage applied to it is more negative than the negative side applied to either main terminal of element -f.
- channel V channel is also brought into conduction, and back-to-back diodes 9/I and 96 cause J5
Current conduction in Rurusonohaku is also prevented. . Goo 1 end j'
The voltage applied to 88 is sufficiently kW in the positive h direction.
If u Q, the element 50 is in a conductive state. Finally, FIG. 5 shows an embodiment based on the more general idea of the invention. Illustrated 1 = MO8FET for power
- Element 110 exhibits tridirectionality 4 but no symmetry. As such, the asymmetric element 110 of FIG. 5 is substantially equivalent to the symmetric element 10 of FIG. Overall,
The device 110 in FIG. 5 is a vertical power MO with a double diffusion structure.
S F [Similar to T element, but instead of having a source-base short circuit, there is a recombination region 1 in the base region.
44 is included. More specifically, device 110 includes a P-type base region 112 between a drain region 118 forming its body and an N4-type source region 116 diffused therein. The drain region 118 is formed at the base 119 of the N1 type by, for example, single-bit axial growth. The base &119 is connected to the terminal 132 of the element, but this main information r serves as the train 2/source end]'.The other 41-1 components of element r110 are the C. in the figure roughly corresponds to the components of the element 10 in FIG.
The reference numerals in Figure 1 plus 100 (
It is represented. The above describes a MO8FEI element for electric power which is oriented to suppress the operation of internal parasitic elements such as bipolar transistors. Such devices exhibit symmetry, so that the withstand voltage, on-resistance, and switching speed are the same for either polarity of operation. It is possible to completely control the conductivity of the element regardless of polarity. :. Specific embodiments of the invention are described herein, 2o
stomach. 81. -□1. %. Number 'j''', 1, <,,)□
1. It will be obvious to those skilled in the art that this is possible. It is therefore to be understood that the appended claims are intended to cover all such variations insofar as they do not depart from the spirit and scope of the invention.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に一実施態様に基づく二方向性かつ対称
性の電力用Mo5t−11素子を承り側断面図、第2図
は第1図の素子の電気的等価回路を示す略図、第3図は
本発明の別の実施態様に基づく二方向性かつ対称性の電
力用MO8FE’l−素子を示1側断面図、第4図は第
3図の素子の電気的等価回路を示り゛略図、イして第5
図は本発明に基づく二り向性かつ非対称性の電力用MO
8flr素子を承り側断面図である。 図中、10は本発明の一実施態様に基づく電力用MO8
FEr素子、12はベース領域、14は主面、16およ
び・18は主端子領域、20および22″′L%周面・
2.ニジυ1帯状部・26お、、L (728t、を主
端子電極、30お、、、、よび32は主端子、34はグ
ー1・絶縁層、36は導電性のゲート電極、38は  
  1ゲー1〜端子、44は丙結合領域、50は本発明
の別の実施態様に基づく電力用MO3FET素子、5)
2および51は中位レル、56は中間端r領域、5)E
)および00はベース領域、(52および(34はベー
ス領域の外周面、66および67は主端子領域、6ε3
 Jj J、び60は三1−÷i1:子電極、70 J
jよび71は主D装置J′、72Jiよび73は主端子
領域の外周面、74および75はオーム短絡部、76a
3よび78はベース領域の延長部、80 (I:iよび
82はグー1〜絶縁層、84および86は導?h性のグ
ー1〜電極、イしく833はグーミル端子を表ねり。 特冶出願人 ゼネラル・土しク1〜リック・カンバニイ代理人 (7
630)  生 沼 徳 ニーム刀ダ”l Iフ互)9 −f7互7/7
1 is a side sectional view of a bidirectional and symmetrical power Mo5t-11 device according to one embodiment of the present invention; FIG. 2 is a schematic diagram showing the electrical equivalent circuit of the device of FIG. 1; 3 shows a bidirectional and symmetrical power MO8FE'l-device according to another embodiment of the invention; 1 shows a side sectional view; FIG. 4 shows an electrical equivalent circuit of the device of FIG.゛Schematic diagram, number 5
The figure shows a bidirectional and asymmetric power MO according to the present invention.
FIG. 8 is a side cross-sectional view of an 8FLR element. In the figure, 10 is a power MO8 based on an embodiment of the present invention.
FEr element, 12 is a base region, 14 is a main surface, 16 and 18 are main terminal regions, 20 and 22''L% circumferential surface.
2. Rainbow υ1 band-shaped part 26o, , L (728t is the main terminal electrode, 30o, , , and 32 are the main terminals, 34 is the goo 1 insulating layer, 36 is the conductive gate electrode, 38 is the
1 gate 1~terminal, 44 is a C coupling region, 50 is a power MO3FET element based on another embodiment of the present invention, 5)
2 and 51 are middle rel, 56 is middle end r region, 5)E
) and 00 are the base area, (52 and (34 are the outer peripheral surfaces of the base area, 66 and 67 are the main terminal areas, 6ε3
Jj J, and 60 are 31-÷i1: child electrode, 70 J
j and 71 are the main D device J', 72Ji and 73 are the outer peripheral surfaces of the main terminal area, 74 and 75 are ohmic short circuit parts, and 76a
3 and 78 are extensions of the base region, 80 (I: i and 82 are the insulating layer, 84 and 86 are the conductive electrodes, and 833 is the goo mill terminal. Applicant General Satoshiku 1 ~ Rick Kanbanyi Attorney (7)
630) Raw Numa Virtue Neem Sword Da”l I Futari) 9 -f7 Mutual 7/7

Claims (1)

【特許請求の範囲】 1、(a>主面を有し、かつ前記1−面から内部に向か
っC広がる1対の一々電形の主螺−f領域を含lυだ半
導体草根、(1))前記主端子領域のイれぞれにA−ム
接触づる1対の主端子電極、(C,)前記主端子領域同
士を隔離りる反対導電形の半導体ベース領域であっC1
電界の作用下では前hd+面に隣接しながら前記主端子
領域の間に広がる前記−導電形の帯状部から成る反転層
を形成づ−るように構成されたベース領域、(+j )
 +iii記帯状記音状部ようにして前記主面上に配置
されたグー1〜絶縁層、(e )前記ゲート絶縁層上に
配置された導電性のグー1〜電極、並びに(r ) ’
+’+:i Ha主端子領域間において前記ベース領域
の内部に含まれる[り結合領域であって、前記ベース領
域の多数キレリヤに対し比較的短かい寿命をイ4りりる
ことによつC前記再結合領域内における多数キレリレの
濃度が過大になることを防止りる結果、前記主端子領域
および前記ベース領域が寄生的バイポーラトランジスタ
とし〔動作護ることを抑制し、かつまた素子のターンA
)時には前記ベース領域内の過剰の多数キャリヤを急速
に再結合さゼるのに役立つ再結合領域の諸要素から成る
ことを特徴とりる二り向性の電力用M OS F E 
T素子。 2、各々の前記主端子領域の位置にJ3い−C1前記再
結合領域が前記主面から隣接づる前記主端子領域の深さ
に少なくとも近似し7j深さまで広がる特許請求の範囲
第1項記載の電力用M、08FET素子。 3、前記再結合領域が深い準位の不純物を含有リ−るこ
とによって前記ベース領域の多数キャリヤに比較的短か
い寿命が付与される特許請求の範囲第2項記載の電力用
MO8FET0 4、前記深い準位の不純物が金および白金から成る群よ
り選ばれた1者である特許請求の範囲第3項記載の電力
用M OS F E−1素子。 5、@記再結合領域が放射線障害を有づ゛ることによっ
C前記ペース領域の多数キトす〜7に比較的短かい寿命
がイ」〜される特1.’l 1illi求の範囲第2 
Jrj記載の電力用M OSトE−1素子。 6、(a)主面を有しかつ一導電形のペース領域を含ん
だ半導体基板、(b)前、i[!l\lメースの内部に
ほぼ同じ深さまで形成され、かり前記ベース領域よりも
小さい横方自店がりおよび深さを有する1対のnいに離
隔した反対導電形の1端子領域であっC1前記主端子領
域が前記主面内に終端を持った外周面を右することにj
;す、前記主面内においては電界の作用下ぐ前記ベース
領域の一部が前記主端子領域の間に広がる前記反対導電
形の帯状部としC存在づるという:′結果をもたらす主
端子領域、(C)前記主端子領域のそれぞれにオーム接
触する1対の主端子電極□、((j)前記ベース已′ 領、域の前記帯状部を覆うJ、)にしC前記主面J−1
゜□、1,3ヶー]、ses□、)と?。)7つ、、<
。、5向に沿いながら前記ベース領域の前記化、・状部
を覆うj;うにして前記ゲート絶縁層上に配置された導
電性のゲート電極、並びに(f )前記主端子領域の間
にJ5いて前記ベース領域の内部に含まれかつ前記主端
子領域の深さに少なくとも近似した深さまで広がる再結
合領域であって、前記ベース領域の多数キレリλ7に対
し比較的短かい寿命を(=J与づることによっC前記杓
結合領域内にd3 l)る多数キャリVの濃度が過大に
なることを防止する結果、前記主端子領域J3よび前記
ベース領域が寄生的バイポーラ1〜ランジスタとしC動
作することを抑制し、かつまた素子のターンオフ時には
前記ベース′sAI!!内の過剰の多数キャリヤを急速
に再結合させるのに役立つ再結合領域の諸要素から成る
ことを特徴とする二方向性かつ対称性の電力用MO8F
El−素子。 7、前記再結合8領域が放射線傷害を有することによっ
て前記ベース領域の多数キャリヤに比較的短かいか命が
付ち1される特許請求の範聞第6項記′:1 載の電力用M OsF、、 E 1−素子。 “  へ− 8、前記再結合8領域が深い準位の不純物を含有するこ
とによって前記ベース領域の多数キャリヤに比較的短か
い寿命が(=J与される特許請求の範囲第6項記載の電
力用M OS F 1〜1累了。 9、前記深い準位の不純物が金ぐある特許請求の範囲第
8項記載の電力用MO8II+素子。 10、前記深い単位の不純物が白金Cある特許請求の範
囲第8項記載の電力用MO8)L丁素子。 11、(a)主面を有しかつ一導電形の中間端子領域を
含lνだ半導体基板、(b)前゛記中間端子領域の内部
に形成されて前記中間端子領域よりb小さい横り自店が
りおJ:び深さをイjし、かつ前記主面内に終端を持っ
た外周面を石づる1λ・1の!lいに離隔°シlご反対
導電形のベース領域、(C)各々の前記ベース領域の内
部に形成された1対の前記−導電形の主端子領域′Cあ
っC1各々の前記主端子領域が前記主面内に終端を持ら
かつ対応する前記ベース領域の外周面の内側に離隔しC
位置りる外周面を有りることにより、前記主面内におい
C電界の作用下で各々の前記ベース領域の一部が対応づ
る前記主端子領域と前記中間端子領域との間に広がる前
記反対導電形の帯状部としC存右覆るという結果をもた
らす主端子領域、(d、)各々の前記主端子領域ど対応
りる前記ベース領域との間にそれぞれ形成され、ぞしく
各々の前記主端子領域、対応ヴる前記、ベース領域およ
び前記中間端子領域lJ<、寄生的バイポーラとしC動
作Jることを抑制づるのに役立つ1対のオーム短□絡部
、((1)前記ベース領域の各帯状部を1百うようにし
−C前記主面上に配置されlこゲート絶縁層、(e )
少なくとし横方向に沿いながら前記ベース領域の各帯状
部を覆うようにしC各々の前記ゲート絶縁層上に配置さ
れた導電性のゲート電極、並びに(f)前記ベース領域
の間において前記中間端子領域の内部に含まれる再結合
領域であつC1前記中間端子領域の多数キャリVに対し
比較的短かい寿命を付与りることによって前記再結合領
域内にお()る多数キ1?すA7の濃度が過大になるこ
とを防止する結果、前記ベース領域a5よび前記中間端
子領域が寄生的バイポーラトランジスタとして勅作り−
ることを抑制し、かつまた素子のターンオフ時には前記
中間端子領域内の過剰の多数キ1Fリヤを急速に再結合
さけるのに役立つ再結合領域の諸要素から成るこどを1
h ′fiどりるニーIj向竹かつ対称性の電力用M 
O3F  li:  T i f。 12、各々の前記ベースπ1域の位置にd3い(、前記
再結合領域が前記主面り臼う隣接りる前記ベース領域の
深さに少なくとも近似した深さまぐ広がる特許請求の範
囲第11項記載の電力用M OS Fl  1 素 子
 。 13、前記角結合領域が深い準位の不純物を3右づるこ
とによっC前記中間端子領域の多数キャリA7に比較的
短かい寿命がイ]ちされる狛が1請求の範囲第11項記
載の電力用MOSトに’T素子。 14、前記深い準位の不純物が金J5よび白金から成る
群より選ばれた1者ぐある特許請求の範囲第13項記載
ノ電ノJ 11 M O8丁1−[素子。 15、前記再結合領域が放剰線傷害を右ツるこ:[:。 とによって前記中間端子領域の多数キャリVに比較的短
かい寿命が付与される′、4.許請求の範囲第11 *
、記載の電力用MO8FEr素子。
[Scope of Claims] 1. (1) A semiconductor root having a main surface and including a pair of monoelectrically shaped main screw-f regions extending inward from the 1-plane; (1) ) a pair of main terminal electrodes in contact with each of the main terminal regions; (C,) a semiconductor base region of opposite conductivity type separating the main terminal regions;
a base region (+j) configured to form, under the action of an electric field, an inversion layer consisting of a strip of the - conductivity type extending between the main terminal regions while being adjacent to the front hd+ surface;
+iii. Goo 1 to insulating layer disposed on the main surface in the manner of the band-shaped recording part; (e) conductive Goo 1 to electrode disposed on the gate insulating layer; and (r)'
+'+: A bonding region included inside the base region between the iHa main terminal regions, which has a relatively short lifespan with respect to the plurality of contacts in the base region. As a result of preventing the concentration of multiple rays in the recombination region from becoming excessive, the main terminal region and the base region are prevented from acting as parasitic bipolar transistors, and the turn A of the device is also suppressed.
) Bidirectional power MOS F E sometimes characterized by comprising elements of a recombination region that serve to rapidly recombine excess majority carriers in the base region.
T element. 2. The recombination region at the position of each of the main terminal regions is at least approximate to the depth of the adjacent main terminal region from the main surface and extends to a depth of 7j. M, 08 FET element for power. 3. The MO8FET for power according to claim 2, wherein the recombination region contains impurities at a deep level, thereby imparting a relatively short lifetime to majority carriers in the base region. 4. The power MOSFET E-1 device according to claim 3, wherein the deep level impurity is one selected from the group consisting of gold and platinum. 5. Due to radiation damage in the recombination region, a large number of the pace regions have a relatively short lifespan.1. 'l 1illi search range 2nd
The power MOSFET E-1 element described by J.R.J. 6. (a) A semiconductor substrate having a main surface and including a space region of one conductivity type, (b) before, i[! A pair of diagonally spaced one-terminal regions of opposite conductivity type formed inside the mace to approximately the same depth and having smaller lateral extension and depth than the base region. The main terminal area has an outer circumferential surface with an end within the main surface.
; In the main surface, a part of the base region under the action of the electric field exists as a band-shaped portion of the opposite conductivity type extending between the main terminal regions; (C) a pair of main terminal electrodes □ in ohmic contact with each of the main terminal regions;
゜□, 1,3 months], ses□, )? . )7,,<
. , a conductive gate electrode disposed on the gate insulating layer, and (f) a conductive gate electrode covering the base region along the 5th direction; a recombination region that is contained inside the base region and extends to a depth at least approximating the depth of the main terminal region, and has a relatively short life (=J given) with respect to the multiple sharpness λ7 of the base region. As a result, the main terminal region J3 and the base region operate as a parasitic bipolar transistor as a result of preventing the concentration of the majority carry V from becoming excessive in the coupling region by The base 'sAI! ! Bidirectional and symmetrical power MO8F characterized by consisting of recombination region elements that serve to rapidly recombine excess majority carriers within
El-element. 7. The power M according to claim 6':1, wherein the majority carriers in the base region have a relatively short life due to radiation damage in the recombination region 8. OsF,, E 1-element. 8. The power recited in claim 6, in which the majority carriers in the base region have a relatively short lifetime (=J) because the recombination region contains deep-level impurities. 9. The power MO8II+ element according to claim 8, in which the deep level impurity is gold. 10. The power MO8II+ element according to claim 8, in which the deep level impurity is platinum C. MO8) L element for power according to scope 8. 11. (a) A semiconductor substrate having a main surface and including an intermediate terminal region of one conductivity type, (b) Inside of the intermediate terminal region. The outer circumferential surface of the outer circumferential surface having a termination in the main surface is formed with a diameter of 1λ·1 and has a depth smaller than the intermediate terminal area. (C) a pair of main terminal regions of the negative conductivity type formed inside each of the base regions; C having an in-plane end and spaced apart inside the outer circumferential surface of the corresponding base region;
The opposite conductivity spreads between the main terminal region and the intermediate terminal region to which a portion of each base region corresponds under the action of the C electric field in the main surface. (d) each main terminal region is formed between each said main terminal region and the corresponding base region, preferably each said main terminal region; , corresponding to the base region and the intermediate terminal region lJ<, a pair of ohmic shorts serving to suppress parasitic bipolar C operation, ((1) each strip of the base region a gate insulating layer disposed on the main surface, (e)
(c) a conductive gate electrode disposed on each of the gate insulating layers so as to cover each strip of the base region along the lateral direction; and (f) the intermediate terminal region between the base regions. C1 is a recombination region contained within the recombination region C1 by giving a relatively short life to the majority carry V in the intermediate terminal region. As a result of preventing the concentration of A7 from becoming excessive, the base region A5 and the intermediate terminal region are formed as a parasitic bipolar transistor.
The recombination region consists of elements that serve to suppress the occurrence of oxidation and also to rapidly recombine excess multi-chip carriers in the intermediate terminal region upon turn-off of the device.
h 'fi Dori Knee Ij Mukaitake and symmetrical power M
O3Fli: Tif. 12. At the position of each base π1 region, the recombination region extends to a depth at least approximate to the depth of the adjacent base region of the main surface. 13. By causing the angular coupling region to trap deep level impurities, the majority carrier A7 in the intermediate terminal region has a relatively short lifetime. 14. The power MOS transistor according to claim 11. 14. The deep level impurity is one member selected from the group consisting of gold J5 and platinum. No. 13 described in No. 11 M O8-1-[Element. 4. Scope of Claim No. 11 *
, MO8FEr element for electric power described.
JP58080252A 1982-05-10 1983-05-10 Bidirectional power high speed MOSFET device Expired - Lifetime JPH0612823B2 (en)

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US376058 1989-07-05

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JPH02100366A (en) * 1988-10-07 1990-04-12 Fuji Electric Co Ltd Insulating gate type transistor
JPH06252407A (en) * 1993-02-22 1994-09-09 Nec Corp Semiconductor device and manufacture thereof
JP2020178049A (en) * 2019-04-18 2020-10-29 三菱電機株式会社 Semiconductor device

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EP0205637A1 (en) * 1985-06-25 1986-12-30 Eaton Corporation Trapped charge bidirectional power fet
EP0164094A3 (en) * 1984-06-08 1987-02-04 Eaton Corporation Isolated bidirectional power fet
DE19816448C1 (en) * 1998-04-14 1999-09-30 Siemens Ag Universal semiconductor wafer for high-voltage semiconductor components, their manufacturing process and their use
DE19958694A1 (en) * 1999-12-06 2001-06-13 Infineon Technologies Ag Controllable semiconductor switching element
FR2940525B1 (en) * 2008-12-18 2011-04-08 Commissariat Energie Atomique SEMICONDUCTOR DEVICE

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GB1345818A (en) * 1971-07-27 1974-02-06 Mullard Ltd Semiconductor devices
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Publication number Priority date Publication date Assignee Title
JPH02100366A (en) * 1988-10-07 1990-04-12 Fuji Electric Co Ltd Insulating gate type transistor
JPH06252407A (en) * 1993-02-22 1994-09-09 Nec Corp Semiconductor device and manufacture thereof
JP2020178049A (en) * 2019-04-18 2020-10-29 三菱電機株式会社 Semiconductor device
US11670634B2 (en) 2019-04-18 2023-06-06 Mitsubishi Electric Corporation Semiconductor device

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JPH0612823B2 (en) 1994-02-16
FR2526587B1 (en) 1987-02-27

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