JPH04196359A - Composite semiconductor device and power conversion device provided therewith - Google Patents

Abstract

PURPOSE:To obtain a composite semiconductor device where an arc is easily made to start and a parasitic thyristor hardly starts operating and which is turned ON or OFF through an insulated gate and possessed of a current limiting action by a method wherein a first and a second insulated gate electrode are electrically connected together. CONSTITUTION:An intermediate P layer of a thyristor region and a P-type well layer of a MOSFET region formed on the intermediate P layer are isolated from each other by an intermediate N layer of the thyristor region. One primary electrode is brought into ohmic contact with an P layer outside the thyristor region, and the other primary electrode is brought into ohmic contact with the source layer and the well layer of the MOSFET region, whereby the N layer outside the thyristor region and the drain layer of the MOSFET region are electrically connected together. Furthermore, a first insulated gate electrode is provided onto the well layer located between the source layer and the drain layer of the MOSFET, a second insulated gate electrode is formed on the surface of the intermediate P layer of the thyristor region, and the first and the second insulated gate electrode are electrically connected together. By this setup, a device which is easily ignited, protected against malfunction, and possessed of a current limiting action can be provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a composite semiconductor device that can be turned on and off by an N408 gate and has saturation characteristics, and a power conversion device using the same.

[Conventional technology] Conventionally, a thyristor is controlled by a MOS gate, and a MOSFE
Regarding semiconductor devices that control the current of a thyristor by the saturation characteristics of ,
EIect, ron Device Letter
s, Vol, Il, 1o2゜(February
1990) Vol, II, a2. pp, 75~
77). FIG. 9 shows the composite semiconductor device described in FIG. 9 of this paper.

In the figure, 10 is a semiconductor substrate having a pair of main surfaces 100, 101, with an upper surface [p soil layer between n1] 1 and an n
- layer 12, with exposed surfaces therein 9 layers 13 and n1+
A layer 130 is formed. An insulating film 3 is provided on the main surface 101.
An insulated gate 300 consisting of 1 and a gate electrode 32 is formed, and 010 layers 15, n, and 010 layers 16 extend from the main surface 101 into the 91st layer 131 and are formed independently so as to reach below this insulated gate 300. has been done. A p1+ layer with high carrier concentration] 30 is formed under the n2+ layer 16,
The resistance r of the layer is made small. This n1+ layer 130 and n
, the ten layers 16 are short-circuited at the cathode electrode 22.

An anode electrode 21 is in ohmic contact with the main surface 100 . This composite semiconductor device has p-soil layers 11 and n
- pnph transistors composed of layers 12, 9 layers 13 - np composed of layers 12, 9 layers 13, and n1+ layer 15
It has a built-in thyristor consisting of an n-transistor.

In addition, the insulated gate 300 and the n1+ layer 15-p layer 13.
It has an n-channel MOSFET consisting of 16 layers. Furthermore, as a parasitic element, n, 10 layers 16·p, +1
30-n-layer] Contains a parasitic thyristor made of a 2.p-substrate 11. FIG. 10 shows an equivalent circuit of the composite semiconductor device of FIG. 9. The operating principle will be described below using FIGS. 9 and 10. First, to turn on the composite semiconductor device, a negative potential is applied to the cathode terminal K and a positive potential is applied to the anode terminal A. Further, a positive potential is applied to the gate terminal G through the cathode terminal, thereby forming an inversion layer on the surface of the 9th layer 13 under the insulated gate, and forming an inversion layer on the surface of the 9th layer 13 under the insulated gate.
and l-1, + layer are short-circuited.

Under such conditions, a base current (
A Hall current (■) is caused to flow through the cathode terminal K. This hole current generates a potential difference between the resistance of the 9 layer 13 and both ends of the n1+ layer 130. When this potential difference exceeds the diffusion potential between the 9 layer 13 and the n1+ layer 5 (approximately 0.7 V at room temperature in silicon), electrons are injected from the n1+ layer 15 to the p layer 3. When the second electron ○ passes through the Yl− layer 12 and flows into the p soil layer 11, more holes ■ than the p4 layer 11 form in the 11− layer]
Inject into 2. When this hole current reaches the p layer]3 and flows to the cathode electrode 22, electrons ○ are further injected from the n1+ layer 15.
The thyristor made of the soil layer 11 is ignited (touched up), and the composite semiconductor device is turned on.

Next, to turn it off, the potential at the gate terminal G may be removed. For example, when the gate terminal G and the cathode terminal K are short-circuited, the inversion layer on the surface of the 9th layer 13 under the insulated gate disappears, and the supply of electrons ○ injected from the n10th layer]5 to the p layer]3 is cut off. , p10 layer 1], and the composite semiconductor device enters the OFF state.

The feature of such a composite semiconductor device is that by using thyristor operation, a large amount of electrons can be transferred to the high-resistance n-layer 12.
By injecting holes (1) and (2), the resistance of the core layer can be lowered, and the resistance loss during conduction occurring inside the composite semiconductor device can be significantly reduced. Moreover, it can be easily turned on and off by applying and removing a potential to the insulated gate 300. For example, there is no need to inject or draw out a large amount of current using a gate as in gate turn-off (GT○) thyristors, and the feature is that the gate circuit can be accommodated and simplified.

Furthermore, the insulated gate 300 and the n1+ layer 15/9 layer +3 (
MOSFET consisting of p, middle layer 130) and n, + layer 16
Using the saturated output characteristic (referred to as saturation characteristic) of n
It is possible to limit the electrons ○ injected from the 1+ layer 15,
Although the composite semiconductor device operates as a thyristor, it can have a current limiting effect due to its saturation characteristics. In a power semiconductor device, usually several hundred to tens of thousands of cells having the structure shown in FIG. 9 are integrated and operated in parallel. At this time, if each cell has a current limiting function, the current will not be concentrated in one cell, and each cell will share the current evenly, thereby preventing damage to the power semiconductor device due to current concentration. Although this composite semiconductor device operates as a thyristor, it has a current limiting effect, so it can achieve a uniform current flow without current concentration in the on state, and evenly reduce the current in each cell in the turn off state. It is also easy to interrupt large currents.

[Problems to be Solved by the Invention] However, the above-described composite semiconductor device has a problem in that it is difficult for electrons to be injected from the n1+ layer 101, and even ignition occurs. That is, the n1+ layer 15 is short-circuited to the cathode electrode 22 via the inversion layer of the insulated gate 300 and the n2+ layer 16, but the resistance of this inversion layer is as large as the sheet resistance, which is several Ω, and this resistance ] Blocks the current supply of electrons ○ injected from 5.

In other words, when the potential difference between the 9 layer 13 and the n1+ layer 15 reaches the diffusion potential or higher, and electrons ○ are about to be injected from the n1+ layer 15, this electron current and the resistance of the inversion layer cause the 010 layer 15 to become n intermediate layer] The potential becomes higher than 6. As a result n1
The potential difference between the + layer 15 and the 9 layer 13 becomes smaller, and injection of electrons O from the n and middle layers is suppressed, making it difficult to ignite. To prevent this, there is a method of increasing the resistance R of the 9-layer 13, but if the carrier concentration of the 9-layer 13 is made low and thin in order to increase R, the depletion layer extending to the 9-layer 13 becomes the n-layer 15. A new problem arises in that the voltage reaches and passes through, resulting in deterioration of withstand voltage. Therefore, the 010 layer 15 is used as the cathode electrode 2.
One possibility is to increase R by extending it in the direction away from 2. In this case, another problem arises. That is, it exists as a parasitic thyristor. B, middle class 16 ・
The problem is that the p-layer 130, the n- layer 12, and the p-layer 11 are likely to latch up. 9 layers 13 include p 10 layers 1
Due to the above-mentioned reason, the p-layer 11 is wide, so there are extremely large amounts of holes ■ that have arrived from the n1+ layer 15 and holes ■ that are generated to satisfy the neutrality condition of the electrons injected from the n1+ layer 15. Cathode electrode 22 through layer 130
flows into. At this time, the p1+ layer 130 has a low resistance r due to a high carrier concentration, or the hole current flowing into the p1+ layer 130 is large, so a large potential difference occurs between both ends of the resistance r.

If the potential difference between the two is greater than the diffusion potential between the p1+ layer +30 and the 020 layer 16, the parasitic thyristor will latch up. Once this parasitic thyristor latches up,
The composite semiconductor device can no longer be turned off by the insulated gate 300, and the current continues to flow, and eventually the device is destroyed by the Joule heat generated by the current and conduction loss.

As described above, the conventional composite semiconductor device does not take into consideration the large resistance of the inversion layer and the operation of the parasitic thyristor, and has the problem of being difficult to ignite and being easily destroyed.

An object of the present invention is to provide an improved composite semiconductor device that is easy to ignite, has a parasitic thyristor that is difficult to operate, is turned on and off by an insulated gate, and has a current limiting effect.

Another object is to provide a power conversion device using a composite semiconductor device.

[Means for Solving the Problems] The composite semiconductor device of the present invention that achieves the above object is characterized by a p-type layer formed in the intermediate p layer of the thyristor region and a p-type layer of the MOSFET region formed in the intermediate r) layer of the thyristor region. The well layer and the well layer are separated by the zero layer in the middle of the thyristor region, one main electrode is in ohmic contact with the p layer outside the thyristor region, and the other main electrode is in ohmic contact with the source layer and well layer of the MOSFET region. , the 0 layer outside the thyristor region and the drain layer of the MOSFET region are electrically connected, a first insulated gate electrode is provided on the well layer located between the source layer and the drain layer of the MOSFET region, and the thyristor A second layer is placed on the p-layer surface in the middle of the region.
The point is that an insulated gate electrode is provided, and the first and second insulated gate electrodes are electrically connected.

A feature of the power conversion device of the present invention that achieves the above object is that the composite semiconductor device of the present invention is used as a switching element constituting an inverter or a converter.

[Function] A composite semiconductor device having such a configuration separates the p-layer in the middle of the thyristor region and the p-type well layer in the MOSFET region by the zero layer in the middle of the thyristor region, thereby eliminating holes in the p-layer in the middle of the thyristor region. Current flows into the n-middle layer outside the thyristor region, and electron injection from the outer n-middle layer occurs smoothly, making ignition easier. Further, most of the Hall current in the thyristor region flows directly into the second main electrode, and the Hall current passing through the parasitic thyristor region is small, so that the parasitic thyristor is prevented from malfunctioning due to latch-up. Furthermore, the current flowing between the first and second main molds is mostly in the thyristor region and the MOSFET.
By flowing through a series circuit in the ET region, a device with current limiting effect can be obtained.

Furthermore, since the power conversion device having such a configuration uses the composite semiconductor device of the present invention having a current limiting effect as a switching element, it is possible to directly connect the switching elements in parallel according to the current carrying capacity, and it is extremely easy to increase the capacity. becomes.

[Example] Hereinafter, an example of the present invention will be described with reference to FIG. Second
The figure is an equivalent circuit of FIG. 1. The difference from FIG. 9 is that the 9th layer 13 in FIG.
FET well layer) 131 and 96 layers (thyristor intermediate layer) 14, each with an n1+ layer 150. n,+
The point where layer 17 was provided, and the n3+ layer 17/92 layer 14/n
- It has a MOSFET consisting of an insulated gate G2 (insulating film 33, gate electrode 34) 301 spanning the layer 12. Next, the principle of operation of the composite semiconductor device of the present invention will be explained. First, in order to turn on this composite semiconductor device, with a negative potential applied to the cathode electrode 22 and a positive potential applied to the anode electrode 21, a positive potential is applied to the insulated gates G, 300 and insulated gates G, 301 from the cathode electrode 22. Apply a potential of Then, the pl layer 13 under the insulated gate G, 300
An inversion layer (channel) is formed on the surface of the 92 layer 14 under the insulated gate G, 30], and the layer 12 is short-circuited with the cathode electrode 22. As a result, electrons ○ flow from the cathode electrode 22 to the n- layer 12, and from the p layer 1 to the hole ○
Encourage injection of Most of the holes ■ reach the 92nd layer 14, raise the potential of the 92nd layer 14 to a positive potential, and
7 causes injection of electrons O.

As a result, the conductivity of the high-resistance n-layer 12 is modulated by the holes (2) and electrons (0), and a large current begins to flow. On the other hand, to turn off the insulated gate G.

300 and G, 30] and remove the potential of pl layer 13
It is sufficient to eliminate the inversion layer in the 1, p layer 14.

The insulated gate G, 300 blocks the injection of electrons from the n,+ layer 17, and the insulated gate G, 301 also prevents the electrons from flowing into the n- layer 12 through the inversion layer. As a result, the injection of holes (2) from the p+ layer 11 also disappears, and the composite semiconductor device enters the OFF state. According to this embodiment, the hole (2) that has reached the 97th layer 14 is connected to the 92nd layer 14 and 9
Since the n-layer 12 is interposed between the 1st layer 131, 91
Therefore, the holes from the p layer 11 are injected into the n3+ layer 17, promoting the formation of the di)30 layer.

Moreover, if the 92 layer 14 is formed by completely separating it from the pl layer 131, the 92 layer 14 will be fixed at the potential of the cathode electrode 22, and p, M14 will be brought to a positive potential by the potential of the anode electrode 21. Can be lifted. As a result, 92 layers 14・n and + layer 17 are forward biased, and n5+
Injection of electrons from the layer 17 becomes easier, and the composite semiconductor device becomes easier to ignite. Also, insulated gate G
, 301, the insulated gate G, 300
By applying the same positive potential as and to the insulated gate G.

300 and G, 30] can be turned on at the same time. Therefore, it is also possible to form G1 and 62 with the same insulated gate.

FIG. 3 shows a modification of the invention. The difference from FIG. 1 is that the area where the cathode electrode 22 or the n2+ layer 22 and the 91st layer 131 are short-circuited is connected to the n, soil layer 150, and the 13+ layer] 7
- P2 layer 14 ・N- layer 1.2 ・The point provided on the thyristor region side of the p-layer 11 and the cathode electrode 22 are n1
The area where the cathode electrode 22 contacts the + layer 131 is n2.
The parasitic thyristor that existed due to the resistor r in FIGS. 1 and 2 can be eliminated by providing the thyristor region closer to the region in contact with the + layer 16. That is, even if some of the holes (2) flowing from I)+RI] flow into F)1 layer 13], they are directly absorbed into electrode 22 without passing through resistor r. Therefore, the equivalent circuit of FIG. 3 is free of parasitic thyristors as shown in FIG. 4. Furthermore, n1 10 layers +5
By moving 0 away from the thyristor region, there is also the effect that the operation of the parasitic thyristor consisting of rl, soil layer 150-p, layer 1.3], n- layer 12, and p-layer 11 can be prevented.

FIG. 5 shows another modification of the invention. Figures 1 and 3
The difference from the figure is that the insulated gate G', 301 is the n3+ layer 1.
7.92 layer 14.n-layer 1 or not pl layer 13
1, and that the insulating gate +-G, 301 is provided on the PL layer 13] side. As a result, by applying a negative potential to the insulated gate G, 301 with respect to the cathode electrode 22, the potential of the 92 layer 14, which had an undefined potential in the off state, is changed to the n- layer 14 under the insulated gate G, 301. An inversion layer is formed on the surface, and the PL layer 13] and the P2 layer]
4 can be shorted. This makes it possible to increase the breakdown voltage of the thyristor region. In other words, if the potential of the 92nd layer 14 is unstable in the off state, a positive potential is applied to the 92nd layer 14 due to the influence of the anode electrode 21, and the 97th layer 14.
n, the soil layer 17 is in a forward bias state, and the n1+ layer・pl
Layer 131 becomes reverse biased. In general, a lateral MOSFET region with an insulated gate G is constructed using several micrometers of n1,000 + 50 and n7,000 layers to reduce channel resistance.
The withstand voltage is low because they are fabricated close to each other. Therefore, there was a concern that the ml/1 pressure of the silice region would become smaller and the withstand voltage of the composite semiconductor device would also become lower. According to this example, p
Since the potential of the second layer]4 is fixed to the pl layer 13], the breakdown voltage of the thyristor region does not decrease, and the composite semiconductor device can be made to have a high breakdown voltage. Of course, pl layer 1
It goes without saying that the same effect can be obtained even if the 31 and 92 layers 14 are short-circuited in a portion of the periphery to such an extent that the ignition sensitivity is not affected. Furthermore, n, soil layer 17 and p7 layer]
By providing the n-channel inter-channel 05FET including the straddling insulated gate G and 301 on the PL layer 131 side, 97 layers 14, n- layer + 2- p1 layer]
There is an advantage that the p-channel MOSFET consisting of 31 and the n-channel MOSFET can be integrally formed.

FIG. 6 shows an equivalent circuit of FIG. A p-channel MOSFET indicated by a broken line is an added circuit in FIG.

FIG. 7 shows a modification of FIG. 5. The difference from FIG. 5 is that, in order to reduce the short-circuit resistance of the PL layer 31 below the N2+ layer 16, a p1,000 layer 133 having a higher carrier concentration than the PL layer 131 is provided. As a result, n2+ layer 16・pl, + layer 133 (p, layer] 31
)・n− layer]2・P Malfunction due to latch-up of the parasitic thyristor composed of the ten layers 11 can be more reliably prevented.

In addition, the hole ■ injected from the p layer 11 makes the p layer 13
1 can be led to the cathode electrode 22 via a low resistance path. On the other hand, in this modification, n
By providing the PL layer 132, which has a higher carrier concentration than the PL layer 131, in the 91st layer 131 below the + layer 150, the n1+ layer +50-p, the 10th layer 132 (p, layer 13
It is also possible to prevent latch-up of a parasitic thyristor formed of ]).]n-layer 12-p ten layers. Of course, pl, 10 layers]
It is also possible to form the p72+ layer 132 and the p72+ layer 132 integrally, but in that case, the pl layer 13 under the insulated gate 300
It is necessary to control the surface carrier concentration of No. 1 to, for example, about 10" to 10" scm+ so that an inversion layer is formed.

In this way, the p,2+ layer 132 and the p, , +l:3:3 may be continuous under the insulated gate G,300, and latch-up malfunctions due to parasitic thyristors can be further prevented. Furthermore, in this modification, the parasitic thyristors are present in the 01,000 layers ] 50 and n, the p 10 layers 11 below the 10 layers 16 and the D−
The point is that an n10 layer 120 is provided between the layers 2 to suppress the injection of holes 1 from the p10 layer 1. This makes it possible to block the injection of holes (2) into the parasitic thyristor region, allowing operation without parasitic effects.

In addition, an n buffer layer (
punch-through of depletion layer and n-layer]
Needless to say, a modification of the conventional technique of not trying to make the film thinner than the above-mentioned method 2 is also conceivable.

Furthermore, using the insulated gates G, , G, as masks, the n1+ layer 150 + p+y+ layer 132 . n, 10th layer 16°pl, 10th layer +33. p, layer 131, n3+
If layer 17°97 layer 14 is formed by self-line, M
The threshold voltage and structure of the OS gate can be formed with good reproducibility.

FIG. 8 shows a plan view of FIG. 7. The semiconductor layer surface 101 is shown at the top. The lower part shows a state in which the insulating film and electrodes formed on the surface 101 overlap. n1+ layer 15
0. pl layer 13], n, 10 layers] 6. p,,+1
33. n-layer 12. p, layer]4゜n,+ layer 17 is shown exposed to the surface]01 of the semiconductor substrate. in addition,
The insulated gates 300 and 301 have a thickness of about 0.1μ as an insulating film.
m of S i O, and a polysilicon film of about 0.4 μm is formed as a gate electrode. Both are imaged using polysilicon.

An insulating film 51, for example S10. , SiN, PSG, etc. are deposited to a thickness of about 1 μm, and an n1+ layer 150, an n, 10 layer 1
6. The p,, ten layers j3;3, are removed to expose the n3+ layer. Further, an electrode 22 is placed on the second insulating film 51.
, 23, 24 are formed, and the electrodes 23, 24 are short-circuited. An insulating film 52 is further formed on the electrode, and a cathode electrode 220 is suspended from the partially removed portion.

In this way, each layer of the present invention has a planar structure in the form of an elongated stripe, as shown in the line xx' in FIG.

It is also possible to form a circular structure centering on Y-Y'.

In a power semiconductor device, a large current can be extracted by integrating a large number of cells of a composite semiconductor device as shown in FIG. For example, in FIG. 8, x - x, ' or Y - Y'
Integrate tens to tens of thousands of unit cells with line symmetry.

FIG. 11 shows a peripheral structure of a semiconductor device in which the planar structure of FIG. 8 is further integrated. An example of a pattern of a semiconductor region exposed on main surface 101 is shown.

The X-Y plane pattern is repeated, and nine layers 18 are formed around the integrated unit cell. p layer]
On the peripheral side of 8, an n- layer 2 is exposed, and an n0 layer 9 is formed at the periphery. The nine layers 18 are short-circuited to the cathode electrode, and have a structure in which a high voltage is blocked by a termination structure such as a fold plate provided on the n-layer 12. Further, the n-middle layer 19 serves as a channel stopper to stop the depletion layer from growing. Also, 9 layers 18
The pl layers 131, I), +133, p, 14, are short-circuited in the peripheral region to stabilize each layer at the cathode potential and prevent false firing due to sudden changes in voltage d v / d etc. can.

FIG. 12 shows a modification of the present invention in which an 0 layer 121 and an n0 layer 122 are provided on the anode side of FIG. 7 to directly short-circuit the n- layer 12 to the anode electrode 21.

By providing the p+10 layer 1 directly under the n,+ layer 17, it becomes difficult for the hole (■) to reach the area below the n,+ layer 150, where the parasitic thyristor exists, and the soil layer 16, ensuring that the parasitic thyristor is latched. can be prevented from rising. Furthermore, excess carriers generated by the injection of holes (2) from the p-layer 11 can be smoothly extracted through the nN layer 121 and the n-layer 122 during tertiary off, so that the turn-off time can be shortened. n-layer] 21 is n-layer] 2
This acts as a stopper for the depletion layer that extends, making it possible to make the n-layer thinner and reducing the on-state voltage.

As explained above, the composite semiconductor device according to the present invention has
Since the current can be turned on and off using an insulated gate, there will be no malfunction, which can improve the performance of power converters. FIG. 13 shows an example of an inverter device for controlling a motor using the composite semiconductor device of the present invention as a switching element.

The figure shows a three-phase inverter device that controls a three-phase induction motor IM.The basic circuit is three series circuits of two switching elements connected in parallel between the DC terminals ', T, and each series From the center point of the circuit to AC terminal T, , 'r4.
It has a configuration that brings out T. Each switching element sW, sw, s〜〜3゜sw, sw, sw
, are connected in parallel with a snubber circuit S consisting of a flywheel diode FD, a snubber diode SD, a snubber resistor SR, and a snubber capacitor SC, respectively. Since the composite semiconductor device of the present invention is used as a switching element, the on/off circuit of the switching element is simplified, and a highly reliable inverter device can be realized.

[Effects of the Invention] According to the present invention, in a thyristor that has a current limiting effect and can be turned on and off by a MOS gate, the potential of the p-layer of the thyristor can be easily increased, so that the thyristor can be easily fired. . Furthermore, since the hole current injected from the p-soil layer can be guided to the cathode electrode without passing through the parasitic thyristor, there is an effect that there is no malfunction due to latch-up of the parasitic thyristor. Furthermore, p-channel M
N-channel M with current limiting effect by OSFET
Since the p-layer of the OSFET and the p-layer of the thyristor can be short-circuited, it is easy to increase the breakdown voltage. Furthermore, if the composite semiconductor device of the present invention is used as a switching element of a power conversion device, the control circuit can be simplified and a highly reliable device can be realized.

[Brief explanation of the drawing]

FIG. 1 is a schematic sectional view showing one embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of FIG. 1, FIG. 3 is a schematic sectional view showing another embodiment of the present invention, and FIG. 3 is an equivalent circuit diagram, FIG. 5 is a schematic sectional view showing another embodiment of the present invention, FIG. 6 is an equivalent circuit diagram of FIG. 5, and FIG. 7 is a schematic sectional view showing a modified example of the present invention. Fig. 8 is a plan view of Fig. 7, Fig. 9 is a schematic sectional view showing the conventional example, Fig. 1O is an equivalent circuit diagram of Fig. 9, and Fig. 1
The figure is a plan view of the peripheral part of the device when the plan view of FIG. 8 is integrated, FIG. 12 is a schematic cross-sectional view showing another modification of the present invention, and FIGS. 1 and 3 are power conversion devices of the present invention. FIG. 2 is a circuit diagram showing one embodiment of the present invention. ]1... p soil layer, ]2... r)-layer, I 3. ]
4.13]... p layer, 15, 16, 17, 150...
・n ten layers, 2 door anode electrode, 22... cathode electrode,
23゜Figure 1Figure 2Figure 3Figure 4Figure 5Figure 6L
j Fig. 8 Fig. 9 r-11) Fig. 10 Fig. 13-111-r--J

Claims (1)

[Claims] 1. A first semiconductor region of a first conductivity type adjacent to the first main surface; a first semiconductor region adjacent to the first semiconductor region and the second main surface;
a second conductivity type second semiconductor region having a lower carrier concentration than the semiconductor region; and a second semiconductor region extending from the second main surface into the second semiconductor region and separated from each other by the second semiconductor region. third and fourth semiconductor regions of the first conductivity type having a high carrier concentration;
a fifth semiconductor region of a second conductivity type extending into the semiconductor region and having a higher carrier concentration than the third semiconductor region; and a fifth semiconductor region extending from the second main surface into the fourth semiconductor region and having a higher carrier concentration than the third semiconductor region; a semiconductor substrate comprising sixth and seventh semiconductor regions of a second conductivity type that are separated and have a higher carrier concentration than the second semiconductor region; an ohmic contact with the first semiconductor region on a first main surface of the semiconductor substrate; a first main electrode in ohmic contact with the fourth and seventh semiconductor regions on the second main surface of the semiconductor substrate; and a first insulated gate electrode provided so as to straddle the fifth semiconductor region, and a first insulated gate electrode provided so as to straddle the sixth, fourth, and seventh semiconductor regions on the second main surface of the semiconductor substrate. a second insulated gate electrode provided; a first means for electrically connecting the first and second insulated gate electrodes; and a second means for electrically connecting the fifth and sixth semiconductor regions.
A composite semiconductor device comprising: means. 2. In claim 1, the portion where the second main electrode makes ohmic contact with the fourth semiconductor region is more ohmic contact with the third semiconductor region than the portion where the second main electrode makes ohmic contact with the seventh semiconductor region. A composite semiconductor device characterized by being close to a semiconductor region. 3. In claim 1, the portion where the second main electrode makes ohmic contact with the fourth semiconductor region and the portion where the second main electrode makes ohmic contact with the seventh semiconductor region form a third semiconductor. A composite semiconductor device characterized by being far from the area. 4. In claim 1, 2, or 3, the portion of the fourth semiconductor region that contacts the first main surface side of the seventh semiconductor region and the second main electrode is larger than the other portions. A composite semiconductor device characterized by a high carrier concentration. 5. Claims 1, 2, 3, or 4
2. The composite semiconductor device according to item 1, wherein the first insulated gate electrode extends over the fourth semiconductor region. 6. A first semiconductor region of the first conductivity type adjacent to each other in sequence;
a thyristor portion consisting of a second conductivity type semiconductor region, a first conductivity type third semiconductor region, a second conductivity type fifth semiconductor region, and a second conductivity type second semiconductor region adjacent in sequence; A first MOSFE comprising a third semiconductor region of the first conductivity type, a fifth semiconductor region of the second conductivity type, and a first insulated gate electrode provided on the surfaces of the second, third, and fifth semiconductors.
A second MOS consisting of T, sixth, fourth, and seventh semiconductor regions and a second insulated gate electrode provided on the surface of each region.
FET, a wiring member connecting the fifth semiconductor region and the sixth semiconductor region, a first main electrode in ohmic contact with the first semiconductor region, and a first main electrode in ohmic contact with the fourth and seventh semiconductor regions. 1. A composite semiconductor device comprising two main electrodes and a gate electrode connecting the first insulated gate electrode and the second insulated gate electrode. 7. A composite semiconductor device according to claim 6, characterized in that the first insulated gate electrode extends over the fourth semiconductor region. 8. A thyristor region having a pair of main surfaces and consisting of four layers of pnpn such that the outer p layer is exposed on one main surface and the other layer is exposed on the other main surface between the pair of main surfaces. A p-type well layer is provided in the intermediate n-layer of the thyristor region so as to be separated from the intermediate p-layer and exposed to the other main surface, and a p-type well layer is provided in the well layer to be exposed to the other main surface. MOSFE consisting of a source layer and a drain layer
A semiconductor substrate having a T region, a first main electrode in ohmic contact with the outer p layer on one main surface of the semiconductor substrate, and a source layer and a well layer of a MOSFET region on the other main surface of the semiconductor substrate. a second main electrode in ohmic contact with the thyristor region; a means for electrically connecting the MOSFET region, the drain layer, and the n-layer outside the thyristor region; The first insulated gate electrode provided on the well layer exposed between the first insulated gate electrode and the first insulated gate electrode provided on the well layer exposed between
a second insulated gate electrode provided on the intermediate p-layer exposed between the p-layer and the second insulated gate electrode; and means for electrically connecting the first and second insulated gate electrodes to each other. Composite semiconductor device. 9. In a power conversion device in which a circuit in which at least one pair of switching elements are connected in series between DC terminals is connected in parallel for an integer multiple of the number of phases on the AC side, and the AC terminal is drawn out from the midpoint of each circuit connected in series, each The switching element includes a first semiconductor region of a first conductivity type adjacent to the first main surface, and a first semiconductor region adjacent to the first semiconductor region and the second main surface and having a lower carrier concentration than the first semiconductor region. 2nd conductivity type
and third and fourth semiconductor regions of the first conductivity type extending from the second main surface into the second semiconductor region, separated from each other by the second semiconductor region, and having a higher carrier concentration than the second semiconductor region. a semiconductor region, a fifth semiconductor region of a second conductivity type extending from the second main surface into the third semiconductor region and having a higher carrier concentration than the third semiconductor region; a semiconductor body comprising sixth and seventh semiconductor regions of a second conductivity type extending into the semiconductor region and separated from each other by a fourth semiconductor region and having a higher carrier concentration than the second semiconductor region; a first main electrode in ohmic contact with the first semiconductor region on the main surface; a second main electrode in ohmic contact with the fourth and seventh semiconductor regions on the second main surface of the semiconductor substrate; a first insulated gate electrode provided on the second main surface of the semiconductor substrate so as to span over the second, third and fifth semiconductor regions; a second insulated gate electrode provided so as to straddle the seventh semiconductor region; a first means for electrically connecting the first and second insulated gate electrodes; and a fifth and sixth semiconductor region. a second electrically connecting each other;
shall be equipped with the means of