JPS58216469A - 二重シリコンゲ−ト電界効果形半導体装置の製造方法 - Google Patents

二重シリコンゲ−ト電界効果形半導体装置の製造方法

Info

Publication number
JPS58216469A
JPS58216469A JP57101103A JP10110382A JPS58216469A JP S58216469 A JPS58216469 A JP S58216469A JP 57101103 A JP57101103 A JP 57101103A JP 10110382 A JP10110382 A JP 10110382A JP S58216469 A JPS58216469 A JP S58216469A
Authority
JP
Japan
Prior art keywords
polycrystalline silicon
gate electrode
silicon film
film
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57101103A
Other languages
English (en)
Japanese (ja)
Other versions
JPS638628B2 (enrdf_load_stackoverflow
Inventor
Tatsuro Okamoto
岡本　龍郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP57101103A priority Critical patent/JPS58216469A/ja
Publication of JPS58216469A publication Critical patent/JPS58216469A/ja
Publication of JPS638628B2 publication Critical patent/JPS638628B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
JP57101103A 1982-06-10 1982-06-10 二重シリコンゲ−ト電界効果形半導体装置の製造方法 Granted JPS58216469A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57101103A JPS58216469A (ja) 1982-06-10 1982-06-10 二重シリコンゲ−ト電界効果形半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57101103A JPS58216469A (ja) 1982-06-10 1982-06-10 二重シリコンゲ−ト電界効果形半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS58216469A true JPS58216469A (ja) 1983-12-16
JPS638628B2 JPS638628B2 (enrdf_load_stackoverflow) 1988-02-23

Family

ID=14291744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57101103A Granted JPS58216469A (ja) 1982-06-10 1982-06-10 二重シリコンゲ−ト電界効果形半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS58216469A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4345007A1 (de) * 1993-01-20 1994-07-21 Mitsubishi Electric Corp Verfahren zur Herstellung einer Halbleitereinrichtung mit einer einkristallinen Siliziumschicht

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4345007A1 (de) * 1993-01-20 1994-07-21 Mitsubishi Electric Corp Verfahren zur Herstellung einer Halbleitereinrichtung mit einer einkristallinen Siliziumschicht

Also Published As

Publication number Publication date
JPS638628B2 (enrdf_load_stackoverflow) 1988-02-23

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