JPS58215060A - Substrate of thick film integrated circuit - Google Patents

Substrate of thick film integrated circuit

Info

Publication number
JPS58215060A
JPS58215060A JP57097633A JP9763382A JPS58215060A JP S58215060 A JPS58215060 A JP S58215060A JP 57097633 A JP57097633 A JP 57097633A JP 9763382 A JP9763382 A JP 9763382A JP S58215060 A JPS58215060 A JP S58215060A
Authority
JP
Japan
Prior art keywords
lead
thick film
integrated circuit
film integrated
unnecessary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57097633A
Other languages
Japanese (ja)
Other versions
JPS6244858B2 (en
Inventor
Kazuo Yoshikawa
和男 吉川
Hiromi Isomae
磯前 博巳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57097633A priority Critical patent/JPS58215060A/en
Publication of JPS58215060A publication Critical patent/JPS58215060A/en
Publication of JPS6244858B2 publication Critical patent/JPS6244858B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/117Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3405Edge mounted components, e.g. terminals

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To contrive to shorten the working time by a method wherein a mark is given at the position corresponding to a lead unnecessary for connection to the substrate of a thick film IC circuit and thus unnecessary soldering repairing working is removed. CONSTITUTION:The marking of a window blank part 10a is provided at the position uncovered with a clip system lead 6b in the neighborhood of the lead terminal electrode elimination part 4 of the substrate of the thick film IC circuit which is printed and calcined as conventional, and then the substrate is manufactured by the printing and calcination of the soldering resist 5a by chromatic glas or resin. Next, leads 6a and 6b in an integral body with a frame 7 are inserted and soldered, the lead terminal electrode 2a and the lead 6a are connected each other, parts X-X' are cut off, and then the unnecessary lead 6b in the neighborhood of the mark 10a is removed. This constitution facilitates the discrimination of the lead unnecessary for solder connection and enables to prevent performing the unnecessary soldering repairing working to the unnecessary lead, and therefore the cost is reduced.

Description

【発明の詳細な説明】 本発明は、厚膜集積回路基板において、IJ−ド端子電
極が削除しであることを、マーキングを施こして表示し
たことに関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thick film integrated circuit board in which marking is applied to indicate that an IJ-de terminal electrode has been removed.

従来技術により、絶縁基板の片面に厚膜集積回路を形成
した場合の平面図を第1図に示す。
FIG. 1 shows a plan view of a case where a thick film integrated circuit is formed on one side of an insulating substrate using a conventional technique.

この様な、厚膜集積回路基板の製造に際してはまず、絶
縁基板10片面に、配線導体5αと一体となっているリ
ード端子電極2αとを抵抗(図示せず)、半田レジスト
5αを順次、印刷、焼成にハシ形成後に、フレーム部7
と1体構造のクリップ式リード6α、6bを該基板の基
板端部8に挿入し、半田付により、リード端子電極2α
とリード6αを接続する。
When manufacturing such a thick film integrated circuit board, first, a resistor (not shown) and a solder resist 5α are sequentially printed on one side of the insulating substrate 10 to form a lead terminal electrode 2α integrated with the wiring conductor 5α. , after forming the frame by firing, the frame part 7
Insert the clip-type leads 6α, 6b, which are integrated into the board, into the board end 8 of the board, and connect the lead terminal electrodes 2α by soldering.
and connect lead 6α.

ここで接続使用されるクリップ式リード6α。Clip-type lead 6α is used for connection here.

6hは、一般的に、フレーム部7と一体構造であリ、リ
ードピッチは一定間隔で連続しており、厚膜集積回路基
板のリード端子電極21Zけ、リードピッチに合わせて
配設するのが通常である。
6h generally has an integral structure with the frame part 7, and the lead pitch is continuous at a constant interval, and the lead terminal electrodes 21Z of the thick film integrated circuit board are arranged in accordance with the lead pitch. Normal.

ただ、前記した従来技術で(−1、リード端子電極2a
が、電気回路上不必要な場合、つまり、抵抗、配線導体
5α等が接続されていない場合(/cは、リード端子電
極削除部4/′)空白部分を設けておき、リード端子属
・函2αとリード6αを半田付けにより接続した後VC
,X−X’部分を切断する。更に、リード端子な翫削除
部4に挿入されている不必要なリード66を抜去して厚
膜集積回路基板が形成される。
However, in the prior art described above (-1, lead terminal electrode 2a
However, if it is unnecessary for the electric circuit, that is, if the resistor, wiring conductor 5α, etc. are not connected (/c is the lead terminal electrode deletion part 4/'), leave a blank space and insert the lead terminal After connecting 2α and lead 6α by soldering, connect VC
, XX' portion is cut. Further, the unnecessary leads 66 inserted into the lead terminal removal portions 4 are removed to form a thick film integrated circuit board.

次に、従来技術【よシ絶縁基板10表裏両面に形成した
厚膜集積回路基板の表面の平面図を第2図(7tJに、
裏面の平面図を第2図(B)に示し、フレーム部7を基
点とする対称図としである。
Next, FIG. 2 (7tJ) shows a plan view of the surface of a thick film integrated circuit board formed on both the front and back sides of a conventional insulating substrate 10.
A plan view of the back side is shown in FIG. 2(B), which is a symmetrical view with the frame portion 7 as the base point.

第3図はその要部断面図である。FIG. 3 is a sectional view of the main part thereof.

図において、第1図と同一符号は同一部分を表わしてお
り、2hは7面のリード端子電極、2Cオモテ は裏面のリード端子Kt 5Aは表面の配線導体5Cは
裏面の配線導体、5h♂に面の半田レジスト、5Cは裏
面の半田レジスト、6C,6tはリードの表面、 6d
、6fはリードの裏面、9は半田である。
In the figure, the same symbols as in Figure 1 represent the same parts, 2h is the lead terminal electrode on the 7th side, 2C front is the lead terminal Kt on the back side, 5A is the wiring conductor on the front side, 5C is the wiring conductor on the back side, 5h♂ Solder resist on the front side, 5C is the solder resist on the back side, 6C, 6t are the front side of the lead, 6d
, 6f is the back side of the lead, and 9 is solder.

第2図(イ)、(B)、及び第4図から容易に推測でき
る様に、この場合には1表裏交互に順次、表面半田レジ
スト5b、裏面半田レジス)5Cまで印刷、焼成により
形成した後に、クリップ式のリード6v、6tL、6g
、6fを基板端部8に挿入し、半田9によ部表面リード
端子電極2b、裏面リード端子邂極2ごとリード表面6
ξ、リード裏面6fを接続する。
As can be easily inferred from FIGS. 2(A), (B), and FIG. 4, in this case, 1 front and back solder resists (5b) and 5C (back solder resists) were printed and fired in order. Later, clip-on leads 6v, 6tL, 6g
, 6f into the board end 8, and solder 9 to the lead surface 6 together with the front surface lead terminal electrode 2b and the back surface lead terminal electrode 2.
ξ, connect the back side of the lead 6f.

続いて、フレーム部7をX−x′の部分から切シ落とし
て形成する。
Subsequently, the frame portion 7 is formed by cutting off from the X-x' portion.

ここで、前記した第1図の片面形成及び、第2図i 、
 CB)、第3図の両面形式の両者ともに、半田付は終
了後に、半田付は不完全な部分を、半田ごて等を使用し
て補修するのが通常行なわれる。その際に、リード端子
電極削除s4に挿入されている片面形成の場合のり一ド
6h及び両面形成の場合のリード表面6e、  リード
裏面6dの半田付は補修が不必要なリードに、半田付は
補イーを行うという無用な作業を行ない易い欠点がある
。これは、半田9が銀色を呈しておシ、リードもSnメ
ッキ等により銀色であり、リード端子電極も材質かp(
t−AV等でるシ銀色であることから、半田付は補修か
不要である部分の判別が困難であることが原因するもの
である。
Here, the single-sided formation shown in FIG. 1 described above, and FIG.
CB) and the double-sided type shown in FIG. 3, after soldering is completed, the incomplete soldering is usually repaired using a soldering iron or the like. At that time, solder the glue 6h in the case of single-sided formation, the lead surface 6e in the case of double-sided formation, and the lead back side 6d inserted in the lead terminal electrode deletion s4 to the lead that does not require repair. It has the disadvantage that it is easy to perform unnecessary work such as supplementary e. This is because the solder 9 is silver-colored, the leads are also silver-colored due to Sn plating, etc., and the lead terminal electrodes are also made of p(
This is due to the silver color of the t-AV, making it difficult to determine whether soldering is necessary for repair or not.

本発明の目的は、前述した従来仮術の欠点を無くし、製
造時におりる早田伺は補修の際に、半田付り不全な部分
でろシ、リード端子電極削除部分に仰人烙れているクリ
ップ式リード−1の、誤認から起こる無用な半田付り補
1し作業を無くし、−造作業時間を短縮できる厚膜集積
回路基板を提供することにある。
The purpose of the present invention is to eliminate the disadvantages of the conventional temporary surgery mentioned above, and to remove the clips from the parts where the solder is insufficient and to remove the clips from the parts where the lead terminal electrodes are removed. To provide a thick film integrated circuit board capable of reducing the manufacturing time by eliminating unnecessary soldering and repair work caused by misidentification of lead-1.

本発明の妾点は、厚膜集積回路基板におりる、−気回路
上不必妥なリード端子二極が削除しである部分に仰人嘔
れでいるリードへの、半田付は補修が急用でめることを
、リード總子電極削除部分の近訴で、かつ、リードで函
蔽され7よい位置に、有彩色の半田レジストもしくは抵
抗等によるマーキングでfJ別できる峨にしたことKあ
る。
The disadvantage of the present invention is that it is urgently necessary to repair the soldering of the leads on the thick film integrated circuit board where the two poles of the lead terminals, which are unreasonable in terms of the electrical circuit, are removed. In recent years, there has been a recent lawsuit regarding the removal of lead wire electrodes, and the use of colored solder resist, resistor, etc. markings in the positions covered by the leads to allow fj to be distinguished.

本発明の実施例の内、絶縁基板の片面に形成した厚膜集
積回路基板の平面図を第4図に示す。
Among the embodiments of the present invention, a plan view of a thick film integrated circuit board formed on one side of an insulating substrate is shown in FIG.

図において、第1図と同一符号は同一部分を表わしてお
り、10αは半田レジス)54Iの窓状空白部である。
In the figure, the same reference numerals as in FIG. 1 represent the same parts, and 10α is a window-like blank part of the solder resist) 54I.

第4図の厚膜集積回路基板の製造に際しては、抵抗(図
示せず)までは、第1図に示した従来技術と同様に順次
、印刷、焼成した後に、リード端子電極削除部4の近傍
でかつクリップ式リード6hで陰蔽されない位置に窓状
空白部10αによりマーキングを設けである有彩色のガ
ラスまたはレジンによる半田レジスト5αを印刷、焼成
し形成する。次に、フレーム部7と一体構造のリード6
α、6hを挿入し、半田付けにより、リード端子型@2
αとリード6αを% 421.た後に、x−x′の部分
を切断しフレーム部7を除去し、窓状空白部10αでマ
ーキングした近傍の電気回路上不必要なり一ド6bを抜
去して形成する。
When manufacturing the thick film integrated circuit board shown in FIG. 4, the parts up to the resistor (not shown) are sequentially printed and fired in the same way as in the prior art shown in FIG. A marking is provided by a window-like blank portion 10α at a position that is large and not shaded by the clip-type lead 6h, and is formed by printing and baking a solder resist 5α made of chromatic glass or resin. Next, the lead 6 which is integrated with the frame part 7
Insert α, 6h and solder to lead terminal type @2.
α and lead 6α% 421. After that, the frame portion 7 is removed by cutting the section xx', and the unnecessary lead 6b is removed from the electrical circuit in the vicinity of the window-like blank portion 10α marked.

次に、本発明により絶縁基板の表躾両面に形成した厚膜
集積回路基板の表面の平面図を第5図(イ)に、裏面の
平面図を第5図(B)に示し、フレーム部7を基点とす
る対称図としてちる。第6図はその要部断面図である。
Next, FIG. 5(A) shows a plan view of the front surface of a thick film integrated circuit board formed on both surfaces of an insulating substrate according to the present invention, and FIG. 5(B) shows a plan view of the back surface. It is assumed to be a symmetrical diagram with 7 as the base point. FIG. 6 is a sectional view of the main part thereof.

図において、第2図(m 、 CB)、第3図と同一符
号は同一部分を表しておシ、iDAは表面半田レジンr
5bの窓状空白部、+Ocけ裏面半田レジストの窓状空
白部である。
In the figure, the same symbols as in Figures 2 (m, CB) and 3 represent the same parts, and iDA is the surface solder resin r.
5b is a window-like blank part of the +Oc backside solder resist.

第5図(6)、(句、第6図の厚膜集積回路基板の製造
に際して、抵抗(図示せず)までは、第2図(A(B)
及び第5図に示した従来技術と同様に順次、印刷、焼成
した後に、第4図と同様な位置に窓状空白部を設けであ
る有彩色のガラス又はレジンによる表面半田レジスト5
h、at半田レジスト5Cを印刷、゛焼成し形式する。
Figure 5 (6), (phrase) When manufacturing the thick film integrated circuit board shown in Figure 6, up to the resistor (not shown),
After sequentially printing and baking in the same manner as in the prior art shown in FIG. 5, a window-like blank area is provided at the same position as in FIG. 4. A surface solder resist 5 made of colored glass or resin is prepared.
h, At solder resist 5C is printed and baked to form a format.

次′(、フレーム部7と一体構造のリード6C,6d、
66.6fを基板端部8に挿入し、半田9にょシ表面リ
ード端子電極2b、裏面リード端子電極2cとリード表
面6C1+)−ド裏面6fを接続した後、フレー一部7
¥、X−X′の部分が切り落して形成する。
Next'(, leads 6C, 6d integrally constructed with frame part 7,
66.6f into the board end 8 and connect the solder 9, the front lead terminal electrode 2b, the back lead terminal electrode 2c, and the lead surface 6C1+) - back side 6f.
Cut off the ¥, X-X' part to form it.

次に、本発明の応用実施例を第7図の平面に示す。図に
おいて、10dは有彩色の生肝レジスト、あるいは、黒
色の抵抗等により島状に形成したランドパターンであり
、これは、前述した第4図、第5図(3)、(司、第6
図の窓状空白部10α10b、101−に相当するもの
である。
Next, an applied embodiment of the present invention is shown in the plan view of FIG. In the figure, 10d is a land pattern formed in an island shape using chromatic raw liver resist or black resistor.
This corresponds to the window-like blank parts 10α10b, 101- in the figure.

前述した本発明によれば、有彩色の半田レジストの窓状
空白部または、ランドパターンあるいは黒色の抵抗によ
るランドパターンを抜去すべきリード及び半田付は接続
が不必要リードの近傍で該リードで陰蔽されない位置に
設けてマーキングとしたことにより、抜去すべきリード
あるいは、半田付は接続が不必要なリードを判別するこ
とが容易となる。
According to the present invention described above, the lead and solder from which the window-like blank part of the chromatic solder resist, the land pattern, or the land pattern of the black resistor should be removed are shaded by the lead in the vicinity of the lead that does not require connection. By providing the marking in a position that is not covered, it becomes easy to identify the lead that should be removed or the lead that does not need to be connected by soldering.

ゆえに1本発明によれば、半田付は補修時に。Therefore, according to the present invention, soldering is performed during repair.

不必要なリードに、半田付は補修を行うという様な無用
な作業を未然に防止できることから。
Soldering can prevent unnecessary work such as repairing unnecessary leads.

厚膜集積回路基板を製造する際の作業時間が短縮され製
造コスト低減が計られる。
The work time required to manufacture thick film integrated circuit boards is shortened and manufacturing costs are reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来技術による片面形成の厚膜集積回路基板
の平面図、第2図及び第6図は、従来技術による両面形
成の厚膜集積回路基板の平面図及び要部断面図、第4図
は1本発明による片面形成の厚膜集積回路基板の平面図
、第5図及び第6図は、本発明による両面形成の厚膜集
積回路基板の平面図及び要部断面図、第7図は本発明に
よる他の実施例の平面図である。 4・・・リード端子電極削除部、 5α、 5A 、 5C・・・半田レジスト、10α、
+Oh、10C・・・窓状空白部。 +od・・・ランドパターン。 代理人弁理士 薄 1)利 、幸 ・、  1 オ ) 囚 オ 2図 ゝ3Q
FIG. 1 is a plan view of a single-sided thick film integrated circuit board according to the prior art, and FIGS. 4 is a plan view of a single-sided thick film integrated circuit board according to the present invention, FIGS. 5 and 6 are a plan view and a cross-sectional view of essential parts of a double-sided thick film integrated circuit board according to the present invention, The figure is a plan view of another embodiment according to the invention. 4...Lead terminal electrode removed part, 5α, 5A, 5C...Solder resist, 10α,
+Oh, 10C...window-like blank area. +od...land pattern. Representative Patent Attorney Susuki 1) Tori, Yuki, 1 O) Prisoner O 2 Figure 3Q

Claims (1)

【特許請求の範囲】 1、 クリップ式リードを基板端部に挿入し、電気回路
上必要なリードを接続して、厚膜集積回路装置を形成す
る厚膜集積回路基板において、該基板の電気回路上接続
不必要なリードに対応する位置に、マーキングを施して
なることを特徴とする厚膜集積回路基板。 2、 絶縁基板の片面もしくは両面に、電極、抵抗を印
刷形成1−た後に、有彩色のガラスもしくはレジンによ
る半田レジストを印刷形成してなる厚膜集積回路基板で
あって、その周縁部にリード接続用の複数の端子電極パ
ターンを設けてなる厚膜集積回路基板において、電気回
路上接続不要なリードに対応する位置の端子電極を削除
し、その位置の近傍の該リードで陰蔽されない位置の、
該半田レジストに窓伏空白部を設けて、マーキングした
ことを特徴とする厚膜集積回路基板。 6、 上記第2項記載のマーキングが、半田レジストあ
るいは抵抗により(島状)ランドパターンで形成したこ
とを特徴とする請求範囲第1項記載の厚膜集積回路基板
[Claims] 1. In a thick film integrated circuit board in which a clip-type lead is inserted into the end of the board and leads necessary for the electrical circuit are connected to form a thick film integrated circuit device, the electrical circuit of the board is A thick film integrated circuit board characterized in that markings are applied to positions corresponding to unnecessary leads for upper connection. 2. A thick film integrated circuit board in which electrodes and resistors are printed on one or both sides of an insulating substrate, and then a colored glass or resin solder resist is printed, and leads are formed on the periphery of the board. In a thick film integrated circuit board that has a plurality of terminal electrode patterns for connection, remove the terminal electrode at a position corresponding to a lead that does not need to be connected in the electrical circuit, and remove the terminal electrode at a position near that position that is not shaded by the lead. ,
A thick film integrated circuit board characterized in that the solder resist is provided with a window blank area and marked. 6. The thick film integrated circuit board according to claim 1, wherein the marking as described in claim 2 is formed in an (island-like) land pattern using a solder resist or a resistor.
JP57097633A 1982-06-09 1982-06-09 Substrate of thick film integrated circuit Granted JPS58215060A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57097633A JPS58215060A (en) 1982-06-09 1982-06-09 Substrate of thick film integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57097633A JPS58215060A (en) 1982-06-09 1982-06-09 Substrate of thick film integrated circuit

Publications (2)

Publication Number Publication Date
JPS58215060A true JPS58215060A (en) 1983-12-14
JPS6244858B2 JPS6244858B2 (en) 1987-09-22

Family

ID=14197554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57097633A Granted JPS58215060A (en) 1982-06-09 1982-06-09 Substrate of thick film integrated circuit

Country Status (1)

Country Link
JP (1) JPS58215060A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6247155A (en) * 1985-08-26 1987-02-28 Rohm Co Ltd Lead mounting method to substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6247155A (en) * 1985-08-26 1987-02-28 Rohm Co Ltd Lead mounting method to substrate

Also Published As

Publication number Publication date
JPS6244858B2 (en) 1987-09-22

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