JPS582071A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS582071A JPS582071A JP56100303A JP10030381A JPS582071A JP S582071 A JPS582071 A JP S582071A JP 56100303 A JP56100303 A JP 56100303A JP 10030381 A JP10030381 A JP 10030381A JP S582071 A JPS582071 A JP S582071A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- region
- film
- semiconductor device
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 238000000034 method Methods 0.000 claims abstract description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 3
- 239000003990 capacitor Substances 0.000 claims description 5
- 238000010894 electron beam technology Methods 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 3
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 3
- 230000001678 irradiating effect Effects 0.000 claims description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 2
- 229910001882 dioxygen Inorganic materials 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 239000011229 interlayer Substances 0.000 abstract description 2
- 238000002955 isolation Methods 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract 1
- 238000005121 nitriding Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
この発明はＭｌＳ形トランジスタ又Ｉｌｉ、、ｌＳ形キ
ャパシタ等のＭＩＳ形半導体装置の製造方法に“Ｑ：ｓ
″：、： ：’Ｏ＋、−ｒ＊ｔｔｉｗｔ＊−ｔ−ｂａａ
。７□８形トランジスタを同−半欅体基板上に形成する
場合、レジストをマスクとしてイオン注入法により不純
物拡散を行い、各トランジスタのチャンネル領域の不純
物磯度を変え、しきい値電圧を異ならせている。しかし
、この方法はレジスフバク−ユング用マスクを必要とす
る他、製造工程が複雑とまた、同一半導体基板上に異な
る容量値を有する複数のキャパシタを形成する場合、電
極間絶縁膜の厚さを変えることにより答讐値を異ならせ
ている。しかし、この方法は２５（ｂ以下の薄い絶縁膜
を複数棟類も制御性良く、得る（亡は困難である他、選
択的に絶縁膜を成膜または除去するためのマスクを必要
とし製造工程が複雑となる欠点かある。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for manufacturing MIS type semiconductor devices such as MIS type transistors, Ili, and IS type capacitors.
″:,: :'O+, -r*ttiwt*-t-baa
. When forming 7□8 type transistors on the same semicircular substrate, impurity diffusion is performed by ion implantation using a resist as a mask, and the degree of impurity in the channel region of each transistor is changed to vary the threshold voltage. ing. However, this method requires a resistive Bak-Jung mask, has a complicated manufacturing process, and also requires changing the thickness of the interelectrode insulating film when forming multiple capacitors with different capacitance values on the same semiconductor substrate. This makes the revenge value different. However, this method is difficult to obtain thin insulating films of 25 (b) or less with good controllability even in multiple structures, and requires a mask to selectively deposit or remove the insulating films, making it difficult to form a thin insulating film in the manufacturing process. There is a drawback that it is complicated.
この発明は簡単な製造工程により複数の異なるしきい値
電圧または容量値を有するＭＩＳ形半導体装置を同一半
導体基板上に形成することを目的とするものである。An object of the present invention is to form MIS type semiconductor devices having a plurality of different threshold voltages or capacitance values on the same semiconductor substrate by a simple manufacturing process.
以下、図に示す実施例について説明する。The embodiment shown in the figures will be described below.
図（４）〜（至）は本発明によるＭ工ＳデＩ（イスの一
例に索子間分離用の選択酸化膜（２）を形成した後、全
表面にシリコン窒化膜（３）を形成する。シリコン窒化
膜（３）は、熱窒化法或いはブラズ啼窒化法によりシリ
コン主面全面に形成された後回（Ｂ）の（４）に示すよ
うにノリーユングされる。或いは活性または不活性の窒
素ガス雰囲気中において、電子ビーム、レーザービーム
等を局部的に照射し、直接選択的にシリコン窒化膜（４
）を形成しても良い。電子ビー □ムを用いる場合
、窒素ガス雰囲気は、電子の平均自由行程から１０−’
＝、、１０−’ｔ ＯＶｒ径程度真空度妙フ′望ましい
。次に図（Ｃ）に示すようにシリコン窒化膜（４）をマ
スクとして、セルファライン的にシリコン酸化膜（５）
を形成する。形成方法としては、シリコン窒イヒ膜（４
）を形成する前に熱酸化法或いはプラズマ酸化法により
非選択的にシリコン酸化膜（５）を形成してから不要部
分を除去することにより形成しても良いし、活性または
不活性な酸素ガス雰囲蝋中に於て、電子ビームまたはレ
ーザービームを局所的に照射して選択的に形成しても良
い。次に図（ロ）に示すようにＭ工Ｓトランジスタを形
成するためのゲート電極（６）をシリコン窒化膜（４）
及びシリコン酸化膜（５）上に形成し、ひき続きｎ士不
純物を拡散してソース・ドレイン領域（７）を形成する
。次に図（Ｋ）に示すように層間絶縁膜（８）を形成し
、これに電極穴を明けて電極（９）を形成する。このよ
うにしてしきい値電圧が異なる２つのＭｌＳ形トランジ
スタがシリコン基板（１）上に形成される。Figures (4) to (to) show that after forming a selective oxide film (2) for isolation between cords on an example of the M/S device according to the present invention, a silicon nitride film (3) is formed on the entire surface. The silicon nitride film (3) is formed on the entire main surface of the silicon by thermal nitriding or blast nitriding, and then is formed as shown in (4) in step (B).Alternatively, it is formed using an active or inactive film. In a nitrogen gas atmosphere, a silicon nitride film (4
) may be formed. When using an electron beam □ beam, the nitrogen gas atmosphere is 10-' from the electron mean free path.
=,, 10-'t It is desirable to have a degree of vacuum about the diameter of OVr. Next, as shown in Figure (C), using the silicon nitride film (4) as a mask, the silicon oxide film (5) is removed in a self-aligned manner.
form. The formation method is a silicon nitride film (4
) may be formed by non-selectively forming a silicon oxide film (5) by a thermal oxidation method or a plasma oxidation method and then removing unnecessary parts, or by using active or inert oxygen gas. It may also be selectively formed by locally irradiating an electron beam or a laser beam in the wax atmosphere. Next, as shown in figure (b), a gate electrode (6) for forming an M-S transistor is formed using a silicon nitride film (4).
and on the silicon oxide film (5), and subsequently diffuse n-type impurities to form source/drain regions (7). Next, as shown in Figure (K), an interlayer insulating film (8) is formed, and electrode holes are formed in it to form electrodes (9). In this way, two MIS type transistors having different threshold voltages are formed on the silicon substrate (1).
尚、図（Ｃ）に於て絶縁膜（４） （５）上に電極（６
）を形成するだけで容量値が異なる２つのＭＩＳ形キャ
／！シタをシリコン基板（１）上に得ることができる。In addition, in Figure (C), electrodes (6) are placed on the insulating films (4) (5).
) are two MIS type capacitors with different capacitance values. The film can be obtained on a silicon substrate (1).
以上のようにこの発明は半擾体基板の主表面の第１領域
上に第１の絶縁膜を形成し、上記主我兜の＠１領域を除
く第２領域上に上記第１の絶縁膜（５）
とは付値が異なゐ第２の絶縁膜を形成するようにしたの
で、異なるしない値１８Ｅまたは容量値を有するＭＩＳ
型半導体装置を容易に得ることができる０
また、絶縁膜として誘電率の高い材質を選ぶことにより
、膜厚の薄膜化に強制されることなく異なる高い容量値
をもりたキャパシタを相変良く広範囲（得ることができ
る−０
また、絶縁膜としてシリコン県轟膜とシリコン酸化膜を
用い前者をマスクとして後者を形成することにより特別
のマスクを用いることなくセルファライン的に容易にシ
リコン酸化膜を形成することができる。As described above, in the present invention, the first insulating film is formed on the first region of the main surface of the semicircular substrate, and the first insulating film is formed on the second region excluding the @1 region of the main body. (5) Since the second insulating film is formed with a different value from that of MIS with a value of 18E or a capacitance value that is not different from that of
In addition, by choosing a material with a high dielectric constant for the insulating film, capacitors with different high capacitance values can be easily manufactured over a wide range ( In addition, by using a silicon oxide film and a silicon oxide film as the insulating film, and forming the latter using the former as a mask, the silicon oxide film can be easily formed in a self-aligned manner without using a special mask. be able to.
図（４）〜（乃はと−の発明の一実施例になるＭＩＳ形
トランジスタの製造工程を示す断面図である。
（１）はシリコン基板、（４） Ｉｒｉシリコン窒化膜
、（５）はシリコン酸化膜、（６）は電極を示す。
代 理 人 葛 野 信 −（６）ｓ９８Figures (4) to (4) are cross-sectional views showing the manufacturing process of a MIS type transistor which is an embodiment of the invention of Nohato. (1) is a silicon substrate, (4) is an Iri silicon nitride film, and (5) is a Silicon oxide film, (6) indicates the electrode. Agent Makoto Kuzuno - (6) s98
Claims (8)
を形成し、上記主表面の第１領域を除く第２領域上に上
記絶縁膜とけ異なる材質からなる第２の絶縁膜を形成し
、上記第１及び第２の絶縁膜上に各々電極を形成するこ
とを特徴とする半導体装置の製造方法。(1) A first insulating film is formed on a first region of the main surface of the semiconductor substrate, and a second insulating film made of a material different from that of the insulating film is formed on a second region of the main surface excluding the first region. A method for manufacturing a semiconductor device, comprising forming an electrode on each of the first and second insulating films.
縁膜がシリコン窒化膜であることを特徴とする特許請求
の範囲第１項記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the first insulating film is a silicon oxide film and the second insulating film is a silicon nitride film.
スクとして第１の絶縁膜を形成することを特徴とする特
許請求の範囲第２項記載の半導体装置の製造方法。(3) After forming the second insulating film, the first insulating film is formed using the second insulating film as a mask.
後、第２領域上の部分が残留されることにより形成され
ることを特徴とする特許請求の範囲第３項記載の半導体
装置の製造方法つ(4) The second insulating film is formed by once forming the entire main surface and then leaving a portion on the second region. Method of manufacturing semiconductor devices
に電子ビームまたはレーザービームを局部的に照射して
第２領域上に選択的に形成されることを特徴とする特許
請求の範囲第３項記載の半導体装置の製造方法。(5) A patent characterized in that the second insulating film is selectively formed on the second region by locally irradiating the second region with an electron beam or laser beam in a nitrogen gas atmosphere. A method for manufacturing a semiconductor device according to claim 3.
後、第１領域上の部分が残留されることにより形成され
ることを特徴とする特許請求の範囲第２項記載の半導体
装置の製造方法。(6) The first insulating film is formed by once forming the entire main surface and then leaving a portion on the first region. A method for manufacturing a semiconductor device.
、に電子ビームまたはレーザービームを局部的に照射し
て第１領域上に選択的に形成されることを特徴とする特
許請求の範囲第２項記載の半導体装置の製造方法。(7) A patent characterized in that the first insulating film is selectively formed on the first region by locally irradiating the first region with an electron beam or a laser beam in an oxygen gas atmosphere. A method for manufacturing a semiconductor device according to claim 2.
ノケート絶縁膜或いはＭＩＳ形キャパシタの電極間絶縁
膜である特許請求の範囲第１〜７項の何れかに記載の半
導体装置の製造方法。(8) The method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein the first and second insulating films are an MIS type transistor node insulating film or an interelectrode insulating film of a MIS type capacitor. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56100303A JPS582071A (en) | 1981-06-25 | 1981-06-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56100303A JPS582071A (en) | 1981-06-25 | 1981-06-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS582071A true JPS582071A (en) | 1983-01-07 |
Family
ID=14270396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56100303A Pending JPS582071A (en) | 1981-06-25 | 1981-06-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS582071A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01257366A (en) * | 1988-04-07 | 1989-10-13 | Toshiba Corp | Semiconductor device and its manufacture |
| JPH04208570A (en) * | 1990-11-30 | 1992-07-30 | Nec Corp | Manufacture of semiconductor device |
| WO2004021440A1 (en) * | 2002-09-02 | 2004-03-11 | Advanced Micro Devices, Inc. | Semiconductor device including a field effect transistor and a passive capacitor having reduced leakage current and an improved capacitance per unit area |
| US6821840B2 (en) | 2002-09-02 | 2004-11-23 | Advanced Micro Devices, Inc. | Semiconductor device including a field effect transistor and a passive capacitor having reduced leakage current and an improved capacitance per unit area |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52129383A (en) * | 1976-04-23 | 1977-10-29 | Hitachi Ltd | Mis semicnductor integrated circuit device |
-
1981
- 1981-06-25 JP JP56100303A patent/JPS582071A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52129383A (en) * | 1976-04-23 | 1977-10-29 | Hitachi Ltd | Mis semicnductor integrated circuit device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01257366A (en) * | 1988-04-07 | 1989-10-13 | Toshiba Corp | Semiconductor device and its manufacture |
| JPH04208570A (en) * | 1990-11-30 | 1992-07-30 | Nec Corp | Manufacture of semiconductor device |
| WO2004021440A1 (en) * | 2002-09-02 | 2004-03-11 | Advanced Micro Devices, Inc. | Semiconductor device including a field effect transistor and a passive capacitor having reduced leakage current and an improved capacitance per unit area |
| US6821840B2 (en) | 2002-09-02 | 2004-11-23 | Advanced Micro Devices, Inc. | Semiconductor device including a field effect transistor and a passive capacitor having reduced leakage current and an improved capacitance per unit area |
| CN1299362C (en) * | 2002-09-02 | 2007-02-07 | 先进微装置公司 | Semiconductor device including a field effect transistor and a passive capacitor having reduced leakage current and an improved capacitance per unit area |
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