JPS582058A - Capacitor - Google Patents
CapacitorInfo
- Publication number
- JPS582058A JPS582058A JP10007381A JP10007381A JPS582058A JP S582058 A JPS582058 A JP S582058A JP 10007381 A JP10007381 A JP 10007381A JP 10007381 A JP10007381 A JP 10007381A JP S582058 A JPS582058 A JP S582058A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- polycrystalline silicon
- capacitor
- oxide film
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 2
- 239000010410 layer Substances 0.000 abstract description 20
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 239000011229 interlayer Substances 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 5
- 238000000059 patterning Methods 0.000 abstract description 2
- 230000007261 regionalization Effects 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- -1 Muj Chemical class 0.000 description 1
- 101100168117 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) con-8 gene Proteins 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- NBJBFKVCPBJQMR-APKOLTMOSA-N nff 1 Chemical compound C([C@H](NC(=O)[C@H](CCC(N)=O)NC(=O)[C@H](CCC(N)=O)NC(=O)[C@@H]1CCCN1C(=O)[C@H](CCCCN)NC(=O)[C@@H]1CCCN1C(=O)CC=1C2=CC=C(C=C2OC(=O)C=1)OC)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)NCC(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](CCCCNC=1C(=CC(=CC=1)[N+]([O-])=O)[N+]([O-])=O)C(=O)NCC(O)=O)C1=CC=CC=C1 NBJBFKVCPBJQMR-APKOLTMOSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はキャパシｐＫ於すて、限られた面積内で大容量
の得られゐ構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure in which a large capacity can be obtained within a limited area in terms of capacitor pK.
飢１図に従来の↑ヤパシタの構造のいく、つかの例を示
して説明する。Figure 1 shows some examples of the conventional ↑Yapashta structure and explains it.
ＩＩＩ Ｉ ＷＪ （ａｌ ＃ｉｙす＝ｔｙ基板に拡散
された不純物と。III I WJ (al #iys=ty impurities diffused into the substrate.
熱酸化膜を介して形成された多結晶シリコンとで形成し
たキャパシタの構造である１例えばＮ型のシリコン基板
１にＭＪの拡散層２と、コンタクトをとるべく、より製
置の濃−ＮｆＡ拡散層３を形成する。しか１後にフィー
ルド酸化＠４を形ｌ１ＩＵＬ。It has a structure of a capacitor formed with polycrystalline silicon formed through a thermal oxide film 1. For example, in order to make contact with an MJ diffusion layer 2 on an N-type silicon substrate 1, a concentrated NfA diffusion layer is formed. Form layer 3. However, after 1 field oxidation @4 form l1IUL.
ホシ工程により窓開けを行なう。熱酸化により。Open the window using the hoshi process. By thermal oxidation.
酸化１に５を形成した後、多結晶シリコン６を電極形成
する０層間絶縁１１７を全面に形広し、コンタクト用の
窓開けを行１ｋ ｖ” ＊ ム！等の配線用金属を配線
形成したものが第１図Ｅａｋである。After forming 5 on oxide 1, polycrystalline silicon 6 was used to form electrodes, interlayer insulation 117 was formed over the entire surface, windows were opened for contacts, and wiring metals such as 1kv''*mm! were formed. The thing is Eak in Figure 1.
第１図（６１１ｊ２層の多結晶シリコン層の間に酸化膜
を介することによって形成したキャパシタの構造である
。例えばシリコン基板９にフィールド酸化膜ｌＯを形成
する。１層目の多結晶シリコン１１を形成した後、熱酸
化工程により酸化＠１２を形広し。FIG. 1 (611j) This is the structure of a capacitor formed by interposing an oxide film between two polycrystalline silicon layers. For example, a field oxide film 10 is formed on a silicon substrate 9. The first layer of polycrystalline silicon 11 is After forming, the oxide@12 is expanded by a thermal oxidation process.
２層目の多結晶シリコン１３を形成する。層間絶縁膜１
４を全面に形成し、コンタクト用の窓開性を行ない、五
！等の配線用金属１５を配線形成したものが第１図ｒ６
１である。このようなキャパシタの構造では、大容量を
必要とする場合、キャパシタの面積を大きくとるか、絶
縁膜を薄くする方法があるが後者の場合、耐圧が低下す
るためにｉ者の方法をとるしかな−。ところがキャパシ
タの面積を大きくとることば、チップサイズが大きくな
ることであり微細化、暮集積化の面から芳しくな込。A second layer of polycrystalline silicon 13 is formed. Interlayer insulation film 1
4 is formed on the entire surface, a window is opened for the contact, and 5! Figure 1 r6 shows a wiring formed using wiring metal 15 such as
It is 1. In this type of capacitor structure, if a large capacity is required, there are two ways to increase the area of the capacitor or to make the insulating film thinner; however, in the latter case, the withstand voltage decreases, so the method of the i method is used. I wonder-. However, increasing the area of the capacitor means increasing the chip size, which is less favorable in terms of miniaturization and integration.
本発明は以上の欠点を改良しｔもので、基板と多層の多
結晶シリコンでキャパシタを形成することにエリ、小さ
な面積で大写を６得られる構造を図ったものである。以
下に本発明による製造方法の１例を説明する。第２図【
α１はＮｆｆ１のシリコン基板１に１＠ウエル２を形成
し、さらＫＮ型の拡散層３と、コｙタタＦをとゐべくよ
り製置のＩＩＩＩｂＮ型拡散層４全拡散層４ものである
。次にフィールド。The present invention improves the above-mentioned drawbacks by forming a capacitor using a substrate and multilayered polycrystalline silicon, and has a structure that allows a large image to be obtained in a small area. An example of the manufacturing method according to the present invention will be explained below. Figure 2 [
α1 is formed by forming a well 2 in a silicon substrate 1 of Nff1, further including a KN type diffusion layer 3, and a IIIbN type diffusion layer 4 which is prepared to remove the Coytata F. Next is the field.
酸化ｌ［５を形成し、ホシ工程によりパターン形成、を
行’＆”ｈ熱酸化１１６を形成した屯のが同図ζｂ１で
ある。１、層目の多結晶シリコンをパターン形成した後
、熱酸化１１ｇを形成したものが同図（０）である。ζb1 in the same figure shows the formation of oxidized 1[5], patterned by a heating process, and thermally oxidized 116. After patterning the first layer of polycrystalline silicon, The one in which oxidation 11g was formed is shown in (0) of the same figure.
さらに２層目の多結晶シリコン９をパターン形成し、全
面に層間絶縁１［１０管形放したものが同図Ｔｄ１であ
る。最後にコンタクト用の窓開性を行な論・ムｊ等の配
線用金属を配線形成したものが同図−１である。この時
、拡散層４と２層目多結晶シリコン９は接続された状態
＃Ｃある。このような構造によれば１例えば１１１図（
６）Ｋ示すように従来の構造に、より得られる容量値に
対し、同じ電極面積絶縁膜厚ならばｇｚａ（／１に示す
よう本発明で得られる構造では２つのキャパシタが並列
に接続された形Ｋｌｋｔ）、２倍の容量値が得られる。Furthermore, the second layer of polycrystalline silicon 9 is patterned, and the interlayer insulation 1 [10 tubes] are formed on the entire surface, as shown in the figure Td1. Finally, window opening for contacts was performed and wiring metals such as wires and wires were formed as shown in Figure 1. At this time, the diffusion layer 4 and the second layer polycrystalline silicon 9 are in a connected state #C. According to such a structure, 1For example, Fig. 111 (
6) As shown in K, for the capacitance value obtained by the conventional structure, if the electrode area and insulating film thickness are the same, then gza (/1) In the structure obtained by the present invention, two capacitors are connected in parallel. type Klkt), twice the capacitance value can be obtained.
従って、所定の容量を得るにあたや面積が半分で１＜１
高集積化を図ることができる０以上のように本発明は多
層構造により大容量が得られるキャパシタで゛ある。Therefore, to obtain a given capacity, the area must be halved and 1<1
The present invention is a capacitor that can obtain a large capacity due to its multilayer structure, as shown in the above-mentioned capacitor that can achieve high integration.
Ｍ１図Ｃα１〜（ｃｋｋｌ従来のキャパシタ構造に関す
ｂものであり、第２図Ｃα１〜（７１Ｆｉ本発明による
キャパシタの製造方法及び構造を示す図である、１、Ｎ
型シリコン基板 ２．Ｐ型ウェル３ ＊ ’４−ＭＩ
Ｉ拡散層 ５ンフイールト°酸化膜６、熱酸化１［
７，多結晶−／１Ｊコン８、熱酸化膜 ９．
多結晶シリコンＩＱ、Ｐ ８ ’Ｇ等の層間絶縁膜
１１、ムｊ等の配線用金属
以 上
出願人 株式会社緻訪精工舎
代理人 弁理士 最 上 務
第１図M1 Figures Cα1~(ckkl) b are related to the conventional capacitor structure, Figure 2 Cα1~(71Fi are diagrams showing the manufacturing method and structure of the capacitor according to the present invention, 1, N
Mold silicon substrate 2. P-type well 3 * '4-MI
I diffusion layer 5 in field ° oxide film 6, thermal oxidation 1 [
7. Polycrystalline-/1J con 8. Thermal oxide film 9.
Interlayer insulating film 11 such as polycrystalline silicon IQ, P8'G, etc., wiring metals such as Muj, etc. Applicant: Souwa Seikosha Co., Ltd. Representative Patent Attorney Mogami Mogami Figure 1
Claims (1)
に含むシリコン基板に於いて、該シリコン基板と篤１の
絶縁膜層を介してなる１層目の電極と、該１層目の電極
と第２の絶縁属層を介してなる２層目の電極を有し、該
２層目の電極と前記不純物層がコンタクトを肩すること
によって形成されることを特徴とするキャパシタ。 （２１１層目及び２層目の電極として多結晶シリコンを
一輪たことを特徴とする特許請求の範囲ｗ４１項記敞の
キャパシタ。 Ｃ３１１層目及び２層目の電極とシて、導電性を有すゐ
金属を用い霞ことを特徴とする特許請求の範囲謳１項記
載のキャパシタ。 ＋４１絶縁膜層としてシリコン酸化Ｍ１１．あるいはシ
リコン窒化膜を用いたことを特徴とする特許請求の範１
１１８１１項記載のキャバシ！。 （５） １ ｍｌ目電極としてム！を用いた場合の２層
目絶縁膜層としてアルｉすを用すたことを特徴とする特
許請求め゛範１！１１１１項記載のキャパシタ。[Claims] (In a silicon substrate containing an impurity having an 11N type or a #'iP type near the surface, a first layer electrode formed between the silicon substrate and an insulating film layer of A1; It has a second layer electrode formed by interposing the first layer electrode and a second insulating metal layer, and the second layer electrode and the impurity layer are formed by shouldering a contact. (A capacitor according to claim W41, characterized in that the electrodes of the 111st layer and the second layer are made of polycrystalline silicon.) A capacitor according to claim 1, characterized in that the capacitor is made of a metal having a property of 1.5%. 1
Cabashi as described in item 11811! . (5) 1 ml can be used as an electrode! 1111. The capacitor according to claim 1, wherein aluminum is used as the second insulating film layer in the case of using aluminum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10007381A JPS582058A (en) | 1981-06-26 | 1981-06-26 | Capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10007381A JPS582058A (en) | 1981-06-26 | 1981-06-26 | Capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS582058A true JPS582058A (en) | 1983-01-07 |
Family
ID=14264274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10007381A Pending JPS582058A (en) | 1981-06-26 | 1981-06-26 | Capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS582058A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61187357A (en) * | 1985-02-15 | 1986-08-21 | Seiko Epson Corp | Semiconductor device |
| US5658821A (en) * | 1996-09-27 | 1997-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of improving uniformity of metal-to-poly capacitors composed by polysilicon oxide and avoiding device damage |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5610954A (en) * | 1979-07-05 | 1981-02-03 | Nec Corp | Semiconductor device |
-
1981
- 1981-06-26 JP JP10007381A patent/JPS582058A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5610954A (en) * | 1979-07-05 | 1981-02-03 | Nec Corp | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61187357A (en) * | 1985-02-15 | 1986-08-21 | Seiko Epson Corp | Semiconductor device |
| US5658821A (en) * | 1996-09-27 | 1997-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of improving uniformity of metal-to-poly capacitors composed by polysilicon oxide and avoiding device damage |
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