JPS63126270A - Semiconductor storage device - Google Patents
Semiconductor storage deviceInfo
- Publication number
- JPS63126270A JPS63126270A JP61272155A JP27215586A JPS63126270A JP S63126270 A JPS63126270 A JP S63126270A JP 61272155 A JP61272155 A JP 61272155A JP 27215586 A JP27215586 A JP 27215586A JP S63126270 A JPS63126270 A JP S63126270A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- layer
- film
- shared contact
- diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 55
- 238000009792 diffusion process Methods 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 230000004888 barrier function Effects 0.000 claims abstract description 7
- 238000005204 segregation Methods 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 4
- 238000004904 shortening Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 33
- 239000010408 film Substances 0.000 description 23
- 239000010409 thin film Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 230000003068 static effect Effects 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910004217 TaSi2 Inorganic materials 0.000 description 1
- 229910008479 TiSi2 Inorganic materials 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、負荷素子とＮチャネルトランジスタとを直列
に接続した一対のインバータでメモリセルが構成された
スタチックＲＡＭに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a static RAM in which a memory cell is constituted by a pair of inverters in which a load element and an N-channel transistor are connected in series.
第４図および第５図は、負荷素子と駆動用Ｎチャネルト
ランジスタとを直列接続したインバータから構成された
高抵抗負荷形スタチックメモリセルの従来例を示す断面
図および回路図である。第４図および第５図において、
１はＰ形つェル、２は分離５ｉＯｚ膜、３はＮ形拡散領
域、４はゲートＳｉＯ□膜、５は第１層多結晶シリコン
としての第１層多結晶シリコンゲート電極、６は５ｉｎ
２膜、７は第２層高抵抗多結晶シリコン、８は第２層中
抵抗多結晶シリコン、Ｌｌ、Ｌ２はビット線、Ｌ３はワ
ード線である。上記第２層高抵抗多結晶シリコン７と第
２層中抵抗多結晶シリコン８は第２層多結晶シリコンか
ら形成される。4 and 5 are a cross-sectional view and a circuit diagram showing a conventional example of a high-resistance load type static memory cell composed of an inverter in which a load element and a driving N-channel transistor are connected in series. In Figures 4 and 5,
1 is a P-type well, 2 is an isolated 5iOz film, 3 is an N-type diffusion region, 4 is a gate SiO□ film, 5 is a first layer polycrystalline silicon gate electrode as the first layer polycrystalline silicon, and 6 is a 5in.
2, 7 is a second layer of high resistance polycrystalline silicon, 8 is a second layer of medium resistance polycrystalline silicon, Ll and L2 are bit lines, and L3 is a word line. The second layer high resistance polycrystalline silicon 7 and the second layer medium resistance polycrystalline silicon 8 are formed from second layer polycrystalline silicon.
次に従来の第２層高抵抗多結晶シリコン７と第２層中抵
抗多結晶シリコン８との形成法について説明する。まず
、駆動用Ｎチャネルトランジスタのゲート電極として多
結晶シリコン膜にＮ形あるいはＰ形不純物をドーピング
した後、バターニングしたＮ形あるいはＰ形の多結晶シ
リコンゲート電極５を形成する。次に層間絶縁のＳｉＯ
□膜６を形成し、Ｎ形拡散領域３とＮチャネルトランジ
スタのゲート電極５とに対するシェアドコンタクトを開
口する。次に第２層多結晶シリコンを形成し、この第２
層多結晶シリコンにイオン種および濃度を選択的に打ち
分けることにより、同じ多結晶シリコン内に第２層高抵
抗多結晶シリコン７と第２層中抵抗多結晶シリコン８と
を形成する。Next, a conventional method for forming the second layer of high resistance polycrystalline silicon 7 and the second layer of medium resistance polycrystalline silicon 8 will be described. First, a polycrystalline silicon film is doped with N-type or P-type impurities as a gate electrode of a driving N-channel transistor, and then a patterned N-type or P-type polycrystalline silicon gate electrode 5 is formed. Next, the interlayer insulation SiO
□ A film 6 is formed and a shared contact between the N-type diffusion region 3 and the gate electrode 5 of the N-channel transistor is opened. Next, a second layer of polycrystalline silicon is formed, and this second layer of polycrystalline silicon is formed.
By selectively bombarding the polycrystalline silicon layer with ion species and concentrations, a second layer of high resistance polycrystalline silicon 7 and a second layer of medium resistance polycrystalline silicon 8 are formed in the same polycrystalline silicon.
従来の半導体記憶装置においては、第２層多結晶シリコ
ン７．８を形成した後の熱処理工程において、Ｎチャネ
ルトランジスタのゲート電極５内のＮ形あるいはＰ形不
純物が第２層高抵抗多結晶シリコン７に拡散していき、
高抵抗部分の有効長が短くなってしまい、その分、高抵
抗配線長の設計寸法を大きくしなければならず、高集積
化を妨げていた。In a conventional semiconductor memory device, in a heat treatment process after forming the second layer of polycrystalline silicon 7.8, N-type or P-type impurities in the gate electrode 5 of the N-channel transistor are removed from the second layer of high-resistance polycrystalline silicon. It spread to 7,
The effective length of the high-resistance portion is shortened, and the design dimensions of the high-resistance wiring length must be correspondingly increased, which hinders high integration.
本発明はこのような点に鑑みてなされたものであり、そ
の目的とするところは、高抵抗多結晶シリコン配線長を
より短くすることができ、より高集積化を可能にする半
導体記憶装置を得ることにある。The present invention has been made in view of these points, and its purpose is to provide a semiconductor memory device in which the length of high-resistance polycrystalline silicon wiring can be further reduced and higher integration is possible. It's about getting.
このような目的を達成するために本発明は、半導体基板
上に形成された拡散領域、第１層多結晶シリコンおよび
第２層多結晶シリコンに対しシェアドコンタクトをとっ
た構造をもつ半導体記憶装置において、第１層多結晶シ
リコンにドーピングした不純物に対する偏析係数又は拡
散係数が多結晶シリコンよりも小さい膜をシェアドコン
タクト部分にバリア層として形成するようにしたもので
ある。In order to achieve such an object, the present invention provides a semiconductor memory device having a structure in which shared contact is made with a diffusion region formed on a semiconductor substrate, a first layer of polycrystalline silicon, and a second layer of polycrystalline silicon. , a film having a segregation coefficient or diffusion coefficient for impurities doped into the first layer polycrystalline silicon is smaller than that of the polycrystalline silicon, and is formed as a barrier layer in the shared contact portion.
本発明においては、第１層多結晶シリコン内の不純物の
第２層多結晶シリコンへの拡散が抑制される。In the present invention, diffusion of impurities in the first polycrystalline silicon layer into the second polycrystalline silicon layer is suppressed.
本発明に係わる半導体記憶装置の一実施例を第１図に示
す。第１図において、９ａはＮ形あるいはＰ形不純物に
対する偏析係数が多結晶シリコンより小さい薄膜である
。薄膜９ａとしては、例えばＰ形不純物ボロンに対する
Ｔａ５ｉｚ膜がある。An embodiment of a semiconductor memory device according to the present invention is shown in FIG. In FIG. 1, 9a is a thin film whose segregation coefficient for N-type or P-type impurities is smaller than that of polycrystalline silicon. The thin film 9a is, for example, a Ta5iz film containing boron as a P-type impurity.
第２図は本発明の第２の実施例を示す断面図である。第
２図において、９ｂはＮ形あるいはＰ形不純物に対する
拡散係数が多結晶シリコンより小さい薄膜、１０は薄膜
９ａと同時に形成される金属シリサイド膜である。薄膜
９ｂとしては、例えばＮ形不純物燐に対してはＴｉＮ膜
があり、この場合、金属シリサイド膜１０はＴｉ５ｉｚ
膜となる。FIG. 2 is a sectional view showing a second embodiment of the invention. In FIG. 2, 9b is a thin film whose diffusion coefficient for N-type or P-type impurities is smaller than that of polycrystalline silicon, and 10 is a metal silicide film formed at the same time as thin film 9a. As the thin film 9b, for example, there is a TiN film for N-type impurity phosphorus, and in this case, the metal silicide film 10 is Ti5iz.
It becomes a membrane.
次に、第１図および第２図の半導体記憶装置の製造方法
について第３図を用いて説明する。まず、第１層多結晶
シリコンゲート電極５．ＳｉＯ□膜６を形成した後、シ
ェアドコンタクトを開口する（第３図（ａ））。次にバ
リア層となる薄膜１１を形成する（第３図（１）））。Next, a method for manufacturing the semiconductor memory device shown in FIGS. 1 and 2 will be described with reference to FIG. 3. First, the first layer polycrystalline silicon gate electrode 5. After forming the SiO□ film 6, shared contacts are opened (FIG. 3(a)). Next, a thin film 11 that will become a barrier layer is formed (FIG. 3 (1)).
この薄膜１１としては、例えば、ポロンに対する偏析係
数が多結晶シリコンより小さいＴａＳｉ２膜又は燐に対
する拡散係数が多結晶シリコンより小さいＴｉ膜を形成
する。As this thin film 11, for example, a TaSi2 film whose segregation coefficient for poron is smaller than that of polycrystalline silicon, or a Ti film whose diffusion coefficient for phosphorus is smaller than that of polycrystalline silicon is formed.
Ｔ ａ Ｓ ＋、 ２膜の場合、シェアドコンタクトを
おおうようにバターニングし、その後、第２層多結晶シ
リコン７．８を形成すると、第１図に示す所望の構造が
得られる。In the case of the T a S +,2 film, the desired structure shown in FIG. 1 is obtained by buttering the shared contact so as to cover it and then forming a second layer of polycrystalline silicon 7.8.
Ｔｉ膜の場合、第３図（Ｃ）に示すように、窒化雰囲気
で熱処理を行なうと、Ｎ形拡散領域３および第１層多結
晶シリコンゲート電極５上にチタンシリサイド膜（Ｔｉ
Ｓｉ、膜）１０が形成され、また同時にその上にバリア
層となるＴｉＮ膜９ｂが形成される。次に第３図（ｄ）
に示すように、シェアドコンタクトをおおうようにＴｉ
Ｎ膜９ｂをバターニングし、その後、第２層多結晶シリ
コン７゜８を形成すると、第２図に示す所望の構造が得
られる。In the case of a Ti film, as shown in FIG. 3(C), when heat treatment is performed in a nitriding atmosphere, a titanium silicide film (Ti
A Si film 10 is formed, and at the same time a TiN film 9b serving as a barrier layer is formed thereon. Next, Figure 3(d)
As shown in , Ti covers the shared contact.
By patterning the N film 9b and then forming a second layer of polycrystalline silicon 7.8, the desired structure shown in FIG. 2 is obtained.
なお上記実施例では、高抵抗負荷形スタチックＲＡＭに
ついて説明したが、シェアドコンタクトを有する他の半
導体記憶装置に本発明を適用しても同様の効果を奏する
。In the above embodiment, a high resistance load type static RAM has been described, but the same effect can be obtained even if the present invention is applied to other semiconductor memory devices having shared contacts.
以上説明したように本発明は、シェアドコンタクト部分
に第１層多結晶シリコンの不純物の拡散を抑制するバリ
ア層を設けたことにより、高抵抗部分の有効長が短くな
ることがなくなり、第２層高抵抗多結晶シリコンの配線
長を短くすることができるので、高集積化を図ることが
できる効果がある。As explained above, the present invention provides a barrier layer that suppresses the diffusion of impurities in the first layer polycrystalline silicon in the shared contact portion, so that the effective length of the high resistance portion is not shortened, and the second layer Since the wiring length of high-resistance polycrystalline silicon can be shortened, there is an effect that high integration can be achieved.
第１図は本発明に係わる半導体記憶装置の一実施例を示
す断面図、第２図は本発明の第２の実施例を示す断面図
、第３図は第１図および第２図の装置の製造方法を説明
するための断面図、第４図および第５図は従来の半導体
記憶装置を示す断面図および回路図である。
１・・・Ｐ形つェル、２・・・分離用５ｉｎｔ膜、３・
・・Ｎ形拡散領域、４・・・ゲー）Ｓｉ０ｇ膜、５・・
・第１層多結晶シリコンゲート電極、６・・・ｓ ｓ
Ｏ！膜、７・・・第２層高抵抗多結晶シリコン、８・・
・第２層中抵抗多結晶シリコン、９ａ・・・Ｔａ３ｉｚ
膜、９ｂ・・・ＴｉＮ膜、１０・・・ＴｉＳｉ２膜。1 is a sectional view showing an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a sectional view showing a second embodiment of the invention, and FIG. 3 is a sectional view of the device shown in FIGS. 1 and 2. 4 and 5 are a sectional view and a circuit diagram showing a conventional semiconductor memory device. 1... P-type well, 2... 5-inch membrane for separation, 3...
...N-type diffusion region, 4...G) Si0g film, 5...
・First layer polycrystalline silicon gate electrode, 6...s s
O! Film, 7... Second layer high resistance polycrystalline silicon, 8...
・Second layer medium resistance polycrystalline silicon, 9a...Ta3iz
Film, 9b...TiN film, 10...TiSi2 film.
Claims (2)
晶シリコンおよび第２層多結晶シリコンに対しシェアド
コンタクトをとった構造をもつ半導体記憶装置において
、前記第１層多結晶シリコンにドーピングした不純物に
対する偏析係数又は拡散係数が多結晶シリコンよりも小
さい膜を前記シェアドコンタクト部分にバリア層として
形成して、前記第１層多結晶シリコン内の不純物の前記
第２層多結晶シリコンへの拡散を抑制することを特徴と
する半導体記憶装置。(1) In a semiconductor memory device having a structure in which shared contact is made between a diffusion region formed on a semiconductor substrate, a first layer of polycrystalline silicon, and a second layer of polycrystalline silicon, the first layer of polycrystalline silicon is doped. a film having a segregation coefficient or diffusion coefficient for impurities smaller than that of polycrystalline silicon is formed as a barrier layer in the shared contact portion, and the impurities in the first layer polycrystalline silicon are diffused into the second layer polycrystalline silicon. 1. A semiconductor memory device characterized by suppressing.
ンをゲート電極とする駆動用Ｎチャネルトランジスタと
第２層多結晶シリコンである負荷素子とを直列に接続し
た接続部分であることを特徴とする特許請求の範囲第１
項記載の半導体記憶装置。(2) The shared contact portion is a connection portion in which a driving N-channel transistor whose gate electrode is made of first layer polycrystalline silicon and a load element whose gate electrode is made of second layer polycrystalline silicon are connected in series. Claim 1
The semiconductor storage device described in 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61272155A JPS63126270A (en) | 1986-11-14 | 1986-11-14 | Semiconductor storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61272155A JPS63126270A (en) | 1986-11-14 | 1986-11-14 | Semiconductor storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63126270A true JPS63126270A (en) | 1988-05-30 |
Family
ID=17509856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61272155A Pending JPS63126270A (en) | 1986-11-14 | 1986-11-14 | Semiconductor storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63126270A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05160369A (en) * | 1991-05-16 | 1993-06-25 | American Teleph & Telegr Co <Att> | Integrated circuit |
| US8967207B2 (en) | 2008-01-31 | 2015-03-03 | Polyplastics Co., Ltd. | Multi-layer cylindrical molded article |
-
1986
- 1986-11-14 JP JP61272155A patent/JPS63126270A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05160369A (en) * | 1991-05-16 | 1993-06-25 | American Teleph & Telegr Co <Att> | Integrated circuit |
| US8967207B2 (en) | 2008-01-31 | 2015-03-03 | Polyplastics Co., Ltd. | Multi-layer cylindrical molded article |
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