JPS58201372A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the formation of a GaAs connecting layer under a Schottky junction electrode, and to prevent the reduction of the reverse withstand voltage of Schottky junction by a method wherein an SiO2 film containing Sn and an Si3N4 film are provided in succession on the GaAs layer coming in contact with the side of the Schottky junction electrode. CONSTITUTION:The N type GaAs active layer 2, the SiO2 film 3 containing Sn are stacked on a semiinsulating GaAs substrate 1, an opening is formed in the film 3 applying a mask 4, and the surface is covered with the Si3N4 film 5. A heat treatment is performed to diffuse Sn from the film 3, and to form the N<+> type connecting layer 6. Anisotropic etching is performed to remove the Si3N4 film 5, and the film 5 on the side wall of the opening in the film 3 is left. Then Al 7 is laminated, the gate electrode 9 is provided applying a resist mask 8, the mask 8 is removed, and a source electrode 10, a drain electrode 11 are formed interposing the electrode 9 between them. According to this construction, the N<+> type GaAS connecting layer 6 is not formed under the electrode 9, reduction of the reverse withstand voltage of Schottky junction is prevented, and the device being able to operate at large amplitude and having high output can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and in particular to a method for manufacturing a Schittke junction carved diode and Schottky junction field effect transistor using a compound semiconductor. ◇ Semi-insulating (8, The development of an integrated circuit (abbreviated as IC) using potassium arsenide (abbreviated as GaAs) is different. Schottky junction diode (8
The methods for lowering the series resistance of the 8Di (abbreviated as 8Di) are as follows: 0) Reduce the distance between the ohmic I11 electrode and the Schottky junction electrode, and (2) Reduce the carrier concentration in the region where the ohmic electrode is to be formed. (3) GaA between the ohmic conductive and Schottky junction electrodes to reduce the ohmic contact resistance.
s The carrier concentration in the active layer is increased, or GaAsl
1b layer is thickened to reduce sheet resistance, (4) I of 01ml active layer where ohmic electrodes are to be formed! In general, methods such as increasing the thickness of oH41E can be considered, using ion implantation, which is expected to produce the effect of (21, +31, r41). However, in recent years, instead of ion implantation, fl), + by diffusion method
21 , +31 , 141 or at least i
Structures satisfying the ll, +21, and A31 CD conditions have been studied. The feature of this method is that it is self-aligned when looking at the above-mentioned tl), and the distance between the ohmic electrode and the Schittky junction wire can be effectively brought close to zero.
The IIMJL carrier layer is formed in contact with the Schittke junction electrode. Figure 1 shows the crucian tooth diagram formed by the conventional diffusion method (jaA@FBTaJ), and Figure 2 shows the FBTaJ crucian tooth diagram.
In the oail1 diagram, which is for explaining the manufacturing method of gT, 8.1.0a is placed on Asl.

Ga to be the channel under the 4 to the 4 to 4
As Ikl1Sakulayer 餉 area 2 is connected and useless (jaAs
A ml area is formed in which the carrier axle is higher than the carrier la table in the production layer area 2. The Gapm contact layer area is a non-conducting layer in GaAs that can be of the conductivity type of -j- with the θ1
It is formed by the diffusion of impurities from the insulating layer J [5].

A source electrode 6 and a drain electrode 7, which are ohmic conductive electrodes, are formed on the GaAm contact layer.

In #Itx shown in 1m, since the end of the OaAs contact layer is located at the Schittky junction gate I1 value, the series resistance is can be reduced,
In addition, because the resistance of the GIAs contact layer is low, even if the source and drain electrodes are formed using a general ring graphie technique based on the gate voltage and the distance between the gate #LfiI and the source electrode or A similar @* structure in which the distance between the drain electrode and the gate electrode is shortened has the structure shown in FIG. 1, and substantially satisfies the series resistance reduction measure (1). In addition, the source and drain electrodes are made of Ga having a high carrier #11 degree.
Since it is formed on the Am contact layer, it also satisfies the measure (2) for reducing series resistance. In addition, by selecting the impurity diffusion temperature and diffusion method for forming the QGaAs contact layer, the thickness of the GaAs contact layer (3mAg contact layer) is thicker than the thickness of the GaAs active layer due to the alignment with the 01mA2 active layer. This also satisfies the series resistance reduction measure 14), particularly in the case of enhancement FIT.

As mentioned above, the G-type FF1T with the structure shown in Fig. 1 may be considered to employ electrode formation by self-alignment in the series resistance reduction measure (1).Next, Fig. 2 shows A method of manufacturing 01 msFgT shown in FIG. 1 will be explained using the following.

In Figure 2(a) % 8.1. GaAs l
On the O aA s operating layer 2 formed above, an insulating film 3 of Hatake 1 is formed, which is to be placed on which a Schittke junction is to be formed. Next, the first ll! ! 1 mm of the edge and the GaAm working layer 2 as described above.
A second insulating film 4 containing impurities having the same conductivity type as the layer 2 is deposited. This second insulating film is formed by applying and drying a liquid that is the fine particles of the insulating film that was bathed at Arimine Kisai, or because the second insulating film was in a liquid state at the time of the bathing. , the thickness on the insulation jla of +41 is Onkmllb
Thinner than the thickness above the strata.

In addition, the disconnected layer of Koji 1 and the insulating film of Koji 2 are selected so that the etching uniformity of each is different.
As shown in b), for example, when 800c(t)^ is used for fb geography, the impurities in the second insulating film diffuse into the 0aAs+ active layer, and the GaAs layer with a high impurity concentration, that is, &# storm carriers. A GaAs contact layer 5 having a high concentration is formed.

Next, as shown in Figure 2 (c), if the etching speed of the 20th insulating film 4 is slower than the etching speed of the insulating film 3 (D), then the etching speed of the insulating film 2 on the first insulating film 3 is As mentioned above, it is thin, so the first insulating film 3 is removed while the second insulating film 4f is left.
As shown in FIG. 3, the area from which the first insulating film 3 has been removed is soldered and a gate electrode 6 is deposited thereon.

Next, as shown in FIG. 2(e), the source electrode 7, which is an ohmic electrode, and the drain voltage are placed on the edge GaAs contact layer 5 from which the second insulating film 4 has been removed so as not to contact the gate electrode 6. 8, GaAsFBT shown in mX is formed. The reverse breakdown voltage of the general kUaAa sheet alignment decreases as the carrier ll&# in GaAs increases.

In the GaAs FMT shown in Figure 1, ^l11! The edges of the GaAs contact layer, which is the carrier layer, are sheet-shaped*
*Because it is located under the pole, the reverse side pressure of the contact region is lower than the reverse breakdown voltage of the contact region on the active layer, so the 1 The reverse breakdown voltage of the GaAs FET shown in Figure 1ζ is (J
Since it is determined by the reverse direction withstand voltage of the aAs contact junction, the withstand voltage is 2 to 3 V@j[,
When the iI current-fed application voltage of G a A s k' g T is small and the human input signal is small, it operates without any problems, but when making a large swing IILII operation, you want to get a large output signal.In the output FWT, this Shit hand gesture or breakdown occurs and no piezoelectric movement is shown.

An object of the present invention is to provide a method for manufacturing a semiconductor device that can withstand the use of layers that increases the conventional junction breakdown voltage and achieves large vibration operation and high output. The mold is deposited on at least a part of the surface of the junction electrode, forming the first e-edge film on the GaAs, and #IJ
A second layer containing impurity M111, which becomes an impurity of − conductivity type, is formed in GaAs on GaA1 along with the insulating film L11.
By depositing an insulating film of
The present invention provides a method for manufacturing a semiconductor device. That is, on the conductive type GaAs active layer formed on the resistor GaAs, the conductive type GaAg active layer and the 411L type 22JelI containing impurities that may occur in the Ga film 1 are formed.
A step of depositing an I film, a step of removing the second insulating film in the area where the gate 4i is to be formed and making a part of the one conductivity type 0aAs@outer layer ridged, and a step of depositing the exposed Ichihiro electrode. Shape G
The step of shaking the round part of the kite 1 with the help of the aAm active layer and at least a part of the second insulating film and heat treatment to remove impurities in the second insulating film. - a step of diffusing ξ into the active layer, and removing at least a part of the insulating film of 驱1 by A-tropic dry etching to remove at least a part of the insulating film of 驱1 - the insulating film of the above-mentioned Tsuru 2 of the conductivity type GaAg active layer. 1 root exposing at least a portion of the area removed and such exposed -41&G
aAs spinning process and a step of forming a part of loquats of all iim and -2 to form a 71-toy jointed abutment, and removing at least a part of the loquat of 2 for the above. This is a method for manufacturing a semiconductor device in which the Vl value is determined by forming an ohmic electrode.

Hereinafter, 111 examples of the present invention will be explained using FIG. In Fig. 3 fat, ^resistance 0aAs layer 1
Carrier 1lkb11XILit formed on top of
x) bLS on NfeOaAsM stirred layer 2? lJEhaG
Soot (an) that can become ε-CN type impurity in aAs
An example of an example containing impurities is silicon dioxide (Si(
Jz) Layer the insulating film 3 of the cradle 2. Next, as shown in Fig. 43 (-), a mask material 4 such as photoresist is applied on the AU acid second insulating film 3, and a photolithographic bonding process is performed using an ordinary photolithography method. The second insulating film in the region where the electrode is to be formed is removed to expose a portion of the N-type GaAs active layer. Next, as shown in FIG. 843(c), after removing the mask material 4,
0x above the exposed N-type GaAs operation and Il
! After depositing a first insulating film 5 of an insulating film type containing an impurity that does not become a - conductivity type impurity in GaAs such as a Sing insulating film or phosphorus [F] to cover the second insulating film, for example, Heat treatment is performed at 800° C. for 5 minutes to diffuse the impurities contained in the second insulating film 1ζ + PAJ IF onto the N-type GaAs active layer 2 of the sntJ IF to form an N-type GaAm contact having a high am carrier VB degree. Form layer 6.

(g) The depth of the N-type OajLm contact layer is determined by the heat treatment temperature and heat treatment time.
8n contained in 0211 was heat-treated at 800°C for 15 minutes to form N with a carrier configuration of 1XllllaN.
Figure 10 shows 10 files of carrier when diffused into Gaks. In JII4Ill, the vertical axis shows the carrier chain and the horizontal axis shows the radius from the surface. ! ! 4m1 (approximately 0.15Jl! II (2) deep, I
It can be seen that a GaAl contact layer having a carrier concentration of "am" is formed. Next, as shown in FIG. 3(d), when the first insulating film on the second insulating film is removed using anisotropic etching, the N-type GaAs exposed to form the Schittky junction is removed. @A part of the outer layer is exposed again, but a part of the first insulating film, that is, a part of the first insulating film deposited on the side surface of the second insulating film remains.

In this step, if the end of the 01λ$ contact layer 6 is not exposed, that is, if the end of the GaAm contact layer is covered with a part of the first insulating film left by the above-mentioned driver etching, it is not exposed. (on iaAs, i.e. N
Even if a Schittke junction is formed on the G a As type active layer, the reverse breakdown voltage of the Schottky junction does not decrease.

On the other hand, the end of the GaAs contact layer explained using FIG. 4 is not the end of the second insulating film, but is located under the first cIJ insulating film due to the lateral diffusion of Sfi. This lateral diffusion is the same #i storm as the depthwise diffusion. Therefore, in the case of the heat treatment salt tension described above, there is a diffusion in the direction of lateral force of 0.15μ, so considering the margin, the thickness of the storm is about 0.3μ.
The thickness of the first insulating film shown in FIG. 3 (as indicated by cl) may be determined so that the first insulating film is coated on the 111 wall of the a & 2 isolation films.

Next, as shown in FIG. 3(e), the seat fitting metal 7 is
After depositing aluminum (AJ), for example, in order to form a gate electrode, a mask material 8, for example a photoresist, is deposited on the area where the Schittke junction electrode is to be formed.

The metal/toki joint metal 7 may have a structure in which different metals are cored in multiple layers.

Next, using the mask material 8 as a mask, a part of the Schittky bonding metal 7 is removed to form a gate electrode 9 as shown in FIG. 3(f), and then the mask material 8 is removed. Next, as shown in FIG. 3(f), a part of the second insulating film is removed and a source electrode IO and a drain 1111 are formed with the C1 gate electrode 9 in between. pole 1
form 1.

As is clear from the above explanation, it is clear that the present invention can also be applied to semiconductor devices manufactured from 8B Di or other semiconductor materials such as InP, etc., instead of the GaAs FBTOJh shown in the example marked #. O which is force 1

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a conventional GaAs FET, and the second figure is a cross-sectional view of a conventional GaAs FET and (11 people's FET).
FIG. 3 is a diagram for explaining the method for manufacturing a GaAs FET according to the present invention, and FIG.
In Figure 1, which shows the carrier profile of GaAs with an AS contact layer, l is 8. I, UaAs,
2 is GaA@active layer, 3 is 0aAs contact 1m, 4 is Sisanbutki mounting base electrode, 5 is tiaAi
An insulating film containing 1 negative which can be of 14 electric type with 1=Htl in the middle,
61J source electrode, 7i! Train Zenitsu, Demeru O 2nd
In the figure ゛(, l is 9.1. C'raA&s 2
(iGaAi active layer, 3+! m 10.) e-edge IA, 4c second insulating film, 51cm UaAs contact increase, 6 is open contact junction electrode, etc., 7h7-base (@,
W+! In the I-rain electrode O Igai&, 1 is the 4-resistance GhAs layer, 2 is the N type (iaA/active layer, 3 is the second insulating film, 4.8 is the mask material, 5 is the ml insulating film, 6 is a GaAm contact layer, 7 is a sheet metal, 9 is a gate electrode, 1O is a source voltage 4k, and 11 is a drain 1tfi. 2 m)

Claims (1)

[Claims] A conductivity type semiconductor active layer formed on a high-resistance P4 body contains the same 4' type impurity as the semiconductor active layer (contains impurities that occur in the skeleton semiconductor active layer and the 4 resistance type body). After removing the second insulating film in at least a part of the region where the second insulating film is to be formed, a part of the first conductivity type semiconductor operating layer make Fujiyama 1
a step of applying an insulating layer to the first conductivity type semiconductor active layer and at least a part of the insulating layer of the second conductive layer, and applying a second insulating layer by heat treatment. A step of diffusing the impurity during the conduction into the semiconductor active layer of one conductivity type, and an anisotropic dry etching process to remove part of the insulating material of if, and remove the part to form the gate conductor 1h. A step of exposing a part of the one-conductivity type semiconductor operating layer in the region and leaving a first insulating layer 1#f on the individual surface of the insulation layer of i@2, A process of forming an electric head across a part of the insulation layer and the second insulation film, and removing at least a part of the insulation film of the above-mentioned aI2 to make the insulation film ohmic. A method for manufacturing a semiconductor device, the method comprising the step of forming an electrode.