JPS58197863A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS58197863A
JPS58197863A JP57080936A JP8093682A JPS58197863A JP S58197863 A JPS58197863 A JP S58197863A JP 57080936 A JP57080936 A JP 57080936A JP 8093682 A JP8093682 A JP 8093682A JP S58197863 A JPS58197863 A JP S58197863A
Authority
JP
Japan
Prior art keywords
ceramic substrate
semiconductor element
metallic
island
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57080936A
Other languages
English (en)
Other versions
JPS639749B2 (ja
Inventor
Takashi Miyamoto
隆 宮本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57080936A priority Critical patent/JPS58197863A/ja
Publication of JPS58197863A publication Critical patent/JPS58197863A/ja
Publication of JPS639749B2 publication Critical patent/JPS639749B2/ja
Granted legal-status Critical Current

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は半導体装置にかかり、とくにセラミ。
り基板に搭載され、金属シールにより気密封止される半
導体装置に関するものである。
本発明は、第１図（ａｔに示すように、セラミック基板
１にキャビティと称する凹部２を設け、その底に半導体
素子３を固着し、半導体素子のｔ極とボンティングパッ
ド４とを全綱細＃５で接続した後、セラミック基板上に
半導体素子を取り囲むようにロウ付けされた金属リング
６に金属キャップ７をかぶせ、その周囲を浴融して封止
するいわゆるシームウェルド法による半導体装置や、第
１図（ｂｌのように、金属リングを設けずに、タングス
テンＷやモリブテン庵メタライズした後にニッケルＮｉ
及び金Ａｕをめっきして塊状の金属層（図示せず）を設
け、この上に例えば金ん１とｆｉ＆１Ｉ８ｎの合金数を
挾んでセラミックキャップや金ＭＩ１２にシールする共
晶合金シール法など、半導体素子の周囲に気密封止する
九めの塊状の金属層を設けた牛導体装撫を含むものであ
る。
以上のような環状金属部封止型の半導体装置に用いられ
るセラミック基蛸シその外部リードピン８の数が同じで
外形形状が同一であっても、それに搭載する半導体素子
３の回路機能によって。
内部の配線パタンを変える必要があった。即ち。
環状金属層の電位を半導体素子３と同じ接地の電位にし
たい場合、第２図のように、キャビティ２の底面から延
在した金属配線をスルーホール９を介してキャップ７と
接続するなどの工夫が必要となり、スルーホールのある
ものとないものの２種類を用意しなければならなかつ九
。
このことは、セラミ、り基板の種類が増加することにな
り、ひいては半導体装置のコスト・アップを招くことに
なる。
本発明は、上記の欠点を解消するため罠なされたもので
あり、金属リングの内側のセラミック基板表面に金属リ
ングから延びた金属ターミナルを設け、更に半導体素子
の裏面または電極と導通し友金属配線の延長部が前記金
属ターミナルに接近して設けられたことを特徴とする屯
のであシ、その目的とするところは同一セラミ、り基板
を用いて種々の半導体素子が搭載できるよう汎用性を持
たせることにより、半導体装置のコスト・ダウンを計る
ことＫある。
以下に１本発明の詳細な説明する。
半導体素子裏明と金属リングとを同一電位に維持する場
合の実施例を第３図に示す。第３図は。
金属リング６の内部を一部分切）出して描いた断面斜視
図である。セラミック基板１に設けたキャビティ２の底
部にはアイランドと称する金属層１゜を設け、これに半
導体素子３を固着する。アイランドは通常セラミ、り基
板の焼成前にタングステンＷやモリブデンＭｏ　の粒子
を分散させたインクをスクリーン印刷し、焼成した後、
ニッケル歯更に金Ａｕをめっさして形成される。半導体
素子３のアイランド１０上への固着は金Ａｕとシリコン
ｓｉの共晶合金やハンダで行なわれる。次に半導体素子
３の電極１１とポンディングパッド４とを金Ａｕやアル
ミニウムＭを主成分とする金属細線５で接続する。ポン
ディングパッドはそれぞれ外部リード　　　！ピンに電
気的に導通している。アイランド１ｏが　　　□らは１
図中に破線で示したように延長部１２があり、これはス
ルーホール１３を通してセラミック基板表面のパッド１
４Ｋｋ続されている。＝万、金属リング６からは金属タ
ーミナル１５がパッド１４に接近して延びている。以上
の構造を有することにより、金属リングがアイランドと
同電位を維持する必要９ある時は、金属細線１６でパッ
ド１４と金織ターミナル１５とを接続すればよいし。
不要な場合はこの接続をしなければよく、同一のセラミ
、り基板が使用できる。
また、同様の構造で、第４図に示したように％特定のボ
ンレイングパッド４と金属リングとを同電位に保ちたい
時も、そのボンディングパッドの延長部からスルーホー
ル１３を介して設けたパ。
ド１４と、金属リングから延びた金属ターミナルとを接
近させておけば、合繊細線１６を接続することにより行
なえる。
パッド１４とアイランドまたは内部配線との接続全必ら
ずしもスルーホールを介する必要はない。
例えば、第５図のように１階段状の凹部の壁面を金蝿配
線を這わせ（側面メタライズ）、パッド１４に接続して
もよい。本例の場合、アイランド１゜と内部配線とパッ
ドと半導体素子の電極とを全て接続した例で示した。
また、第６図のようにアイランド１０から延在した内部
配線１２が、スルーホール１７を介して接続し更に上段
でパッド１４に怪紗する一万、金編リング６の直下から
スルーホール１８を介し、て金緘ターミナル１５を形成
し１両者を金属線＃１６で＋に続するとともできる。
以上は１代表的な半導体装置ｋ寸あるＤＩ）’（Ｄｕａ
ｌｌ醜１ｉｎｅ　）’ａｃｋａｇｅ）型について龜明し
たが１本発明はその外杉形状には制約をれない。例えば
、ＰＩＦ（）’ｌｕｇ　ｉｎ　Ｐａｃｋａｇｅ）型やチ
ップキャリア型シングルインライン型等の半導体装置に
も適用できる。
また組立方式は、ワイヤ・ボンデインク法に限られるこ
とはな（、’Ｉ”ＡＢｆ：、など他の組立法による牛尋
体装診にも適用できる。
１ち使用される材料も以上に挙げたものに限らず他の材
料も使用できることは営うまでもない。
以上、詳細に説明し友ように本発明だよれば。
半導体素子を搭載するセラミ、り基板の内用性が高くな
り、１種類のセラミック基板で多種類の半導体素子の搭
載が可能となり、ひいては半導体装置のコストダウンを
可能とすることができる。
【図面の簡単な説明】
第１図（ａｔ　、　（ｂ）は金属封止型セラミック半導
体装置を説明する断面図、第２図は従来の半導体装置の
断面図、第３図乃至第６図は本発明の実施例を示す断面
斜視図である。 図中で％　１・・・・・・セラミック基板、２・・・・
・・キャビティ、３・・・・・・半導体素子％４・・川
・ポンディングパッド、５・・・・・・金属細線、６・
・・・・・金属リング、７・・・・・・キャップ、８・
・・・・・外部リードビン、９・・・・・・スルーホー
ル、１０・・・・・アイランド、１１・・・・・・電極
。 １２・・・・・・内部配線の延長部、１３・・・・・・
スルーホール、１４・・・・・・パッド、１５・・印・
金属ターミナル。 １６・・・・・・金属細線である。 ＜ａ＞ 第ｌ　図　　　　　　　　　１ ＃−２図 ６ 范６図 −−− ／／ “ヱ −ｖ−３目

Claims (1)

    【特許請求の範囲】
  1. 半導体素子と、該半導体素子を搭載したセラミック基板
    と、このセラミ、り基板に密着し前記半導体素子を取り
    囲むように形成した環状金属層と、その環状金属層に固
    着されたキャップとを備えた半導体装置において、前記
    環状金属層に取り囲まれた領域内に、前記セラミ、り基
    板の表面に密着しその環状金属層と電気的に導通し友金
    属ターミナルの近くに、前記半導体素子の裏面または前
    記半導体素子の表面の電極と電気的に導通した導電鳩が
    設けられたことを特徴とする半導体装置。
JP57080936A 1982-05-14 1982-05-14 半導体装置 Granted JPS58197863A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57080936A JPS58197863A (ja) 1982-05-14 1982-05-14 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57080936A JPS58197863A (ja) 1982-05-14 1982-05-14 半導体装置

Publications (2)

Publication Number Publication Date
JPS58197863A true JPS58197863A (ja) 1983-11-17
JPS639749B2 JPS639749B2 (ja) 1988-03-01

Family

ID=13732342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57080936A Granted JPS58197863A (ja) 1982-05-14 1982-05-14 半導体装置

Country Status (1)

Country Link
JP (1) JPS58197863A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63500692A (ja) * 1985-08-27 1988-03-10 ヒユ−ズ・エアクラフト・カンパニ− 超小形電子パッケ−ジ
US5027191A (en) * 1989-05-11 1991-06-25 Westinghouse Electric Corp. Cavity-down chip carrier with pad grid array

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63500692A (ja) * 1985-08-27 1988-03-10 ヒユ−ズ・エアクラフト・カンパニ− 超小形電子パッケ−ジ
JPH0324067B2 (ja) * 1985-08-27 1991-04-02 Hughes Aircraft Co
US5027191A (en) * 1989-05-11 1991-06-25 Westinghouse Electric Corp. Cavity-down chip carrier with pad grid array

Also Published As

Publication number Publication date
JPS639749B2 (ja) 1988-03-01

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