JPS5819785A - Memory access controlling system - Google Patents

Abstract

PURPOSE:To reduce the access time from a processor to cache memory and to increase the processing efficiency for a memory access controlling system of the processor, etc., by fetching in advance the address counter of the cache memory. CONSTITUTION:A main storage device 18 and a cache memory 3 are connected to a processor 6. An adder memory 2 stores the addition given to an address counter 1 and delivers an added signal G. The memory 3 comprises an address part (a) and a data part (d) and, to the beginning, and accessed by a lower level address a2 of the counter 1. The read-out address data a1 is compared 5 with an upper level address a1, and a hit signal H1 obtained upon attaining a comparison agreement reads out the data d1 to transfer it to the processor 6. A discriminating part 17 compares the signal H1 with the signal G, and an output signal B is fed to a comparing part 4. The addresses a1 and a2 are compared with an address data A coming next which and the data d1 of the memory 3 is read out by the signal H2 upon attaining comparison agreement to be fed to the processor 6.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a memory access control scheme for controlling access to underlying memory to a processor.

In a processing device equipped with a cache memory, part of the information in the main memory is stored in the cache memory. Since this cache memory uses a high-speed integrated circuit (IC), processing speed is significantly improved. Generally, the access time of cache memory is 92 times faster than the access time of main memory. Therefore, the cache memory can be accessed at least twice within one cycle time of the main memory. Therefore, the cache memory control unit receives the first
After receiving and controlling the address data A, the address counter of the cash register is immediately set to
, and set its value to A1+1. Next, the processing device sends second address data A! When received, this person is compared with the value (A1+1) of the address counter to make a determination, and if person=(A1+1), data can be immediately read from the cache memory. In other words, the antecedent 'l1il+ of memory access can be performed.

The present invention has focused on the above points, and aims to provide a memory access flilJO11 method that improves the processing efficiency of a processing device.

The present invention comprises a main storage device, a cache memory, an address counter that determines an address of the cache memory, and a processing device, and the first address of the address counter set at a first time and the cache memory a first comparing means for comparing the first address with a second address read from the processing device; and a second comparing means for comparing the first address and a third address issued from the processing device at a second time point. , comprising means for incrementing the address counter by +1, and means for discriminating between the incrementing signal and the output signal of the first comparing means, the first address and the second address and when the first address and the third address match, the data in the cache memory determined by the first address is transferred to the processing device. .

Hereinafter, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram illustrating an embodiment of the present invention, and 20th is a flowchart illustrating an embodiment of the present invention, in which 1 is an address counter, 2 is an addition memory, 3 is a cache memory, 4 and 5 are comparison sections, 6 is a processing device, 7 and 13 are OR circuits, 8, 9.12 are M Yamaguchi paths, 10 is a set pulse generation section, 11 is an address generation section, 14 is a read command generation section, 15
is a register section, 16 is a processing J/U section, 17 is a discrimination section, 18
is the above t (inspection device j: i, A I-j address data, B is the output signal, C is the reading command, E, F is the mismatch signal, G is the added signal, II, , H, is the hit signal,
S is a set signal, a is an address part, al is an upper address, af is address data, a2'! :l: Lower address, d is the data part. The addition memory 2 in FIG. 1 is a memory that stores the fact that the address counter has been added (+1), and the addition completed signal G is a signal indicating the addition completed state. The deep cache memory 3 is composed of an address section a and a data section d, and the upper byte of address data A is stored in the address section a. In FIG. 1, at the first time C1), the memory 3 is accessed using the lower address a2 in the address counter, address data a/, is read from the address section R, and this al and the address counter The comparator 5 compares the address with the upper address a. As mentioned above, since the address a1 is the upper byte of the address data A, when both al and al match, the comparing section 5 generates the hit signal H1. This hit signal H, reads data d1 from the data section d of address a2 of the cache memory 3, and transfers it to the processing device 6. The data d1 is the AND circuit 9. It is set in the register section 15 via the OR circuit 13. Next, the determining section 17 determines between the hit signal H and the added signal G. That is, if the hit signal H8 is output from the comparator 5 and the address counter 1 has already been added (+1), the discriminator 1
Output signal B is output from 7. According to this output signal B,
In the comparator 4, the address (a
A comparison is made with the address data A to be compared. When the two match, a hit signal I2 is generated, and the data d1 in the cache memory is taken out and transferred to the controller 6. Data d is AND circuit 8, OR
It is set in the register section 15 via the circuit 13. In other words, address data 4 from the processing device 6 is set in the address counter 1, the data is read from the cache memory 3, and then the address counter 1 is incremented (plus 1). Next, since the address data (At) issued from the processing device 6 and the address data (At) match, data is immediately read from the cache memory 3.

When the comparison section 5 generates a mismatch signal E, the mismatch signal E passes through the OR circuit 7 and triggers the set pulse generation section. The generated set pulse S reaches the address counter 1 and sets the address data A from the processing device 6.

On the other hand, the mismatch signal is sent to the processing device 6,
The data d2 in the main memory device 18 is input to the AND circuit 12, OR,
It is set in the register section 15 via the circuit 13.

When a mismatch signal F is generated in the comparator 4, this signal passes through the OR circuit 7 and triggers the set pulse generator, so the generated set pulse S reaches the address counter 1 and sets the address data A. On the other hand, the difference ν (signal F reaches the comparator 5 and the upper address a1
and the address data a1 are compared. This comparison operation is the same as described above. FIG. 2 is a flowchart showing the sequence of operations described above.

As described above, the present invention takes advantage of the high speed of cache memory and increments the address counter of the cache memory in advance to shorten the time required for accessing the cache memory from the processing device. It has the advantage of significantly improving processing efficiency.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining one embodiment of the present invention, ff
+'++ Figure 2 is a flowchart explaining an embodiment of the uninvented joke, and the symbols used in the figure are as follows: 0 1ζ-1 Near address counter 2: Force 117: Memory;
3 is a cache memory, 4 and 5 are comparison sections, 6 is a processing device, 7.13 is an OR circuit, 8, 9.12 is an AND circuit, 1
0 is a set pulse generator, 11 is an address generator, 14
15 is a register unit, 16 is a processing unit,
17 is a determination unit, 18 is a main memory installed, A is address data, B is an output signal, ci, [I'W take all commands, F is a mismatch signal, G is a force γ completed signal, Hl. ■■2 is a hit signal, S is a set signal, a digit address part, aI is an upper address, a' is address data, a,
indicates a lower address, and d indicates a data portion.

Claims (1)

[Claims] The device includes a main storage device, a cache memory, an address counter that determines the address of the cache memory, and a processing device, and the first address of the address counter set at a first time point and the first address read from the cache memory are a second comparing means for comparing the first address with a third address issued from the processing device at a second time; A means to advance by +1,
means for discriminating between the incremented signal and the output signal of the first comparing means, and when the first address and the second address match, or when the first address and the third A memory control method characterized in that when the first address matches the first address, data in the cache memory determined by the first address is transferred to the processing device.