JPH04361343A - Parity check circuit - Google Patents

Abstract

PURPOSE:To make operations into a pipeline and to perform access to a memory in a shortest cycle by temporarily latching read data and parity by a latch circuit, completing the operation of a memory bus and afterwards executing a parity check. CONSTITUTION:When a request signal comes from a system bus in the case of a memory read cycle, a memory controller 1 generates a control signal required for access and according to this control signal, the data and the parity are read out of the memory. These data and parity are temporarily latched by a latch circuit 7 at timing for a host to accept the data, and the access cycle of the host side is finished. On the other hand, the next cycle is started at the system bus from this point of time and at a parity check/judgement circuit 5, however, the truth of the preceding access is judged. Then, the result is latched and outputted to the outside according to a parity error latch timing signal to be outputted from the memory controller 1 at the next timing.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parity check circuit, and more particularly to a parity check circuit for a storage device having a parity check mechanism and realizing high-speed memory access.

0002

2. Description of the Related Art In general, a parity check method is often used as a method of checking the authenticity of data in a storage device. Conventionally, in this type of parity check method, the read data and parity are used to determine whether the data is is configured to determine the truth or falsity of. The situation is shown in Figure 3 (block diagram) and Figure 4 (
(waveform diagram).

In the parity check method shown in FIG. 3, since the data section 12, parity section 13, parity generation/check circuit 14, and judgment circuit 15 are arranged on the same memory bus, the truth of the data can be verified within the same memory access cycle. Must be determined to be false. The operation during the memory data read cycle is as shown in the waveform diagram of FIG.
outputs the control signal 1b necessary for data reading. Data 1c and parity 1 read by this control signal
d passes through the parity generation/check circuit 14, the result is checked by the determination circuit 15, and the rising edge t11 of the parity error latch timing signal 1h generated by the memory controller 1 within the same access cycle determines whether or not there is a parity error. The information is latched and output to the outside, but the operating speed of the parity generation/check circuit 14 and the judgment circuit 15 is generally very slow.
Even if there is no problem in sending and receiving data read from the data section 12 during read access, the result of the parity check is determined by the parity error latch timing signal 1h.
If the access cycle is not completed by the rising edge t11 of , the access cycle often has to be extended, which significantly degrades system performance.

0004

[Problems to be Solved by the Invention] In the conventional technology, data and parity read by control signals output from a memory controller during a memory data read cycle are
It passes through a parity generation/check circuit, and a circuit that determines its authenticity determines whether or not it is a parity error within that cycle.However, the operating speed of the parity generation/check circuit and determination circuit is generally very slow, so the host However, even if there is no problem in data exchange, if the parity check is not completed, the cycle must be extended, which significantly degrades system performance.

The purpose of the present invention is to improve the above-mentioned drawbacks, to pipeline the operation by latching the read data and parity in a latch circuit, completing the operation of the memory bus, and then checking the parity, so that the memory can be stored in the fastest cycle. This improves system performance by providing access.

[0006]

[Means for Solving the Problems] A parity check circuit of the present invention includes a memory configured with a data section and a parity section, a memory controller that outputs control signals necessary for reading/writing to these memories, and a memory controller that outputs control signals necessary for reading/writing to the memories. A parity generation circuit that generates write parity when writing, a latch circuit that latches read data and read parity using a timing signal from the memory controller and isolates it from the memory bus when reading memory data, and an access cycle depending on the output contents of the latch circuit. and a parity check/determination circuit for determining whether or not there is a subsequent parity error.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining its operation.

In FIG. 1, the parity check/judgment circuit 5 is separated from the memory bus by a latch circuit 7, and by pipelining the operation, the memory access cycle is performed in the shortest possible time, and the response time of the parity check/judgment circuit 5 is shortened. By providing a margin, high-speed memory access is enabled and system performance is improved. The operation at that time will be explained with reference to FIG.

When a request signal a is received from the system bus during a memory read cycle, the memory controller 1 generates a control signal b necessary for access, and data c and parity d are read from the memory by this control signal. These are latched by the rising edge of the latch timing signal e output from the memory controller 1 to the latch circuit 7 at t1 when the host can receive the data, and the access cycle on the host side is completed.

On the other hand, from this point on, the next cycle starts on the system bus, but the parity check/judgment circuit 5
Then, the truth or falsity of the previous access is determined, and the result is determined at time t2. In order to output this result as an external signal, it is latched by the parity error latch timing signal h output from the memory controller 1 at t3 and output as an external signal.

[0011] In this way, by overlapping the cycle for access requests from the system bus with the parity check operation, the memory access cycle can be performed in the shortest possible time, thereby enabling high-speed memory access and improving system performance. .

0012

The parity check circuit of the present invention can determine the shortest memory access cycle in which the host can receive read data, thereby enabling high-speed memory access and improving system performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a waveform diagram illustrating the operation of FIG. 1;

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a waveform diagram illustrating the operation of FIG. 3;

[Explanation of symbols]

1, 11 Memory controller 2, 12 Data section 3, 13 Parity section 4 Parity generation circuit 5 Parity check/judgment circuit 6, 16
Buffer 7 Latch circuit 14 Parity generation/check circuit 15
Judgment circuit

Claims (1)

[Claims] 1. A memory having a parity memory check mechanism, a memory controller that outputs control signals necessary for reading/writing to the memory, a parity generation circuit that generates write parity when writing memory data, and a read when reading memory data. It is characterized by comprising a latch circuit that latches data and read parity using a timing signal from a memory controller and separates it from the memory bus, and a parity check/judgment circuit that determines whether there is a parity error after an access cycle based on the output contents of the latch circuit. parity check circuit.