JPH09282887A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor memory device which performs a write operation without disturbing the operation of a memory in a next access cycle after the confirmation of whether the write operation of the memory can be performed or not by a method wherein a decoded address signal and write data are held. SOLUTION: In a memory write cycle, an address decoder 102 receives an address signal 109 so as to output an address decode signal 110. An address- decode-signal holding circuit 105 holds the address decode signal 110 by using a hold control signal 111 so as to be output to a word line 107. At this time, a write-data holding circuit 104 holds write data 112 by using the hold control signal 111. At the timing of a write pulse 113, a write circuit 103 outputs write data 114 from the write data holding circuit 104 to a bit line 108 so as to be written to a selected memory cell 106. The write pulse 113 is issued within a next access cycle after the confirmation of whether a write operation can be performed or not.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique for speeding up memory access of a memory access device such as a processor.

[0002]

2. Description of the Related Art As a conventional storage control method for reducing the time required for a read-modifier-write operation for a main storage device, for example, in Japanese Patent Laid-Open No. 3-35340, R
In a system including a main memory device having a memory unit formed of a DRAM having an AS (row address strobe) only refresh function and a memory controller controlling the memory device, a memory read modify instruction is executed at the time of reading. By sending a memory write request to the main memory without waiting for the error detection result, the read-modify-write operation time is shortened by an error check cycle when there is no error, while an error is detected. Proposes a control method in which the write enable signal is controlled in the next cycle to suppress the write operation.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the conventional memory access control method disclosed in Japanese Patent Publication No. 40, although it is certainly effective in improving the memory access time of the error detection cycle for the read data of the memory read modify instruction, the SRAM such as a microprocessor is used. This cannot be applied to error detection for a write instruction when a write instruction is issued in a cache system using (static random access memory). For example, at the time of executing a write command to the cache memory, the write operation cannot be executed until a cache hit is confirmed (that is, until write availability is confirmed). Therefore, the above-mentioned Japanese Patent Laid-Open No. 3-35340 discloses. The method of sending a write request to the memory without waiting for the error detection result as described above cannot be applied.

The problem to be solved by the present invention will be described in detail below with reference to FIGS. 5 and 6.

FIG. 5 is a block diagram showing the structure of a conventional semiconductor memory device. Referring to FIG. 5, the conventional semiconductor memory device includes a memory array 501, an address decoder 502, and a write circuit 503. The memory array 501 includes a memory cell 504 and a word line 50.
5, bit line 506. Further, the address signal 507 is supplied to the address decoder 502, and the write data 508 and the write pulse 509 are supplied to the write circuit 503.
Are entered respectively. Note that, in FIG. 5, only one memory cell 504 is shown for simplification among a plurality of memory cells included in the memory array.

The operation of the conventional semiconductor memory device shown in FIG. 5 will be described below with reference to the time chart of FIG.

Address signal 507 (AD1) is decoded by address decoder 502 and output to word line 505. The write operation is performed using the write data 508 (WD1) at the timing of the write pulse 509.
At this time, the timing of the write pulse 509 can be set as soon as the address decoding by the address decoder 502 is completed and output to the word line 505, as shown by the dashed line in FIG. As shown by the solid line in the figure, the write pulse 509 cannot be activated in many cases until the determination of write enable / disable is completed (that is, until the signal value of the write determination signal is determined in the figure). For this reason, it is necessary to increase the length of the write cycle time, which makes it difficult to realize high speed.

Therefore, the present invention has been made in view of the above circumstances, and an object thereof is to solve the problem that, in a write command to a memory, the determination of write enable / disable determines the write cycle and deteriorates the cycle time. It is an object of the present invention to provide a semiconductor memory device capable of speeding up memory access and reducing a write cycle time.

[0009]

In order to achieve the above object, a semiconductor memory device according to the present invention holds a decoded address signal and write data in a system for updating a memory by a write signal instruction of a processor. Thus, it is possible to delay the write operation to the memory without affecting the operation of the next cycle.

The outline of the present invention will be described below. According to the present invention, at the time of write access, the address decode signal obtained by decoding the write access address signal and the write data are respectively held by the holding circuit, and the memory cell selected by the held address decode signal,
Even if the write operation timing of the held write data is delayed by a predetermined time so that the write operation is performed in the memory access cycle subsequent to this write access cycle, the write operation timing is not affected. It was done. That is, according to the present invention, the write operation to the memory can be delayed until, for example, within the next cycle without affecting the operation of the next cycle. Therefore, when executing the write instruction to the memory, In a system that requires a write operation after confirming whether or not the memory can be written, the cycle time of the memory access can be shortened without causing the problem of the increase in the cycle time as in the above-described conventional technique. This enables high speed memory access.

[0011]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram for explaining an embodiment of the present invention. Referring to FIG. 1, the embodiment of the present invention includes a memory array 101, an address decoder 102, a write circuit 103, and a write data holding circuit 104. The memory array 101 also includes an address decode signal holding circuit 105, a memory cell 106, a word line 107, and a bit line 108.

Next, the operation of the embodiment of the present invention will be described with reference to the timing charts of FIGS. 1 and 2.

In the memory write cycle T1, the address signal 109 is decoded by the address decoder 102, and the address decoder 102 outputs the address decode signal 110.

The address decode signal 110 is held in the address decode signal holding circuit 105 controlled by the hold control signal 111, and is output to the word line 107.

The write data 112 is held in the write data holding circuit 104 controlled by the holding control signal 111.

To write data into the selected memory cell 106, the write data 114 held in the write data holding circuit 104 is written by the write circuit 103 at the timing of the write pulse 113, and the bit line 1 is written.
It outputs by outputting to 08.

As shown in FIG. 2, in the embodiment of the present invention, the write pulse 113 is output in the access cycle T2 next to the write cycle T1, and writing to the memory cell 106 is performed in the cycle T2. It is being appreciated. At that time, the operation is not affected whether the next cycle T2 is a read access or a write access.

[0019]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 3, the embodiment of the present invention includes a memory array 301, an address decoder 302, a write circuit 303, a read circuit 304, and a write data holding circuit 305. In addition, the memory array 30
Reference numeral 1 includes an address decode signal holding latch 306, a memory cell 307, a read word line 308, a write word line 309, a read bit line 310, and a write bit line 311. And the memory cell 307
Is composed of data holding inverter circuits 312 and 313, a data reading NMOS transistor 314, and a data writing NMOS transistor 315.

Next, the operation of the embodiment of the present invention will be described in detail with reference to the timing charts of FIGS.

In the memory write cycle T1, the address signal 316 is decoded by the address decoder 302 and output to the read word line 308.
The write word line 3 held in the address decode signal holding latch 306 controlled by the latch control signal 317
09 is output.

The write data 318 is the latch control signal 31.
It is held in the write data holding latch circuit 305 controlled by 7.

The write pulse 319 is output if it is writable after the writability is determined, and the write data 320 held in the write data holding latch circuit 305 is output to the write bit line 311. Writing is performed to the memory cell 307 (in FIG. 4, before the finalized output of the read word line 308 in the next access cycle T2 is finalized). As the address at this time, the address held in the address decode holding latch 306 is used.

In the memory access cycle T2, when the read word line 308 is accessed after address decoding of the read access address, the contents of the memory cell 307 are output to the read bit line 310, and the read circuit 304 outputs the read data 321. Is output.

[0026]

As described above, according to the present invention,
By holding the decoded address signal and write data, the write operation to the memory can be delayed without affecting the operation of the next cycle, which speeds up the memory access and reduces the cycle time.

[Brief description of drawings]

FIG. 1 is a diagram for describing an embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation of the exemplary embodiment of the present invention.

FIG. 3 is a circuit diagram showing one embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of one embodiment of the present invention.

FIG. 5 is a block diagram for explaining a conventional example.

FIG. 6 is a time chart explaining the operation of a conventional example.

[Explanation of symbols]

 101 memory array 102 address decoder 103 write circuit 104 write data holding circuit 105 address decode signal holding circuit 106 memory cell 107 word line 108 bit line 109 address signal 110 address decode signal 111 holding circuit control signal 112 write data 113 write pulse 114 write data (After holding) 301 memory array 302 address decoder 303 write circuit 304 read circuit 305 write data holding latch 306 address decode signal holding latch 307 memory cell 308 read word line 309 write word line 310 read bit line 311 write Bit line 312, 313 Data holding inverter circuit 314 Data reading NMOS transistor 15 data writing NMOS transistor 316 address signal 317 latch control signal 318 write data 319 write pulse 320 write data (after latching) 321 read data 501 memory array 502 address decoder 503 write circuit 504 memory cell 505 word line 506 bit line 507 address signal 508 write data 509 write pulse

Claims (4)

[Claims] 1. In a system for updating a memory by a write signal instruction of a processor, by holding a decoded address signal and write data respectively, writing to the memory without affecting the operation of the next cycle. A semiconductor memory device capable of delaying an operation. 2. A memory, wherein an address decode signal obtained by decoding a write access address signal by an address decoder during write access and write data are respectively held in a holding circuit, and selected by the held address decode signal. Even when the held write data is written into the cell within the memory access cycle next to the write access cycle with the write operation timing being shifted, the influence on the operation of the next memory access cycle is exerted. A semiconductor memory device characterized by being configured so as not to exist. 3. The semiconductor memory device according to claim 2, wherein the write operation timing is determined based on a confirmation result of whether or not writing to the memory cell is possible. 4. The output of the address decoder is used as a read word line, the output of the address decode signal holding circuit is used as a write word line to select the memory cell, and the output of the write data holding circuit is used. Writing to the memory cell is performed by outputting to the write bit line via the write circuit, while when reading data from the memory cell, the data is read via the read bit line connected to the memory cell. 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is read out.