JPS59140685A - Data processor having hierarchical cache memory - Google Patents

Abstract

PURPOSE:To enable a central processing unit to read out data at a high speed without deteriorating the hit ratio by constituting hierarchical cache memory of a central processing unit, an address converter and the 1st and 2nd cache memories. CONSTITUTION:When a central processing unit 2 delivers a reading request, the address to be converted among virtual addresses used for reading is sent to an address converter 3. In parallel to this action, an offset address among the virtual addresses used for reading is sent to the 1st cache memory 6. A converted addresses of two physical addresses put on address lines 120 and 103 and 104 are sent to a address comparator 64 for comparison with each other. When the coincidence is obtained between these two addresses, a gate 63 is opened by the control signal put on a control line 110. Then the date of the 1st cache memory 6 is put on a data line 20 and then sent to the unit 2. If no coincidence is obtained from the comparison, the gate 63 is closed to give an indication to check whether the read-out data of the 2nd cathe memory 7 is effective or not.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data processing device that allows a central processing unit to read data from a main memory at high speed, and in particular, to a data processing device that allows a central processing unit to read data at high speed using a cache memory. The present invention relates to a data processing device capable of processing data.

Prior Art Conventionally, in this type of data processing device, a cage-memory connection has been used in order for the central processing unit to read data at a higher speed than the main memory. However, as shown in FIG.

In the conventional data processing device 1, the cache memory 4 is provided between the address conversion device 3 and the main memory 5, and in the process of reading data by the central processing unit 2, the cache memory 4 is necessarily connected to the address conversion device 3. It was necessary to convert the virtual address into a physical address in the step 1 and access the cache memory 4 using this physical address.

If such a method is adopted, there is a drawback that the time for continuous photographing of the address translation device 3 is always added to the time when the central processing unit 2 obtains the read data.

Furthermore, in the method of directly accessing the cache memory using a virtual address, it is possible to access the cache memory at high speed without passing through an address translation device, but it has the following drawbacks. In the case of so-called direct memory access (DMA) transfer, in which data is written directly from the peripheral device to the main memory, the cache memory holds a copy of the main memory data (7), so the main memory is DMA When the cache memory is modified in a transfer.

You must determine whether you have a copy of the changed data and, if so, take steps to update that copy. However, in this case, since the addresses used in DMA transfers are executed using physical addresses, the cache memory accessed using virtual addresses will cause the area of main memory changed by the DMA transfer to become its own memory area. Determining whether there is a corresponding part has the drawback of requiring a reverse translation from a physical address to a virtual address. This inverse transformation is extremely difficult and therefore impractical.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a data processing device that solves the above-mentioned conventional drawbacks and enables a central processing unit to read data at high speed.

Structure of the Invention The data processing device of the present invention includes a central processing unit that executes an operation, an address translation device that converts a virtual address into a physical address, and a first cache memory that is accessed using an offset address in the virtual address. , a second cache memory that is accessed using a physical address translated by an address translation device.

In the data processing apparatus of the present invention having such a configuration.

When the central processing unit receives a read request in accessing the main memory, the central processing unit causes the address translation device and the first cache memory to operate in parallel, checks whether the first cache memory has been hit, and in the case of no hit, determines whether the first cache memory has been hit or not. , the second cache memory is accessed using the physical address translated by the address translation device.

Principle and operation of the invention Next, the principle and operation of the present invention will be explained. As shown in FIG. 2, the virtual address used by the central processing unit when reading data necessarily consists of an offset address part that does not undergo address translation in the address translation device 3, and a translated address part that undergoes address translation. have.

Using this offset address, a first cache memory accessed by the offset address is provided. The first cache-memory is.

Because it is accessed using an offset address.

It can operate completely simultaneously with the address translation device 3. Then, a translated address of the physical addresses shown in FIG. 2 is read from the directory section of the first cache memory, and data is read from the data section. Further, the address translation device 3 is given a translated address among the virtual addresses, and generates a physical address by converting this into a translated address.

If the directory section of the first cache memory and the translated address in the physical address translated by the address translation device 3 match (hit), the data read from the data section of the first cache memory is transferred to the central processing unit. can be sent to the central processing unit at high speed as requested data. On the other hand, when the translated addresses in the physical addresses do not match (no hit), the second cache memory is accessed using the physical address (consisting of translated address and offset address) translated by address translation device 3.

In this way, when reading from the first cache memory, high-speed access is possible without adding the conversion time of the address translation device 3. Also, the second cache memory is required for the first order of reasons. As shown in FIG.

Offset addresses have a relatively small address width, so the first cache memory can be configured using high-speed, small-capacity memory elements, increasing speed, but the drawback is that the memory capacity is small, so there is a high probability of a no-hitter. occurs. As a means of compensating for this, a large-capacity second cache memory that is accessed using physical addresses that have been converted in the same way as in the past is provided to avoid the high probability of a no-hitter using only the first cache memory. It has been resolved.

Embodiments of the Invention Next, embodiments of the invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram showing the configuration of an embodiment of a data processing device according to the present invention. In fig.

1' indicates a data processing device of the present invention, and a central processing device 2
．． Address translation device 3. It is composed of a first cache memory 6 and a second cache memory 7. Further, 5 is a main memory, 8 is a peripheral device control unit, and 9 is a common bus.

FIG. 4 shows details of the data processing device 1' in FIG. 3. When the central processing unit 2 makes a read request, the translated address among the virtual addresses used for the read is transferred to the address line 101.
It is sent to the address translation device 3 via. In parallel with this operation, the offset address among the virtual addresses used for reading is

the first cache memory 6 via the address line 102;
sent to. From the directory section 61 of the first cache memory 6, the translated address in the physical address is read out and placed on the address line 120, and the data section 62
From there, data is read out and placed on the data line 201. On the other hand, the lower-order side of the translated address in the physical address generated by the address conversion device 3 is the address line 1.
On 03.

The upper side is placed on the address line 104.

The translated addresses in the two physical addresses carried on the address lines 120 and 103 and 104 are sent to the address comparator 64 and compared, and if they match, the control signal carried on the control line 110 causes the dart 63 is opened, data from the first cache memory 6 is loaded onto the data line 200, and sent to the central processing unit 2. On the other hand, if the addresses do not match in the address comparator 64, the controller 3 is closed by the control signal multiplied by the control line 20.

It instructs to check whether the read data of the second cache memory 7 is valid.

Upon receiving the above instruction, the second cache memory 7
It is accessed using the offset address carried on the address line 102 and the lower-order converted address carried on the address line 03. From the directory section 71 of this second cache memory 7.

The higher-order translated address among the read physical addresses is read and placed on the address line 121.

Data is read from the data section 72 and the data line 2
It will be put on board 02. The upper translated address read from the directory section 71 and the upper translated address generated by the address translation device 3 and placed on the address line 104 are
The addresses are sent to the address comparator 74 for comparison, and if they match, the gate 73 is opened by a control signal placed on the control line 111, and the data from the second cache memory 7 is placed on the data line 200 and sent to the central processing unit 2. On the other hand, if the addresses do not match in the address comparator 74, the control line 111
A control signal placed on the bus instructs the bus control circuit 75 to close the gate 73 and read data from the main memory 5.

Effect of the invention As is clear from the above description, there are two aspects of the present invention.

By making the cache memory hierarchical, there is an effect that the central processing unit can read data at high speed without reducing the hit rate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional data processing device, FIG. 2 is a diagram showing the relationship between virtual addresses and physical addresses translated by an address translation device, and FIG. 3 is a data processing device according to the present invention. FIG. 4 is a block diagram showing the data processing apparatus shown in FIG. 3 in detail. 1.1'...Data processing device, 2...Central processing unit. 3...Address translation device, 4...Catch-memory. 5... Main memory, 6... First cache memory, 7
. . . second cage-memory, 8 . . . peripheral device control section. 9... Common lotus, 61... Directory section of first cache memory, 62... Data section of first cache memory, 63... Dirt, 64... Address comparator, 71... - Directory section of the second cache memory, 7.2... Data section of the second cache memory. 73...Ke"-), 74...Address comparator, 75
...Path control circuit, 101 to 104, 120, 121
...Figure 1 2 ■ 1 Figure 3

Claims (1)

[Claims] 1. A central processing unit that executes operations and sends out a virtual address consisting of a translated address and an offset address when reading data, and a central processing unit that converts the translated address into a translated address. an address translation device that converts an address and the offset address into a physical address; a first cache memory that operates in parallel with the address translation device and is accessed using the offset address; A data processing device having a hierarchical cache memory comprising a second cache memory that is accessed using the physical address in the case of a no-hit.