JPS61125658A - Address converting system - Google Patents

Abstract

PURPOSE:To reduce hardware quantity by providing an address conversion mechanism into a memory device to convert a logical address into a real address. CONSTITUTION:A CPU1, a channel CHU2 and a main memory MMU4 containing an address conversion mechanism ATN3 are connected to a path 5 in a computer system. Both the CPU1 and 2 share the MMU4 and produce logical addresses in response to the progress of processing to try to give an access to the MMU4. Those produced logical addresses are supplied as they are to the ATN3 via the path 5 to be converted into real addresses. These real addresses are supplied to the MMU4 and used for access operations. Thus just a single address conversion mechanism suffices for reduction of the hardware quantity.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to an address conversion method, particularly an address conversion method for converting a logical address into a real address in an information processing device in which a plurality of devices share a storage device. Regarding.

(Prior Art) In a conventional information processing device of this type, the device that generates the logical address is individually equipped with an address conversion mechanism for converting it into a real address, performs address conversion internally, and the storage device stores the real address. is being sent.

(Problems to be Solved by the Invention) In such a conventional configuration, there is a problem that an address translation mechanism is required for each device that generates a logical address, which increases the amount of hardware.

Therefore, an object of the present invention is to provide an address translation method that reduces the amount of hardware.

(Means for Solving the Problems) To this end, the method of the present invention is an address conversion method for an information processing device in which a plurality of devices share a storage device, in which a logical address generated by the device is converted to the storage device. The present invention is characterized in that an address conversion mechanism for converting into a real address of the device is provided in the storage device.

(Embodiment) Referring to FIG. 1 showing an embodiment of the present invention, this embodiment has a central processing unit (hereinafter referred to as CPU) 1 and a channel (
(hereinafter referred to as CHU) 2, and an address translation mechanism (hereinafter referred to as AT
This is a combiator system in which a main storage unit (hereinafter referred to as MMU) 4 with a main storage unit (hereinafter referred to as MMU) 3 is connected to a path 5.

CPU1 and CHU2 share MMU4,
As the process progresses, a logical address is generated and an attempt is made to access the MMU 4. The generated logical address is directly input to the ATN 3 via the bus 5, converted into a real address in the ATN 3, and then supplied to the MMU 4 for use in access operations.

FIG. 2 shows details of the ATN 3 together with the MMU 4. Second
Referring to the figure, this ATN 3 includes logical address registers 30. It is composed of an associative memory 31, an address conversion circuit 32, a real address register 33, a data register 34, and an error reporting circuit 35.

First, the logical address on the path is logical address register 3.
0, and the logical page address 300 of this logical address paste S is input to the associative memory 31 and the address conversion circuit 32.
Then, address 30 within the page among the logical addresses t
1 is supplied as is to the real address register 33, respectively.

The address conversion circuit 32 uses the logical page address 300 supplied from the logical address conversion module J30 as a key to obtain a real page address corresponding to the logical page address 300. Part of the correspondence table with addresses is in the associative memory 31
is stored in

The associative memory 31 is constituted by a set-associative high-speed memory, and can obtain real page addresses at a higher speed than the address conversion speed in the address conversion circuit 32. Therefore, in order to obtain the real page address corresponding to the logical address set in the logical address register 30, first, it is started by checking whether it is stored in the associative memory (hit) or not (miss).

The hit/miss check is based on a principle similar to that often used in cache memory, in which a plurality of real page addresses are read using a part of the logical page address 300 as a key, and these real page addresses are This is done by matching K with the remaining bits of the logical page address 300.

When there is a hit, the associative memory 31 outputs the matching real page address 310 to the real address register 33. This real page address 310 is the in-page address 301 previously input to the real address register 33.
Together with this, a real address 330 is formed. The associative memory 31 outputs a memory cycle start signal 311 to the MMU 4 in order to start accessing the MMU 4 using the real address 330 obtained in the real address register 33 in this way.

Further, when a miss occurs, the associative memory 31 outputs an address conversion start signal 312 to the address conversion circuit 32. Address conversion circuit 32 starts address conversion in response to address conversion start signal 312. The real page address 320 obtained as a result of address conversion is once registered in the associative memory 31 and also supplied to the real address register 33. Registration in the associative memory 31 is performed based on the program's tendency that once a logical page address is hit, there is a high probability that it will occur subsequently.

Note that the data register 34 holds continuous data from the MMU 4 and data written to the MMU 4, and these data are exchanged via the path 5 between the MMU 4 and the CPU 1 or CHU 2 that made the access request. Further, the error reporting circuit 35 holds address translation errors 321 in the address translation circuit 32 and memory errors 40 in the MM05, and reports these error information to the CPUI, Vi, and cHU 2 via the path 5.

(Effects of the Invention) According to the present invention, by employing the above configuration, only one address translation mechanism is required, so that the amount of hardware can be reduced to 5.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows the configuration of an address translation mechanism in this embodiment. 1...Central processing unit (CPU), 2...
・Channel (CHU), 3... Address translation mechanism (ATN), 4... Main memory unit (MMU),
5...Pass.・Go 1, Agent Patent Attorney Susumu Hara T-Par' $l(!l $2 α1

Claims (1)

[Claims] In an address conversion method for an information processing device in which a plurality of devices share a storage device, an address conversion mechanism is provided in the storage device for converting a logical address generated by the device into a real address of the storage device. An address conversion method characterized by: