JPS6413649A - Information processor - Google Patents
Information processorInfo
- Publication number
- JPS6413649A JPS6413649A JP62170064A JP17006487A JPS6413649A JP S6413649 A JPS6413649 A JP S6413649A JP 62170064 A JP62170064 A JP 62170064A JP 17006487 A JP17006487 A JP 17006487A JP S6413649 A JPS6413649 A JP S6413649A
- Authority
- JP
- Japan
- Prior art keywords
- cache memory
- capacity
- enlarging
- cache
- array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE:To enlarge the capacity of a cache memory without enlarging an access time by minimizing a capacity for a first complicated cache memory, enlarging the capacity for a second simple cache memory and judging the registering condition of the cache memory with first and second cache memories. CONSTITUTION:A second address array 1 and a first data array 2 are the first cache memory of two-level constitution indexed by an address register 13 and a second address array 6 and a second data array 7 are the second cache memory of four-level constitution indexed by an address register 14 or an address register 25. When the data are not registered by both the first and second cache memories, the processor has a means to activate a block load to the first cache memory and the second cache memory for a main storage device. Thus, the capacity of the cache memory can be enlarged without enlarging the access time of the cache memory.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62170064A JPS6413649A (en) | 1987-07-07 | 1987-07-07 | Information processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62170064A JPS6413649A (en) | 1987-07-07 | 1987-07-07 | Information processor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6413649A true JPS6413649A (en) | 1989-01-18 |
Family
ID=15897960
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62170064A Pending JPS6413649A (en) | 1987-07-07 | 1987-07-07 | Information processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6413649A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007504552A (en) * | 2003-09-03 | 2007-03-01 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Micro TLB and micro tag for reducing processor power |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59140685A (en) * | 1983-02-01 | 1984-08-13 | Nec Corp | Data processor having hierarchical cache memory |
-
1987
- 1987-07-07 JP JP62170064A patent/JPS6413649A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59140685A (en) * | 1983-02-01 | 1984-08-13 | Nec Corp | Data processor having hierarchical cache memory |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007504552A (en) * | 2003-09-03 | 2007-03-01 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Micro TLB and micro tag for reducing processor power |
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