KR980011450A - High-speed memory device - Google Patents

Abstract

More particularly, the present invention relates to a high-speed memory device, and more particularly, to a high-speed memory device comprising: means for constructing a request packet; A judging means for receiving a row address from the means constituting the request packet and discriminating a hit and a miss and generating a corresponding miss signal; An instruction code decoding means for receiving and decoding an instruction code from the means constituting the request packet in response to the miss signal of the discrimination means; Latch means for latching the output signal of the decoding means; Latch control means for generating a control signal for controlling the latch means to control the memory; And memory means enabled in response to a signal detected by the latch means.

Therefore, according to the present invention, there is no need to generate the same command at the time of occurrence of a miss, so that the time for accessing the memory is shortened, thereby improving the operation efficiency and reducing the waiting time from the first request to the data output by about 1 to 2 clocks .

Description

High-speed memory device

The present invention relates to a high-speed memory device, and more particularly, to a high-speed memory device for increasing the efficiency of a system controller and reducing memory latency.

Generally, the Rambus DRAM, which is implemented with a high frequency and a high bandwidth, is composed of a DRAM and a cache, which are pure memory portions. The cache is a sense amplifier inside the DRAM, and serves as an interface between a DRAM and a request packet. Rambus DRAMs enable high-speed data access by making good use of this interface part.

As shown in FIG. 1, a conventional semiconductor memory device using a packet type command includes a command packet, a request packet 10 in which a row address and a column address are sequentially connected, and a row address portion of the request packet 10 A hit / miss discriminator 20 for detecting and detecting a hit / miss, an instruction code decoder 40 for detecting and decoding an instruction code portion of a request packet, And a memory 60 that operates in accordance with the output signal of the command code decoder to be controlled.

The discriminator 20 accepts a command of a request packet 10, which is a series of data strings, to make a Hit or Miss decision, After delivering it to the controller, it generates an internal signal that controls the DRAM part.

At this time, a signal for a miss is transmitted to the system controller by an Acknowledge Packet. Therefore, the discriminator 20 stores the currently accessed row address and compares it with the stored row address when a new command is input. If the result of the comparison is the same, if the heat is wrong, a mistake is generated. If a miss occurs, the word line designated by the new row address generating the miss is enabled in the DRAM, and the discriminator 20 senses and stores the cell data in the memory.

Thereafter, a new request packet is received, and a row address inputted and stored in the discriminator at the time of inputting the previous request packet is compared with the currently inputted row address to determine a miss or a hit again.

For example, if a data read operation is performed for row address 0 of the DRAM by the controller and then row address 1 of the DRAM is accessed by the controller, a miss occurs because the row address between the controller and memory is different . Once a miss occurs, the command code (OP code) received in the request packet is ignored and the data to be sensed as a new row address is stored in the determiner 20.

2, in the case of a read hit, a data value specified by an address is output after one operation cycle of a request packet and a liquid-flow packet. In the case of a read miss, After keeping the interval specification between the packet and the request packet, the same command as the command that caused the miss should be given to the memory. This is the action that occurs after accepting the incoming packet from memory. Finally, it takes two cycles until data is finally output.

Thus, as described above, when the controller wishes to access another lower address in the memory, the same instruction must be given twice. This results in a loss of efficiency of the controller and limits the utilization time of the controller, resulting in a constant waiting time of the request packet regardless of the diram speed.

It is an object of the present invention to provide a high-speed memory device for increasing the efficiency of a system controller and reducing memory latency in order to solve the problems of the related art.

According to an aspect of the present invention, there is provided an apparatus comprising: means for constructing a request packet; A judging means for receiving a row address from the means constituting the request packet and discriminating a hit and a miss and generating a corresponding miss signal; An instruction code decoding means for receiving and decoding an instruction code from the means constituting the request packet in response to the miss signal of the discrimination means; Latch means for latching the output signal of the decoding means; Latch control means for generating a control signal for controlling the latch means to control the memory; And memory means enabled in response to a signal detected by the latch means.

1 is a block diagram showing a configuration of a conventional memory device;

FIG. 2 is a timing chart showing an operation state of a conventional memory device; FIG.

FIG. 3 is a block diagram showing a configuration of a memory device according to the present invention; FIG.

FIG. 4 is a timing chart showing an operation state of the memory device according to the present invention; FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention.

FIG. 3 is a block diagram showing a configuration of a high-speed memory device according to the present invention.

The memory device according to the present invention includes a command packet, a request packet 10 in which a row address and a column address are sequentially connected, and a hit / miss discriminator 10 for detecting a row address portion of the request packet 10 and discriminating a hit / (20), an instruction code decoder (40) for detecting and decoding an instruction code portion of the request packet, and a latch for temporarily storing an output signal of an instruction code decoder controlled by an output signal of the hit / A latch control unit 80 for operating a row address strobe cycle to generate a signal for controlling the latch, and a memory 100, which is enabled in accordance with the output signal of the latch.

The following is a description of the operation of a preferred embodiment of the present invention.

The system controller accesses the memory cell using a packet-type command to the Rambus DRAM. Rambus DRAM uses the sense amplifier of the DRAM, which is a pure memory part, with the cache memory of the system and uses it as an interface to enable high-speed operation. The Rambus DRAM receives the request packet by the interface and compares the row address in the packet with the row address of the interface to determine a miss or a hit.

In the present invention, the request packet 10 is received and the row address in the packet is input to the hit / miss discriminator 20 for discriminating a miss or a hit, and the previously ignored command code (OP code) Is stored in the latch 60 proposed in the invention and is placed in the latch state while waiting for the signal A.

A precharge, a sense, a latch control (ImpRestore), and a holdoff (Hold) operation from a latch control unit (RAS State Mashine) 80 operating a row address cycle in the interface of FIG. -Off) occurs sequentially with the time interval set in the register. The signal A is a third-occurring signal ImpRestore. When this signal is enabled, the command code is decoded to enable the latched DRAM control signal to proceed the operation of the request packet without a new request packet as in FIG.

As described above, according to the present invention, since it is not necessary to generate the same command when a miss occurs, the time for accessing the memory is shortened to improve the operation efficiency, and the waiting time from the first request to the data output is also about 1 to 2 clocks There is an effect that can be reduced.

Claims (2)

Means for constructing a request packet; A judging means for receiving a row address from the means constituting the request packet and discriminating a hit and a miss and generating a corresponding miss signal; An instruction code decoding means for receiving and decoding an instruction code from the means constituting the request packet in response to the miss signal of the discrimination means; Latch means for latching the output signal of the decoding means; Latch control means for generating a control signal for controlling the latch means to control the memory; And memory means enabled in response to a signal detected by said latch means. The high-speed memory device according to claim 1, wherein said latch control means for generating a free charge, sense, latch control and hold-off signal uses a latch control signal. ※ Note: It is disclosed by the contents of the first application.