KR19990086857A - Cache system with serial / parallel cache structure with selective control - Google Patents

Abstract

The present invention relates to a cache system for evaluating hit rates in a cache system that accommodates a serial cache structure and a parallel cache structure, and optionally using a parallel or serial cache structure in accordance with the evaluated hit rate. The prior art cache structure has a drawback that the data access time is increased because the cache is first accessed and a cache miss occurs, and then the main memory access cycle is started again. If the bus was occupied by another master device when accessing cache and main memory at the same time, the CPU could not access main memory, so it was necessary to wait for the bus to terminate and perform the operation. However, in the present invention, the performance of the system as a whole can be improved by selecting a serial cache and a parallel cache structure according to the evaluated hit rate.

Description

Cache system with serial / parallel cache structure with selective control

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a cache system that accommodates a serial cache structure and a parallel cache structure. In particular, the cache controller evaluates a hit rate and, according to the evaluated hit rate, a parallel cache structure or a serial cache structure. It relates to a cache system for optional use.

In general, computer systems access data in order to improve the performance of the entire system by compensating for the disadvantage of main memory, which is relatively slow compared to the processing speed of the Central Processing Unit (CPU). Use a fast cache. The cache is placed between the CPU and the main memory and stores some of the data in the main memory that is frequently used by the CPU. This configuration allows the CPU to preferentially take data from the fast cache, increasing the CPU's data throughput rate and ultimately improving the overall system performance.

The cache configuration used in the cache system is a way for the CPU to access the cache and main memory in serial or parallel. The parallel cache system occupies the system bus to read the desired data from the CPU and simultaneously reads the cache and main memory. When a cache hit occurs, the CPU accesses the cache and reads the desired data. When the CPU reads the desired data from the cache, the access cycle to main memory is terminated. If a cache miss occurs that does not find the desired data, the CPU continues the main memory access cycle and reads the desired data from main memory. However, since the parallel method accesses main memory simultaneously through the cache and the system bus, there is an advantage in that the desired data can be read from the main memory when a cache miss occurs, but in the case of a hit or a miss, the CPU must occupy the bus. There is a drawback that no other master device can occupy the bus.

In contrast, in a serial cache system, the data requested by the CPU is first retrieved from the cache. If the data desired by the CPU is in the cache, as a cache hit, the CPU reads data from the cache without occupying the system bus. On the other hand, if the data the CPU wants is a cache miss that is not in the cache, the CPU begins the main memory access cycle, occupies the system bus, and reads data from main memory. Since separate read operations are performed to the cache and main memory, data can be read from the cache at high speed without occupying the system bus at the time of a cache hit, so that another master device can occupy the system bus. However, in the case of a cache miss, the main memory access cycle is restarted, thus delaying the data read from the CPU.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a cache structure having a fast access speed according to a cache hit rate in a cache system that accommodates a serial cache structure and a parallel cache structure. To provide a cache control device of the cache system to improve the performance of the cache system as a whole.

In order to achieve the above object, the present invention provides a cache system having a CPU, a main memory for providing data to the CPU, a cache storing some data of the main memory frequently used by the CPU, and an enable signal. A first buffer providing a serial path between the cache and the main memory and the CPU or closing the serial path, and a second buffer providing a parallel path between the cache and the main memory and the CPU or closing the parallel path according to the enable signal. And a cache controller for determining a hit / miss of the cache and generating a signal for selectively enabling the first buffer or the second buffer according to the determination result.

1 is a block diagram of a cache system according to the present invention;

FIG. 2 is a block diagram illustrating a connection state between a cache controller shown in FIG. 1 and a peripheral device connected to the cache controller.

<Description of the code | symbol about the principal part of drawing>

102: CPU 104: first buffer

106: cache control unit 108: second buffer

110: cache 112: main memory

114: DMA 118: system bus

202: CPU matching unit 204: Hit rate evaluation unit

206: serial / parallel control unit 208: tag control unit

210: data RAM control unit 212: buffer control unit

214: main memory matching unit

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 shows a block diagram of a cache system according to the present invention.

The cache system of the present invention provides a main memory 112 that provides data to a bus master device occupying the system bus 118, and reads information from the main memory 112 and executes commands according to the information and instructions according to the information. The CPU 102, the cache 110 in which some data of the main memory 112 frequently used by the CPU 102 are stored, and the cache 110 are selectively enabled under the control of the cache controller 106. Determine the first and second buffers 104 and 108 and the cache 110 hits / misses that provide a path through which the &lt; RTI ID = 0.0 &gt; Cache control unit 106 for controlling.

The NOT gate 105 is connected between the cache control unit 106 and the first buffer 104 or the second buffer 108 such that the first buffer 104 and the second buffer 108 perform opposite operations. In the present invention, it is shown as being connected between the cache control unit 106 and the first buffer 104.

The cache controller 106 determines the cache 110 hit / miss between the cache 110 and the main memory 112 and controls to open only one of the buffers 104 and 108 according to the determination result. The enable signal or the disable signal is sent to the first buffer 104 or the second buffer 108.

The enable signal generated by the cache controller 106 is directly input to the second buffer 108 and inverted through the NOT gate 105 to be input to the first buffer 104 as the disable signal. Thus, the first buffer 104 is in a disabled state and the second buffer 108 is in an enabled state. As a result, the path between the CPU 102 and the cache 110 and the main memory 112 is opened through the second buffer 108 and the system bus 118 and the path of the first buffer 104 is closed. This is formed as a parallel type structure in which the CPU 102 can access the cache 110 and the main memory 112 and read data at the same time by occupying the system bus 118 when the system bus 118 is idle.

In contrast, the disable signal generated by the cache controller 106 is directly input to the second buffer 108 and inverted through the NOT gate 105 to be input to the first buffer 104 as an enable signal. Thus, the first buffer 104 is enabled and the second buffer 108 is disabled. As a result, the path between the CPU 102 and the cache 110 is opened through the first buffer 104 and the path of the second buffer 108 is closed. This is formed as a serialized structure in which a path is provided for the CPU 102 to first read from the cache 110.

In a serial cache structure with the first buffer 104 open, the CPU 102 reads data from the cache 110 via the first buffer 104 and the cache control unit 106. However, if a cache miss occurs, the CPU 102 checks the occupancy state of the system bus 118 through the first buffer 104 and the cache controller 106. If the system bus 118 is not occupied, the CPU 102 occupies the system bus 118 and reads data from the main memory 112.

In a parallel cache structure with the second buffer 108 open, the CPU 102 checks the occupancy of the system bus 118 via the second buffer 108. When the system bus 118 is not occupied, the CPU 102 reads data from the main memory 112 and simultaneously reads data from the cache 110 through the cache controller 106.

FIG. 2 illustrates a block diagram showing details of the cache controller 106 shown in FIG. 1 and a peripheral device connected to the cache controller 106.

The cache controller 106 includes a CPU matching unit 202, a hit rate evaluation unit 204, a serial / parallel control unit 206, a tag control unit 208, a data RAM control unit 210, a buffer control unit 212, and a main unit. Memory matching unit 214.

The first buffer 104 or second buffer 108 is optionally set to disable or enable before the cache system initially operates. In a preferred embodiment of the present invention, the cache system is described under the assumption that the first buffer 104 is enabled and the second buffer 108 is disabled and set in a serial cache structure.

The tag control unit 208 searches whether the address that the CPU 102 is looking for is in the tag area of the cache 110. As a result of the search, if the address to be searched for by the CPU 102 includes a tag area, the tag control unit 208 determines that the hit is made, and provides a hit state signal indicating the hit to the hit rate evaluation unit 204 and at the same time the cache ( Data corresponding to the corresponding tag area in 110 is transmitted to the CPU 102 through the data RAM control unit 210, the CPU matching unit 202, and the first buffer 104.

However, if the address that the search result tag control unit 208 is looking for in the CPU 102 is not present in the tag of the cache 110, it is determined as a cache miss and the CPU matching unit 202 and the first buffer 104 are used. The CPU 102 is notified of the miss, and a miss state signal indicating the miss is provided to the hit rate evaluation unit 204. The CPU 102 then finds the required data in the main memory 112. The data retrieved from the main memory 112 is transmitted to the CPU 102 through the system bus 118, the main memory matching unit 214, the CPU matching unit 202, and the first buffer 104.

The above-described process is repeated each time the CPU 102 approaches the cache 110, and the hit rate evaluation unit 204 receives information indicating a hit or a miss from the tag control unit 208 and misses it. The miss count is increased by "1", and in the case of a hit, the hit count is increased by "1". When the above-described process is repeated and a certain period of time is reached, the hit rate evaluator 204 calculates the hit rate using the information of the miss count and the hit count.

The hit rate obtained by the hit rate evaluator 204 is transmitted to the serial / parallel control unit 206, and the serial / parallel control unit 206 determines whether the hit rate provided by the hit rate evaluator 204 is greater than or less than a preset rate. Judge.

For example, assuming that the preset ratio is "0.9" and the hit ratio calculated by the hit rate evaluation unit 204 is 0.9 or more, the serial / parallel control unit 206 compares the calculated hit ratio with the preset ratio. When the calculated hit ratio is greater than or equal to the preset ratio, a signal for selecting a serial cache structure is transmitted to the buffer controller 212. The buffer control unit 212 generates a disable signal in order to switch the cache system to the serial type in response to the serial type selection signal. The disable signal is input to the second buffer 108 while input to the first buffer 104 via the NOT gate 105 as an enable signal. Thus, the first buffer 104 is enabled and the second buffer 108 is disabled, thereby forming a path of serial structure.

However, if the hit rate calculated by the hit rate evaluation unit 204 is smaller than the preset rate, the serial / parallel control unit 206 transmits a signal for selecting the parallel scheme cache structure to the buffer control unit 212. The buffer controller 212 transmits an enable signal to the second buffer 108 and removes the disable signal formed through the NOT gate 105 in order to switch the cache system to the parallel scheme in response to the parallel scheme selection signal. 1 is sent to the buffer 104. Thus, by enabling the second buffer 108 and disabling the first buffer 104, a path of parallel structure between the CPU 102 and the cache 110 is formed.

As described above, the present invention has the effect of increasing the performance of the entire system by selecting the cache of the serial system and the cache of the parallel system according to the hit rate.

Claims (3)

A cache system having a CPU, A main memory for providing data to the CPU; A cache storing some data of the main memory frequently used by the CPU; A first buffer providing a serial path between the cache and the main memory and the CPU according to an enable signal; A second buffer providing a parallel path between the cache and the main memory and the CPU in accordance with an enable signal; A cache for determining a hit / miss rate of the cache and generating the enable signal in which the first buffer or the second buffer selectively provides a serial path or a parallel path according to a result of the determination; Cache system comprising a control unit. The method of claim 1, The cache control unit: A tag control unit for determining a cache miss and a hit for a cache accessed by the CPU; A hit rate evaluator configured to calculate a hit rate from the tag controller using a hit / miss state signal indicating the hit / miss; The hit rate calculated by the hit rate evaluator is compared with a preset rate to generate a serial type selection signal when the hit rate is greater than or equal to the preset rate, and when the hit rate is less than the preset rate, the parallel type A serial / parallel control unit for generating a selection signal; The enable signal is provided to the first buffer according to the serial mode selection signal generated by the serial / parallel control unit, and the enable signal is provided to the second buffer according to the parallel mode selection signal generated by the serial / parallel control unit. And a buffer control unit. The system of claim 2 wherein the system is: And an inverter configured to invert an enable signal generated by the cache controller to provide an inverted signal to the first buffer or the second buffer so that the first buffer and the second buffer perform an opposite operation. Cache system.