JPH10124383A - Memory access control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the memory access control system which makes memory access faster by switching and using speeding-up technique for the memory access. SOLUTION: Information regarding the kind of memory access is added as additional information to address information and outputted from a CPU 1. The said additional information is decoded by access kinds through an additional information decoding part 21. According to the output of the decoding part 21, an access kind judgement part 22 determines speeding-up technique by the access kinds. The speeding-up technique which is thus determined is used by a memory timing control part 23 to control the execution timing of the said memory access.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory access control system, and more particularly to a technique for speeding up memory access.

[0002]

2. Description of the Related Art Conventionally, when a CPU accesses a memory, a memory control unit operates uniformly assuming the same type of access method. That is, the speed of the memory access is increased by only a single speed-up method.

[0003] For example, Japanese Patent Application Laid-Open No. 2-105384 discloses that memory access is speeded up using additional information added to address information.

[0004]

However, in the prior art, the speed of memory access is increased by a single speed-up method. Therefore, if an access deviating from that method occurs, the speed is increased. There is a problem that the performance is further degraded as compared with the case without the above. In other words, speeding up is not versatile, but rather is based on a specific access procedure and speeding up focusing on that access method. Thus, the recovery operation of the part that has performed the preceding operation must be performed, which requires extra time.

It is therefore an object of the present invention to provide a memory access control system which can further increase the speed of memory access by switching and using the method of increasing the speed of memory access.

[0006]

According to the present invention, in a memory access control system for controlling access to a memory, information relating to data to be accessed is added to address information as additional information and output from a CPU. A high-speed operation mode of the memory is determined by referring to the additional information.

According to the present invention, in a memory access control system for controlling memory access, a CPU for adding information about an access type to address information as additional information and outputting the information, and decoding the additional information for each access type An additional information decoding unit, an access type determination unit that determines a speed-up method for each access type according to an output of the decoding unit, and a memory timing control unit that controls execution timing of the memory access using the determined speed-up method And a memory access control method characterized by including the following.

[0008] The additional information may be related to a type of data to be accessed or an access frequency.

[0009]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a memory access control method according to an embodiment of the present invention, in which a CPU 1 for adding additional information indicating an access type to address information and outputting the address information, and a memory 3 for actually storing the information. And a memory control unit 2 for controlling the memory 3 based on the address information and the additional information from the CPU 1.

FIG. 2 shows the memory control unit 2 in detail. The memory control unit 2 includes an additional information decoding unit 21 that performs decoding for determining an access type based on the additional information from the CPU 1 and an access type determination unit 22 that determines which speeding method is associated with the access type. , And a memory timing control unit 23 that generates timing for memory control based on the determined high-speed technique.

The operation of the memory access control method will be described in detail with reference to FIGS.

The CPU 1 first presents address information when accessing the memory, and at this time, simultaneously outputs information on the type of access. As the content of the information as the type of the access, some information is output so that the continuity of the access, the interval of the access, the access system, and the like can be inferred. As means for adding this information,
As shown in FIG. 1, notification may be made as additional information completely different from the address information, or information may be superimposed using part of the address information.

There are several methods for generating the additional information. A mechanism for automatically detecting information may be provided in the CPU 1, a method of explicitly specifying information at the time of generating a program, or a method of determining an attribute at the time of execution by a kernel program may be used.

The additional information thus output is input to the memory control unit 2 together with the address information. In the memory control unit 2, first, the additional information decoding unit 21 restores the information of the access type using the transmitted additional information,
The access type determination unit 22 associates the restored access type with which speeding method is used for access.

Commonly used techniques include access page operation, page write-back operation delay, line selection prefetch operation for a memory having a cache line, and the like. The memory timing control unit 23 accesses the memory 3 using the speed-up method determined here.

The description will be continued with reference to FIGS. 5 and 5 together with FIG. 3 which combines FIGS. 1 and 2.

When a user program is executed, only an area obtained by issuing a use request of a memory area to a kernel program can be used. As described above, since the kernel program knows all the memories used by the user program, it is appropriate to make the kernel program determine the access type.

If addresses can be divided into large groups and the access type can be associated with each group, there is no need to prepare a signal dedicated to additional information other than address information.

The kernel program analyzes a memory allocation request requested by the user program, and determines whether the request is for a program area, a data area, or a stack area. If it is a data area, the size of the data is divided by a certain threshold and classified into a large data area and a small data area.

The kernel program allocates a different address area to each of the divided access types. In this example, as shown in FIG. 4, 00000 program area, 04000 large data area, 08000
It is allocated to the small data area and the 10,000 stack area.

When an attempt is made to access a memory by executing a program, the memory is accessed as one of these address areas. By judging the address, it is possible to determine which access type it is.

The additional information decoding unit classifies the address information into the address areas shown in FIG.
Determine the access type.

Next, the access type judging unit 22 associates a high-speed technique which is considered to be most suitable for the access type as described below. As shown in FIG. 5, in the case of the program area, there is a high probability that the next successive address will be accessed. Therefore, the next address is read ahead, and in the case of the large data area, the cache line "0" side in the memory 3 has priority. Use For small data area, memory 3
The cache line "0" side is preferentially used, but the vicinity thereof is highly likely to be accessed continuously, so that the page hit state is maintained. In the case of the stack area, the cache line "1" side of the memory is used preferentially because it is used at a timing completely different from the data.

The memory timing control unit 23 performs memory access based on the speed-up method and the address information determined here. In other words, the memory timing control unit 2
3 controls the execution timing of the memory access using the determined speed-up method.

[0026]

According to the memory control method of the present invention, an optimum speed-up method can be adopted for each type of access, so that the memory access performance is improved. The reason is that, since the speed-up method can be switched, in the case of a single speed-up method, the performance degradation due to a misprediction hinders the performance improvement, but this hindrance is removed. .

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining a memory access control method according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the inside of a memory control unit of FIG. 1 in detail;

FIG. 3 is a block diagram collectively showing FIGS. 1 and 2;

FIG. 4 is an explanatory diagram showing the correspondence between access types and address areas.

FIG. 5 is an explanatory diagram showing a relationship between an access type and a corresponding high-speed technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Memory control part 3 Memory 21 Additional information data decoding part 22 Access type judgment part 23 Memory timing control part

Claims (4)

[Claims] In a memory access control method for controlling access to a memory, information on data to be accessed is added to address information as additional information.
A memory access control method, wherein a high-speed operation mode of the memory is determined by outputting the data from a PU and referring to the additional information in a memory control unit. 2. In a memory access control method for controlling memory access, a CPU for adding information on an access type to address information as additional information and outputting the information.
An additional information decoding unit that decodes the additional information for each access type, an access type determination unit that determines a speed-up method for each access type according to the output of the decoding unit, and the memory access using the determined speed-up method A memory timing control unit for controlling execution timing of the memory access control. 3. The memory access control method according to claim 1, wherein the additional information relates to a type of data to be accessed. 4. The memory access control method according to claim 1, wherein the additional information is related to an access frequency.