KR100564560B1 - High bandwidth memory controller using synchronous dynamic random access memory - Google Patents

Abstract

A high speed memory controller using a synchronous DRAM is disclosed. A high speed memory controller using a synchronous DRAM according to the present invention is a memory controller of a memory access system that controls a plurality of master devices to access a predetermined memory device to write or read desired data, and is applied from the master devices. The memory access address is compared with the recently accessed address to determine whether they are the same, and includes a control path for controlling data access and a predetermined buffer in response to the determined result, and responds to the result determined in the control path. A data path for outputting data stored in a buffer to a plurality of master devices, or for accessing a memory device to load new data, and according to the present invention, because the master devices accessing the SDRAM are accessed in burst length units. Can reduce Since the data of the burst length unit is buffered inside the memory controller, the data access speed can be increased even in the case of a single read other than the burst read. In addition, the data access speed can be improved by using the bank open register provided in the memory controller.

Description

High bandwidth memory controller using synchronous dynamic random access memory

1 is a schematic block diagram illustrating a memory access system, in which a memory controller according to an embodiment of the present invention is applied.

2 is a block diagram illustrating a high speed memory controller according to an exemplary embodiment of the present invention.

FIG. 3 is a detailed circuit diagram illustrating a bank hit / miss determination unit included in the control path of the apparatus illustrated in FIG. 2.

4 is a detailed block diagram illustrating a data path of the apparatus shown in FIG. 2.

The present invention relates to a memory access system, and more particularly, to a high speed memory controller using a synchronous DRAM.

Currently, the speed of the processor is faster than the speed of memory. Thus, the performance of a system that accesses memory is determined by the speed of the memory rather than by the speed of the processor. However, the use of high speed memory is very costly. Therefore, in order to solve this speed problem, the system side uses expensive multi-level fast cache memory and uses relatively low cost memory as main memory. In other words, efforts have been made to increase the performance of the system compared to the price. In addition, in terms of memory, there is a trend to provide a variety of memory that can be cheap and high bandwidth (bandwidth). Here, the various memories may be, for example, synchronous DRAM (SDRAM), Rambus DRAM (RDRAM), graphics data RAM (GDRAM), or double rate DRAM. In other words, both the system side and the memory side must be considered, so that a system having excellent cost-performance ratio can be implemented.

In addition, current system design technology tends to include a microprocessor, a memory, a memory controller, and the like on one chip, or some components thereof on a single chip. In this case, on the microprocessor side, how to implement a memory controller that processes data in memory can greatly affect system performance. Therefore, in order to design a system having a good performance ratio based on price, it is required to implement a memory controller in a more efficient manner.

An object of the present invention is to provide a high speed memory controller using a synchronous DRAM, which can speed up a memory access using a synchronous DRAM in a memory access system.

In order to achieve the above object, a high-speed memory controller using a synchronous DRAM according to the present invention is a memory controller of a memory access system that controls a plurality of master devices to access a predetermined memory device to write or read desired data And comparing a memory access address applied from master devices with a recently accessed address to determine whether they are identical to each other, and including a control path for controlling data access in response to the determined result, and a predetermined buffer therein. In response to the result determined by the output data stored in the buffer to a plurality of master devices, or a data path for loading the new data by accessing the memory device, the memory device is preferably implemented as a synchronous DRAM.

Hereinafter, a high speed memory controller using a synchronous DRAM according to the present invention will be described with reference to the accompanying drawings.

1 is a schematic block diagram illustrating a memory access system, in which a memory controller according to an embodiment of the present invention is applied. Referring to FIG. 1, a memory access system includes a central processing unit (CPU) 10, a direct memory access unit (DMA) 14, a master device such as cache memories 12, and other master devices 16. , A memory controller 18 and a synchronous DRAM (hereinafter referred to as SDRAM) 19.

In the memory access system shown in FIG. 1, the CPU 10, the cache memory 12, the DMA 14, and the other master devices 16 serve as master devices to access the SDRAM 19 through the memory controller 18. Play a role. Reference numeral 15 in FIG. 1 is a transmission line of data processed between respective master devices and the memory controller 18. In the present invention, each master device processes the data in burst length units through the memory controller 18 when the SDRAM 19 is accessed.

The memory controller 18 according to the present invention has a control path and a data path therein. Here, a buffer is provided inside the data path to buffer data transmitted by each master device from the SDRAM 29 in burst length units. Therefore, the memory controller 18 can effectively perform not only a burst read but also a single read that accesses one data by accessing the SDRAM 19 in units of burst length. Can be. The configuration and operation of the specific memory controller 18 will be described in detail with reference to FIGS. 2 to 4.

In addition, in the cache memory 12 of FIG. 1, when a cache miss occurs, the cache line is line-filled by a burst length. Therefore, the cache line size is determined in advance at the time of designing the cache memory 12. The DMA 14 places the FIFO memory by the burst length therein and processes the data in burst length units at one time.

All other master devices must also be designed to handle data in burst lengths. That is, when data is processed in burst length units, the data processing speed can be improved. However, since the CPU 10 cannot process data in units of burst length at the time of cache miss, the corresponding data among the data buffered by the burst length by using the buffers (not shown) included in the memory controller 18 is not included. Read and perform a single read.

2 is a block diagram illustrating a memory controller 18 according to an embodiment of the present invention. Referring to FIG. 2, the memory controller 18 includes a control path 20 and a data path 27.

The control path 20 compares a memory access address applied from each master device with a recently accessed address to determine whether they are identical to each other, and controls data access in response to the determined result in order to improve the data access speed. . To this end, the control path 20 includes a bank hit / miss determination unit 22 and a finite state machine (hereinafter referred to as FSM). Specifically, the bank hit / miss determination unit 22 compares the RAS address of the currently accessed memory access address with the RAS address of the recently accessed address, and compares the RAS address of the bank in which the RAS address of the memory access address is opened. Determine if it is the same. At this time, the RAS address of the recently accessed address is stored in a bank open register section (not shown) inside the bank hit / miss discriminating section 22. Therefore, when the two RAS addresses are compared and matched, it is determined to be a bank open hit (HIT), and when not matched, it is determined to be a bank open miss (MISS). In addition, the FSM 24 controls the precharge of the RAS based on the result determined by the bank hit / miss determination unit 22. That is, if it is determined that the determination result in the bank hit / miss determination section 22 is a bank open hit, the FSM 24 skips the precharge cycle of the RAS and accesses data only by the CAS address. Thus, memory access speed can be reduced compared to conventional memory access speed. That is, since a general memory access cycle is composed of RAS active, CAS active, and RAS precharge cycles, the memory access speed can be reduced to 1/3 in the present invention.

The data path 27 has a buffer 28 therein to buffer data processed in units of burst length by the master devices shown in FIG. 1, and access the buffered data to perform burst read or single read operations. Perform.

By the memory controller having such a configuration, the plurality of master devices shown in FIG. 1 load data stored in the buffer 28 when there is desired data in the buffer 28 in the data path 27. do. If the desired data does not exist in the buffer 28, the external SDRAM 19 is accessed to load the desired data.

 FIG. 3 is a detailed circuit diagram illustrating the bank hit / miss determination unit 22 of the control path 20 shown in FIG. 2. Referring to FIG. 3, the bank hit / miss determination unit 22 includes a bank open register unit 32, a multiplexer 34, and a comparator 36.

The bank open register section 32 includes a plurality of bank open registers 32a to 32n. Here, the number of registers is equal to the number of banks constituting the SDRAM 19. Each of the bank open registers 32a to 32n stores a RAS address for the recently opened bank of the n banks constituting the SDRAM 19 (see Fig. 1). Here, the RAS address for a recently opened bank indicates the last RAS address of an address recently accessed by the bank.

The multiplexer 34 inputs the output signals of the respective bank open registers 32a to 32n, and inputs the bank address 30a of the memory access address applied from the master devices as the selection signal SEL. Accordingly, the multiplexer 34 applies the output signal of the selected bank open register among the bank open registers to the second input of the comparator 36 in response to the bank address 30a.

The comparator 36 compares the RAS address 30b of the memory access address 30 with the RAS address of the corresponding bank output from the multiplexer 34, and determines a bank open hit / miss based on the comparison result. Outputs (H / M_DET). Here, the bank open hit / miss determination signal H / M_DET is a signal for determining whether or not the same RAS address is provided for a predetermined bank opened. Therefore, it is set to be a bank open hit when having the same RAS address, and set to be a bank open miss when not having the same RAS address.

Hereinafter, the operation of the bank hit / miss determination unit 22 will be described in detail with reference to FIG. 3. First, the memory access address 30 applied from one of the external master devices is composed of a bank address 30a, a RAS address 30b and a CAS address 30c. Here, the bank address 30a corresponds to an upper bit of the SDRAM access address 30, and the CAS address 30c corresponds to a lower bit. In addition, the RAS address 30b corresponds to the word address of the memory, and the CAS address 30c corresponds to the column address of the memory. At this time, the RAS addresses of the bank open registers selected through the multiplexer 34 are compared by the comparator 36 by the bank address 30a of the memory access address 30 that is externally accessed. If the RAS address of the currently accessed memory access address and the RAS address output from the multiplexer 34 are determined to match by the comparison result in the comparator 36, the hit / miss determination signal H / M_DET is It is set to a predetermined level, for example, a high level. The finite state machine (FSM) 24 of FIG. 2, which receives the hit / miss determination signal (H / M_DET) as an input, does not change the RAS address with respect to the open bank, so only the CAS signal is activated to access the memory. That is, data access can be made only to the CAS active cycle for the bank opened by the RAS address. At this time, since the RAS precharge is omitted, the access speed is increased by the time required for the RAS precharge.

If the RAS address 30b of the memory address 30 currently accessed and the RAS address output through the multiplexer 34 do not match, the hit / miss discrimination signal H / M_DET output from the comparator 36 is inconsistent. May be set to a second level, for example, a low level. Therefore, when it is determined that the bank is open missed by the bank open hit / miss determination signal H / M_DET, the RAS address of the currently accessed memory address is controlled to be updated to the corresponding bank open register.

 FIG. 4 is a detailed block diagram for explaining the data path 27 shown in FIG. Referring to FIG. 4, the buffer 28 inside the data path 27 is composed of storage blocks 28a to 28m for storing each burst length data 1 to burst length data M. As shown in FIG.

In the buffer 28 of FIG. 4, each of the storage blocks 28a to 28m corresponding to the depth is equal to the burst length m. Thus, if the burst length is four, then there are four storage blocks. In addition, the data stored in each of the storage blocks 28a to 28m in the buffer 28 of FIG. 4 are accessed by some addresses, preferably burst length addresses included in the CAS address section 30c of FIG. 3. That is, among the memory access addresses 30 shown in FIG. 4, the upper address is set to the bank address 30a of the address shown in FIG. 3, and some addresses of the RAS address 30b and the CAS address 30c. Therefore, the burst length address represents the remaining partial section of the CAS address 30c.

In the following, the operation of the data path 27 of FIG. 4 is described in detail. As described above, the memory controller 18 according to the present invention includes a buffer 27 that can always buffer data in units of burst length. Thus, each master device that accesses the SDRAM 19 (see FIG. 1) can access the data in burst length units. However, certain master devices, such as the CPU 10, do not always require burst access. Therefore, in the case where a single read rather than a burst read is required, the data path 27 determines whether the upper address of the memory access address 30 and the upper address of the data currently buffered in the buffer 28 are the same. At this time, if the same as the upper address of the buffered data, a single read is performed by accessing the data buffered in the buffer 27 using the burst length address indicating the lower address. Therefore, the data output from the buffer 28 is loaded via the data bus 15 to the master device that requested the data. That is, even if the master requests a single read, the memory controller 18 always buffers data in units of burst length. Therefore, if the single data required by the master is buffered later, the data can be accessed in one cycle. This can significantly reduce the access time because of the high probability of hitting the buffered data in terms of locality.

According to the present invention, the access time can be reduced because the master devices accessing the SDRAM are accessed in units of burst length, and the data access speed is achieved even in the case of a single read other than the burst read because the data in the burst length unit is buffered inside the memory controller. This has the effect of speeding up the process. In addition, the data access speed can be improved by using the bank open register provided in the memory controller.

Claims (3)

A memory controller in a memory access system for controlling a plurality of master devices to access a predetermined memory device to write or read desired data, A control path comparing memory access addresses applied from the master devices with recently accessed addresses to determine whether they are the same, and controlling data access in response to the determined result; And It includes a predetermined buffer therein, and outputs the data stored in the buffer to the plurality of master devices in response to the result determined in the control path, or has a data path for accessing the memory device to load new data and, And the memory device is a synchronous DRAM. The method of claim 1, wherein the control path, A bank hit / miss discrimination unit for comparing the RAS address of the memory access address with the RAS address of the recently accessed address to determine whether the RAS address of the memory access address is the same as the RAS address of the open bank; And A finite state machine for controlling RAS precharge in response to a result determined by the bank hit / miss determination unit, The bank hit / miss determination unit, A bank open register unit having N (> 1) bank open registers, each bank open register storing a last RAS address accessed in open banks among N banks constituting the memory device; A multiplexer which receives an output signal of each of the N bank open registers and selects one output signal of the bank open registers in response to a bank address of the memory access address accessed from the master devices; And Comparing the RAS address of the memory access address applied from the master device and the RAS address output from the multiplexer, and outputs a discrimination signal for determining a bank open hit / miss based on the comparison result A memory controller characterized by the above-mentioned. The method of claim 1, wherein the data path is And a buffer for buffering data corresponding to the burst length defined in the memory device.

Images