JPS5818997A - Method of producing hybrid integrated circuit substrate - Google Patents

Method of producing hybrid integrated circuit substrate

Info

Publication number
JPS5818997A
JPS5818997A JP11744081A JP11744081A JPS5818997A JP S5818997 A JPS5818997 A JP S5818997A JP 11744081 A JP11744081 A JP 11744081A JP 11744081 A JP11744081 A JP 11744081A JP S5818997 A JPS5818997 A JP S5818997A
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
layer
thermosetting resin
resin layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11744081A
Other languages
Japanese (ja)
Inventor
長島 建二
博 松本
洋 大平
田中 正高
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP11744081A priority Critical patent/JPS5818997A/en
Publication of JPS5818997A publication Critical patent/JPS5818997A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は、混成集積回路用基板の製造方法に関する。[Detailed description of the invention] The present invention relates to a method of manufacturing a substrate for a hybrid integrated circuit.

従来、混成集積回路(HrC)用基板として、セラi、
り基体上にムgPd系の導体イーストを印刷し、これを
700〜800℃の高温で焼成し、導体を形成したもの
が使用されている。また、必要に応じてRuO2系のペ
ーストで抵抗体を同じく印刷、焼成したものも使用され
ている。而して、基板上に載せる半導体素子が熱損失の
太きい・量ワー素子である場合には、どうしても熱放散
性の優れた構造忙しなければならない。この丸め、通常
第1図に示す如く、Δワー素子1、抵抗体2、導体層1
等が形成されたセラ電、り基体4の裏面に1接着樹脂層
5を介して金属放熱板6を張付は九構造が採用されてい
る。しかしながら、このような混成集積回路!では、十
分表放熱効果が得られず、しかも導体層の形成やムg−
Pd勢の貴金属を使うことやセラミック基体4と金属放
熱板6を別々に用意するためKl1品点数が多くなシ、
製造コストが高くなる問題があった。
Conventionally, as substrates for hybrid integrated circuits (HrC), Cera i,
A conductor is used by printing MugPd-based conductor yeast on a substrate and firing it at a high temperature of 700 to 800°C. Further, if necessary, resistors are also printed and fired using RuO2 paste. Therefore, if the semiconductor element to be mounted on the substrate is a power element with large heat loss, it is necessary to have a structure with excellent heat dissipation. This rounding usually consists of a Δwar element 1, a resistor 2, a conductor layer 1, as shown in FIG.
A metal heat dissipating plate 6 is attached to the back surface of the substrate 4 on which the heat dissipation plate 4 is formed, with an adhesive resin layer 5 interposed therebetween. However, such a hybrid integrated circuit! In this case, sufficient surface heat dissipation effect cannot be obtained, and furthermore, it is difficult to form a conductive layer or to
Due to the use of precious metals such as Pd and the preparation of the ceramic substrate 4 and metal heat sink 6 separately, the number of Kl1 items is large.
There was a problem of high manufacturing costs.

この問題を解消するために、第2図に示す如く、例えば
金属放熱板I上に厚さ100〜500μmのセラ電、り
層9を溶射によシ直接形成して放熱効果の向上を図った
混成集積回路用基板10が製造されている。
In order to solve this problem, as shown in Fig. 2, for example, a 100 to 500 μm thick ceramic layer 9 was directly formed on the metal heat sink I by thermal spraying to improve the heat dissipation effect. A hybrid integrated circuit substrate 10 is manufactured.

値が小さい程熱の伝導が良い。例えば、第1図の混成集
積回路用基板のセラ建ツク基体4をAj、0.で形成し
その厚さを0.63m、接着樹脂層5を工/3?シ樹脂
で形成しその厚畜を0.020箇とした場合のRthを
計算すると次の通りである。
The smaller the value, the better the heat conduction. For example, the ceramic construction base 4 of the hybrid integrated circuit board shown in FIG. 1 is Aj, 0. The thickness was 0.63 m, and the adhesive resin layer was 5/3? The Rth calculated when the resin is used and the thickness is set to 0.020 is as follows.

また、第2図に示す混成集積回路用基板のセラミック層
9を厚さ0.1■のAj、O,で形成した場合のRth
を計算すると次の通〕である。
Furthermore, Rth when the ceramic layer 9 of the hybrid integrated circuit board shown in FIG. 2 is formed of Aj, O, with a thickness of 0.1
The calculation is as follows.

つまり、第2図に示す混成集積回路用基板。That is, the hybrid integrated circuit board shown in FIG.

の熱抵抗は、第1図に示す混成集積回路用基板のものに
比べて5/100 Kなっていることが判る。
It can be seen that the thermal resistance of the substrate is 5/100 K compared to that of the hybrid integrated circuit board shown in FIG.

ココテ、hl、O,(D熱伝導率は0.26 aW/y
Mlc、x / A& シ樹脂の熱伝導率は、0.00
35W/m℃である。また、式中、Qは移動する熱量、
Kは熱伝導率、Aは熱の移動する部分の面積、ΔXは物
質の厚み、7丁は厚み社の両端での温度差である。
Kokote, hl, O, (D thermal conductivity is 0.26 aW/y
The thermal conductivity of Mlc, x/A & C resin is 0.00
It is 35W/m°C. In addition, in the formula, Q is the amount of heat transferred,
K is the thermal conductivity, A is the area of the part where heat moves, ΔX is the thickness of the material, and 7th is the temperature difference at both ends of the thickness.

このような放熱効果の為い混成集積回路用基板−L!に
導体層を形成する方法として■レジンペースOCm A
−ストを用いる方法、■Cm、Ni 等の無電解メッキ
によるもの、■Cm、Ni溶射によるものがある。■の
レジンペースのC1(−ストによるものは、空気中で比
較的低い温11j(120〜iso℃)で焼成で亀、か
つ半田付が可能で製造コストを低減できるが機械的衝撃
に弱い欠点がある。■の無電解メッキによるものは、製
造コストが高くなる。■のCm、姐溶射によるものは、
溶射で形成され九セラZ、り層には、連結空孔状の穴が
存在するため、セラζ、り層上に直!! Cmを溶射し
九としても長期間の実用試験、例えば60℃、90%−
の湿気中に放熱されると、絶縁抵抗が極端に小さくなる
。従りて、このままの状態では使用できず、完全に気密
の封止をしなければならなくなる。これでは、気密自体
が大変であるばか)か、製造スストも着しく高くなる。
Because of this heat dissipation effect, the hybrid integrated circuit board-L! As a method of forming a conductor layer on ■Resin paste OCm A
There are two methods: (1) electroless plating of Cm, Ni, etc., and (2) thermal spraying of Cm, Ni. ■Resin paste C1 (-st) can be baked in air at a relatively low temperature of 11J (120~ISO℃) and can be soldered, reducing manufacturing costs, but has the disadvantage of being weak against mechanical shock. There is a method using electroless plating (■), which increases the manufacturing cost.
Since there are holes in the form of connected pores in the 9-layer Z layer formed by thermal spraying, the 9-layer layer is formed by thermal spraying. ! Long-term practical test, for example, 60℃, 90%-
When heat is dissipated into humidity, the insulation resistance becomes extremely low. Therefore, it cannot be used in this state and must be completely hermetically sealed. This would not only make airtightness difficult, but also increase production costs.

本発明は、かかる点に鑑みてなされ九もので、放熱特性
の向上を図って信頼性の高い混成集積回路を安価な製造
コストで容易に製造することができる混成集積回路用基
板の製造方法を見出したものである。
The present invention has been made in view of the above points, and provides a method for manufacturing a substrate for a hybrid integrated circuit, which improves heat dissipation characteristics and makes it possible to easily manufacture a highly reliable hybrid integrated circuit at a low manufacturing cost. This is what I found.

以下、本発明方法について説明する。The method of the present invention will be explained below.

本発明方法は、先ず第3図(A)K示す如く、金属基板
20の表面に例えばAj、O,からなるセラン、り層2
1を100〜500μ溶射により形成する。次いで、セ
ラミ、り層21の表面領域の欠陥部分を塞ぐように熱硬
化性樹脂層22を形成する。次に1これを熱硬化性樹脂
層22の材質に適した有機溶媒例えばトリクレンからな
る写囲気中に設置し、熱硬化性樹脂層220表面領域を
所定深さまで除去する。(同図(B)参照)ここで、熱
硬化性樹脂層22を形成する熱硬化性樹脂としては、硬
化温度が低く、硬化時間が短く、かつ粘度が低くて作業
性の良いものを使用するのが望ましい、・この条件を満
すものとじては、例えば、エポキシ樹脂、アクリル樹脂
、ぼりウレタン樹脂、ジアリルフタレート樹脂、熱硬化
性fすfウレタン樹脂、シリコーン樹脂、モノマーを配
合したものがある。
In the method of the present invention, first, as shown in FIGS.
1 is formed by thermal spraying with a thickness of 100 to 500μ. Next, a thermosetting resin layer 22 is formed to fill the defective portions of the surface area of the ceramic layer 21. Next, this is placed in an atmosphere made of an organic solvent such as trichlene suitable for the material of the thermosetting resin layer 22, and the surface area of the thermosetting resin layer 220 is removed to a predetermined depth. (See figure (B)) Here, as the thermosetting resin for forming the thermosetting resin layer 22, a resin with low curing temperature, short curing time, and low viscosity and good workability is used. Examples of products that meet this condition include epoxy resins, acrylic resins, polyurethane resins, diallyl phthalate resins, thermosetting fs urethane resins, silicone resins, and monomers. .

次に、所定温度の熱処理を施して熱硬化性樹脂層22′
を硬化せしめ先後、同図(C’)K示す如く、熱硬化性
樹脂層22′の表面に所定パターンのレジスト膜23を
印刷する。
Next, heat treatment is performed at a predetermined temperature to form the thermosetting resin layer 22'.
After curing, a resist film 23 having a predetermined pattern is printed on the surface of the thermosetting resin layer 22', as shown in FIG.

次いで、同図の)K示す如く、レゾスト膜21で仕切ら
れ良熱硬化性樹脂層12′の露出表面に導体層形成部材
14を堆積し、所定の工、チンダ液で同図@に示す如く
、レジスト膜21を除去して所定パターンの導体層2j
を得る。
Next, as shown in )K in the same figure, a conductive layer forming member 14 is deposited on the exposed surface of the thermosetting resin layer 12' partitioned by the resist film 21, and is coated with a cinder solution in a predetermined manner as shown in the figure @. , the resist film 21 is removed to form a conductor layer 2j in a predetermined pattern.
get.

このようKして得られた混成集積回路用基板2gの導体
層IJ上に同図#′)#!c示す如く、/譬ワー素子s
r、抵抗体21等を形成して混成集積回路2#を得る。
#') #! cAs shown, /example power element s
r, a resistor 21, etc. are formed to obtain a hybrid integrated circuit 2#.

このようKして製造された混成集積回路2#では、混成
集積回路基板26が金属基板zo上に形成された薄肉の
セラミック層11とこのセラず、り層21の表面領域に
形成され九極薄の熱硬化性樹脂層j j’とで構成され
ているので極めて高い放熱特性を有してシシ、その結果
、高い信頼性を有する。また、熱硬化性樹脂層22′上
の導体層15は、所定の肉厚でかつ強固な接着力で容易
に形成できるので、製造工程を簡略にして製造コストを
低減させることができる。
In the hybrid integrated circuit 2# manufactured in this way, the hybrid integrated circuit board 26 is formed on the thin ceramic layer 11 formed on the metal substrate zo, and on the surface area of this ceramic layer 21. Since it is composed of a thin thermosetting resin layer jj', it has extremely high heat dissipation characteristics, and as a result, it has high reliability. Further, since the conductor layer 15 on the thermosetting resin layer 22' can be easily formed with a predetermined thickness and strong adhesive strength, the manufacturing process can be simplified and manufacturing costs can be reduced.

尚、セラミ、り層2ノは、Aj、O,の他にもマグネシ
ア、ベリリア、窒化アル建ニウム、窒化−ロン尋の少な
くとも1種類を含む部材で形成しても良い。
The ceramic layer 2 may be formed of a material containing at least one of magnesia, beryllia, aluminum nitride, and aluminum nitride in addition to Aj and O.

次に1本発明方法の実施例について説明する。Next, an example of the method of the present invention will be described.

第3図(ト)に示す如く、板厚2■の純アル之ニウムか
らなる金属基板20の表面K Al、O,の粗い粉末を
吹きつけて20〜30声の深さで粗面化し、これに1〜
2時間以内11Cfラズマ溶射によって粒径lO〜40
μのム1,0.粉末を厚さ100〜150μ堆積して竜
う電ツク層21を形成する。次に、これを60℃の熱板
上に載置してセラ?、り層21の表面に工Iキク樹脂か
らなる熱硬化性樹脂層j2を形成する6次いで、3分間
放置した後これをトリクレン蒸気中に晒し表面に残った
工4キシ樹脂を除去する。(同図側)参照)然る後、こ
れを160℃の雰囲気中で1時間放置して熱硬化性樹脂
層21を硬化せしめる。次いで、同図(e)K示す如く
、熱硬化性樹脂層210表面に120℃の雰囲気中で所
定ツタターンのレゾス)l[j Jを形成し、10分間
乾燥させる。次いで、同図@に示す如く、IIs〜40
μの粒径のC11粉末からなる導体層形成部材24を溶
射せしめてレジスト膜23で回着れた熱硬化性樹脂層2
1の表面に厚さ30〜50声堆積する。次に、同図(6
)に示す如く、トリクレン溶剤でレゾスト膜23を除去
し、所定ノ譬ターンの導体層25が形成された混成集積
回路用基板26を得九。
As shown in FIG. 3(G), the surface of a metal substrate 20 made of pure aluminum having a thickness of 2 cm is roughened by spraying coarse powder of Al, O, to a depth of 20 to 30 degrees. 1 to this
Particle size lO~40 by 11Cf plasma spraying within 2 hours
μ's 1,0. The powder is deposited to a thickness of 100 to 150 microns to form the warping electrical layer 21. Next, place this on a 60℃ hot plate and heat it. A thermosetting resin layer j2 made of polyurethane resin is formed on the surface of the layer 21.Next, after being left for 3 minutes, it is exposed to triclene vapor to remove the polyurethane resin remaining on the surface. (See side of the figure) Thereafter, this was left in an atmosphere at 160° C. for 1 hour to harden the thermosetting resin layer 21. Next, as shown in FIG. 4(e)K, a predetermined pattern of res)l[j J is formed on the surface of the thermosetting resin layer 210 in an atmosphere at 120° C. and dried for 10 minutes. Next, as shown in the same figure @, IIs~40
The thermosetting resin layer 2 is coated with a conductor layer forming member 24 made of C11 powder with a particle size of μ by thermal spraying and covered with a resist film 23.
A thickness of 30 to 50 layers is deposited on the surface of 1. Next, the same figure (6
), the resist film 23 was removed using a trichloride solvent to obtain a hybrid integrated circuit substrate 26 on which a conductor layer 25 with a predetermined number of turns was formed.

然る後、導体層250表面に牛田クリームを選択的に印
刷して/豐ワー素子21、抵抗体21等を載置し、15
0℃で1s秒間予備加熱後、230℃で15秒間半田を
溶融して同図(ト)K示す如き混成集積回路2#を得九
After that, Ushida cream is selectively printed on the surface of the conductor layer 250, and the power element 21, resistor 21, etc. are placed on the surface of the conductor layer 250, and
After preheating at 0°C for 1 second, the solder was melted at 230°C for 15 seconds to obtain a hybrid integrated circuit 2# as shown in FIG.

このよう圧して混成集積回路用基板2dを簡単な製造工
程でしかも低コストで製造し、熱伝導性、耐熱性及び信
頼性の高い混成集積同順を容易に製造することができた
By applying pressure in this way, the hybrid integrated circuit board 2d was manufactured through a simple manufacturing process and at low cost, and a hybrid integrated circuit with high thermal conductivity, heat resistance, and reliability could be easily manufactured.

以上説明した如く、本発明に係る混成集積回路用基板の
製造方法によれば、放熱特性の向上を図って信頼性の高
い混成集積回路を安価な製造コストで容易に製造する仁
とができる混成集積回路用基板を提供することができる
As explained above, according to the method for manufacturing a hybrid integrated circuit board according to the present invention, it is possible to easily manufacture a highly reliable hybrid integrated circuit at a low manufacturing cost by improving heat dissipation characteristics. A substrate for an integrated circuit can be provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来の混成集積回路の構成を示す正面図、第
2図は、従来の混成集積回路用基板の正面図、第3図(
4)乃至同図(ト)は、本発明に係る混成集積回路用基
板の製造方法を工程1[K示す説明図である。 20・・・金属基板、21・・・セラfyり層、22゜
22′・・・熱硬化性樹脂層、21・・・レジスト膜、
24・・・導電層形成部材、26・・・導電層、26・
・・混成集積回路用基板、IF・・・14ワー素子、2
8・・・抵抗体、2g−・混成集積回路。
FIG. 1 is a front view showing the configuration of a conventional hybrid integrated circuit, FIG. 2 is a front view of a conventional hybrid integrated circuit board, and FIG.
4) to (G) are explanatory diagrams showing step 1 [K] of the method for manufacturing a hybrid integrated circuit board according to the present invention. 20... Metal substrate, 21... Serafy layer, 22°22'... Thermosetting resin layer, 21... Resist film,
24... Conductive layer forming member, 26... Conductive layer, 26.
...Mixed integrated circuit board, IF...14 power elements, 2
8...Resistor, 2g--hybrid integrated circuit.

Claims (1)

【特許請求の範囲】[Claims] 金属基板の表面にセラミ、り層を形成した後、該セラミ
、り晶硬化性樹脂層を含浸し、次いで、前記熱硬化性樹
脂層の表面層を有機溶媒で除去し、次に1゛前記熱硬化
性樹脂層上に所定ノ4ターンの導体層を形成することを
特徴とする混成集積回路用基板の製造方法。
After forming a ceramic layer on the surface of a metal substrate, the ceramic layer is impregnated with a crystal hardening resin layer, and then the surface layer of the thermosetting resin layer is removed with an organic solvent, and then 1. 1. A method for manufacturing a hybrid integrated circuit board, which comprises forming a conductor layer with a predetermined number of four turns on a thermosetting resin layer.
JP11744081A 1981-07-27 1981-07-27 Method of producing hybrid integrated circuit substrate Pending JPS5818997A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11744081A JPS5818997A (en) 1981-07-27 1981-07-27 Method of producing hybrid integrated circuit substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11744081A JPS5818997A (en) 1981-07-27 1981-07-27 Method of producing hybrid integrated circuit substrate

Publications (1)

Publication Number Publication Date
JPS5818997A true JPS5818997A (en) 1983-02-03

Family

ID=14711698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11744081A Pending JPS5818997A (en) 1981-07-27 1981-07-27 Method of producing hybrid integrated circuit substrate

Country Status (1)

Country Link
JP (1) JPS5818997A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60121296A (en) * 1983-12-06 1985-06-28 Mitsubishi Alum Co Ltd Metallic strip for roll power supply surface treatment
JPS61186498A (en) * 1985-02-13 1986-08-20 Nippon Kokan Kk <Nkk> Operating method of plating in horizontal type electroplating installation

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60121296A (en) * 1983-12-06 1985-06-28 Mitsubishi Alum Co Ltd Metallic strip for roll power supply surface treatment
JPH0530918B2 (en) * 1983-12-06 1993-05-11 Mitsubishi Aluminium
JPS61186498A (en) * 1985-02-13 1986-08-20 Nippon Kokan Kk <Nkk> Operating method of plating in horizontal type electroplating installation

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