JPH03108396A - Multilayer electronic circuit board - Google Patents

Multilayer electronic circuit board

Info

Publication number
JPH03108396A
JPH03108396A JP1245952A JP24595289A JPH03108396A JP H03108396 A JPH03108396 A JP H03108396A JP 1245952 A JP1245952 A JP 1245952A JP 24595289 A JP24595289 A JP 24595289A JP H03108396 A JPH03108396 A JP H03108396A
Authority
JP
Japan
Prior art keywords
electronic circuit
circuit board
film
porous
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1245952A
Other languages
Japanese (ja)
Other versions
JP2803754B2 (en
Inventor
Kiyotaka Tsukada
輝代隆 塚田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP1201757A priority Critical patent/JP2787953B2/en
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP1245952A priority patent/JP2803754B2/en
Priority to US07/556,521 priority patent/US5144536A/en
Priority to KR1019900011819A priority patent/KR100211852B1/en
Priority to DE69008963T priority patent/DE69008963T2/en
Priority to EP90114875A priority patent/EP0411639B1/en
Publication of JPH03108396A publication Critical patent/JPH03108396A/en
Application granted granted Critical
Publication of JP2803754B2 publication Critical patent/JP2803754B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To improve resistance to high humidity, resistance to high temperature, and heat dissipative property by laminating porous electronic circuit boards and intervening inorganic or metallic porous intermediate layer between adjacent electronic circuit boards, and filling resinin interstices. CONSTITUTION:For a multi-layer electronic circuit board, electronic circuit boards 1, 1 are laminated on the upper and lower portions of a central electronic circuit board 2, and these members are integrally bonded intervening porous intermediate layers 6 therebetween. For the electronic circuit 12 board 1, a film-like conductive circuit 12 and a film-like resistor 13 are formed on te surface side of a board porous ceramic sintered structure 11 in close contact with the same, and the film-like conductive circuit 12 is likewise formed on the back side of the same. The close contact state is such that the lower surfaces of the film-like conductive circuit 12 and the film-like resistor 13 bite into uneven surface portions among many ceramic particles 10 constituting the sintered structure 11. Further, in the sinered structure 11, resin 14 impregnated after the lamination is filled in interstices formed among the ceramic particles 10. Further, the electronic circuit board 2 is likewise constructed, and the porous intermediate layer 6 is impregnated with resin.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は1表面に導電性回路等の膜状素子を形成した。[Detailed description of the invention] [Industrial application field] In the present invention, a film element such as a conductive circuit is formed on one surface.

信鯨性に優れた多層状の電子回路基板に関する。This invention relates to a multilayer electronic circuit board with excellent reliability.

〔従来技術〕[Prior art]

近年、電子回路基板としては種々のものが知られ、かつ
実用化されており1例えばガラス・エポキシ複合体、ア
ルミナ質焼結体およびムライト質焼結体等を基板材料と
する電子回路基板が提案され使用されている。そして、
高集積化を促進する1つの方法として、シリコン集積回
路などを直接基板に搭載する実装方法が検討されている
In recent years, various types of electronic circuit boards have become known and put into practical use.1 For example, electronic circuit boards using glass-epoxy composites, alumina sintered bodies, mullite sintered bodies, etc. as substrate materials have been proposed. has been used. and,
As one method for promoting higher integration, a mounting method in which silicon integrated circuits and the like are directly mounted on a substrate is being considered.

しかしながら、ガラス・エポキシ複合体はシリコン集積
回路と熱膨張率が大きく異なるため、該基板に直接搭載
することのできるシリコン集積回路は極めて小さいもの
に限られている。そればかりでなく、ガラス・エポキシ
複合体のみからなる基板は9回路形成工程において寸法
が変化し易いため、特に微細で精密な回路が要求される
基板には適用が困難である。
However, since the glass-epoxy composite has a significantly different coefficient of thermal expansion from that of silicon integrated circuits, the silicon integrated circuits that can be directly mounted on the substrate are limited to extremely small ones. In addition, the dimensions of a substrate made only of a glass-epoxy composite tend to change during the 9-circuit forming process, making it difficult to apply to substrates that require particularly fine and precise circuits.

また、アルミナ質焼結体やムライト質焼結体は硬度が高
く機械加工性に劣る。そのため9例えばスルーホール等
を設けるような機械加工が必要な場合には、生成形体の
段階で加工した後焼成する方法が行われている。しかし
、焼成時の収縮を均一に生じさせることは困難であり、
特に高い寸法精度を要求されるものや寸法の大きなもの
を製造することは困難であった。
Furthermore, alumina sintered bodies and mullite sintered bodies have high hardness and poor machinability. For this reason, if machining is required, for example to create through holes, etc., a method is used in which machining is performed at the stage of producing a formed body and then fired. However, it is difficult to cause uniform shrinkage during firing,
It has been difficult to manufacture products that require particularly high dimensional accuracy or have large dimensions.

そこで、これらの問題に対処するため、特開昭61−2
87190号あるいは特開昭64−82689号には、
多孔質セラミック焼結体の気孔に樹脂を含浸した基板が
提案されている。
Therefore, in order to deal with these problems,
No. 87190 or Japanese Patent Application Laid-Open No. 64-82689,
A substrate in which the pores of a porous ceramic sintered body are impregnated with resin has been proposed.

この基板は、セラミックの気孔率を種々変化させること
で、実装する部品1例えばシリコン集積回路等の熱膨張
に合わせたもので、低膨張で寸法安定性に優れている。
This substrate is made by varying the porosity of the ceramic to match the thermal expansion of the component 1 to be mounted, such as a silicon integrated circuit, and has low expansion and excellent dimensional stability.

また9機械加工が容易で大型化及び軽量化に対応できる
Furthermore, it is easy to machine and can be made larger and lighter.

一方、近年は、高集積化のために、1を子回路基板を複
数枚重ねて多層電子回路基板とすることが多用されてい
る。
On the other hand, in recent years, in order to achieve high integration, it has become common to stack a plurality of child circuit boards 1 to form a multilayer electronic circuit board.

また、チップ抵抗、コンデンサー等のチップ部品に代わ
り、これら素子を膜状に回路上に形成した膜状素子を有
する電子回路基板が開発されている。
Moreover, instead of chip components such as chip resistors and capacitors, electronic circuit boards having film-like elements in which these elements are formed on circuits in the form of films have been developed.

このように、膜状の導電性回路、抵抗体、コンデンサー
等の膜状素子を形成することにより、電子回路基板の小
型化、軽量化が図られる。
In this way, by forming film-like conductive circuits, resistors, capacitors, and other film-like elements, the electronic circuit board can be made smaller and lighter.

〔解決しようとする課題〕[Problem to be solved]

しかしながら、上記の多孔質セラミックー樹脂含浸基板
に膜状素子を形成した電子回路基板は。
However, the electronic circuit board in which film-like elements are formed on the porous ceramic resin-impregnated substrate described above.

使用上の信頼性に乏しい。Poor reliability in use.

即ち、上記の樹脂含浸多孔質セラミック基板では、その
表面に形成した膜状素子が樹脂上に形成されるため、樹
脂の挙動により膜状素子が著しく影響を受ける0例えば
、高湿度、高温度により。
That is, in the resin-impregnated porous ceramic substrate described above, since the film-like elements formed on the surface are formed on the resin, the film-like elements are significantly affected by the behavior of the resin. .

上記樹脂と接触している膜状素子の初期特性1例えば、
抵抗値、コンデンサー容量が大きく変動するという大き
な欠点がある。
Initial characteristics 1 of the membrane element in contact with the above resin, for example,
A major drawback is that the resistance value and capacitance of the capacitor vary greatly.

また、複数枚の電子回路基板を積層してなる多層電子回
路基板においては、各電子回路基板の電子回路から発生
する熱を効率良く外部へ放出させる必要がある。
Furthermore, in a multilayer electronic circuit board formed by laminating a plurality of electronic circuit boards, it is necessary to efficiently release heat generated from the electronic circuits of each electronic circuit board to the outside.

本発明は、かかる従来の問題点に鑑み、上記の樹脂含浸
多孔質セラミック焼結体基板の長所を生かした。耐高温
度性、耐高温度性及び放熱性に優れた。信頼性の高い多
層電子回路基板を提供しようとするものである。
In view of these conventional problems, the present invention takes advantage of the advantages of the resin-impregnated porous ceramic sintered substrate. Excellent high temperature resistance, high temperature resistance and heat dissipation. The present invention aims to provide a highly reliable multilayer electronic circuit board.

〔課題の解決手段〕[Means for solving problems]

本発明は、多孔質セラミック焼結体の表面に膜状の導電
性回路、抵抗体、コンデンサー等の膜状素子を直接形成
して電子回路基板を作製し、その後該電子回路基板を積
層すると共に該電子回路基板の間に無機質又は金属の多
孔質中間層を介在させて接着し2次いで上記多孔質セラ
ミック焼結体の気孔内に樹脂を充填してなることを特徴
とする多層電子回路基板にある。
The present invention produces an electronic circuit board by directly forming a film-like conductive circuit, a film-like element such as a resistor, a capacitor, etc. on the surface of a porous ceramic sintered body, and then laminating the electronic circuit board. A multilayer electronic circuit board, characterized in that a porous intermediate layer of inorganic or metal is interposed between the electronic circuit boards and bonded together, and then resin is filled into the pores of the porous ceramic sintered body. be.

本発明において最も注目すべきことは、多孔質セラミッ
ク焼結体の表面に直接膜状素子を形成した電子回路基板
を複数枚用い、これらを前記多孔質中間層を介在させて
積層、接着し9次いで前記焼結体の気孔内に樹脂を含浸
したことである。
The most noteworthy feature of the present invention is that a plurality of electronic circuit boards each having a membrane element formed directly on the surface of a porous ceramic sintered body are used, and these are laminated and bonded with the porous intermediate layer interposed. Next, the pores of the sintered body were impregnated with resin.

即ち1本発明の電子回路基板においては、多孔質セラミ
ック焼結体の表面の気孔及び凹凸に、導電性回路等の膜
状素子がくさび状に入り込んで直接密着している。一方
、膜状素子形成部分以外の気孔内には、電子回路基板を
積層した後に樹脂が充填される。
That is, in the electronic circuit board of the present invention, a membrane element such as a conductive circuit is inserted into the pores and irregularities of the surface of the porous ceramic sintered body in a wedge shape and directly adheres thereto. On the other hand, the pores other than the part where the membrane element is formed are filled with resin after the electronic circuit boards are laminated.

多孔質セラミック焼結体の表面に導電性回路等の膜状素
子を形成する方法としては、まずセラミックの生成形体
に膜状素子を形成する粒子を含んだペーストを、印刷な
どの方法により塗布し1次いでセラミックの生成形体を
焼結体が形成される温度で焼成する方法がある。
To form film-like elements such as conductive circuits on the surface of a porous ceramic sintered body, first, a paste containing particles that form film-like elements is applied to the ceramic formed body by a method such as printing. First, there is a method in which the ceramic green body is fired at a temperature at which a sintered body is formed.

また、他の方法としては、まず多孔質セラミック焼結体
を作成しておいた後、その表面に前記ペーストを塗布し
1次いで焼つける方法がある。
Another method is to first prepare a porous ceramic sintered body, then apply the paste on its surface and then bake it.

更に、多孔質セラミック焼結体の表面に回路となる部分
以外をマスクして、蒸着、スパッター等により導電性回
路等の膜状素子を形成し、その後前記マスクを除去する
方法がある。
Furthermore, there is a method in which a film element such as a conductive circuit is formed by vapor deposition, sputtering, etc. by masking the surface of the porous ceramic sintered body except for the part that will become the circuit, and then removing the mask.

いずれの方法においても、多孔質セラミック焼結体と膜
状素子が、直接密着していることが重要である。
In either method, it is important that the porous ceramic sintered body and the membrane element are in direct contact with each other.

上述のように多孔質セラミックと膜状素子が直接密着し
ていることで、膜状素子は温度、湿度などの環境変化に
対して極めて安定になる。
As described above, the direct contact between the porous ceramic and the membrane element makes the membrane element extremely stable against environmental changes such as temperature and humidity.

ここに膜状素子とは、前記のごとき導電性回路。The term "membrane element" here refers to a conductive circuit as described above.

膜状抵抗体、膜状コンデンサーなど、基板上に膜状に形
成する電子部品をいう、また、これらの膜状素子は、電
子回路基板の片面又は両面に形成する。
Electronic components such as film resistors and film capacitors that are formed in the form of a film on a substrate, and these film elements are formed on one or both sides of an electronic circuit board.

また、上記多孔質セラミック焼結体の材質としては、コ
ージェライト、アルミナ、窒化アルミニウム、ムライト
チタン酸マグネシウム、チタン酸アルミニウム、二酸化
ケイ素、酸化鉛、酸化亜鉛、酸化ベリリウム、酸化錫、
酸化バリウム、酸化マグネシウム、酸化カルシウムのい
ずれか少なくとも1種を主成分とするセラミックスなど
がある。この中、コージェライトは、熱膨張率がシリコ
ン集積回路のそれに近く、好ましい材料である。
Further, the materials of the porous ceramic sintered body include cordierite, alumina, aluminum nitride, mullite magnesium titanate, aluminum titanate, silicon dioxide, lead oxide, zinc oxide, beryllium oxide, tin oxide,
There are ceramics whose main component is at least one of barium oxide, magnesium oxide, and calcium oxide. Among these, cordierite is a preferred material because its coefficient of thermal expansion is close to that of silicon integrated circuits.

本発明において、前記多孔質セラミック焼結体は、平均
気孔径が0.2〜15μmであることが好ましい、この
理由は、平均気孔径が0.2よりも小さいと、前記膜状
素子と多孔質セラミック焼結体との密着力が低下するか
らである。即ち、密着力向上のための楔効果が低下する
ためである。
In the present invention, the porous ceramic sintered body preferably has an average pore diameter of 0.2 to 15 μm. This is because if the average pore diameter is smaller than 0.2, the membrane element This is because the adhesion with the quality ceramic sintered body decreases. That is, this is because the wedge effect for improving adhesion is reduced.

一方、平均気孔径が15μmよりも大きいと、多孔質セ
ラミック焼結体の表面よりかなり深く膜状素子が入り込
み、精度の高い電子回路基板の形成が困難となるからで
ある。
On the other hand, if the average pore diameter is larger than 15 μm, the membrane element will penetrate considerably deeper than the surface of the porous ceramic sintered body, making it difficult to form a highly accurate electronic circuit board.

また1本発明においては、気孔率が10%(容量比)以
上であることが好ましい、この理由は9気孔率が10%
より小さいと、前記楔効果が低下するからである。
In addition, in the present invention, it is preferable that the porosity is 10% or more (volume ratio).9 This is because the porosity is 10% or more.
This is because if it is smaller, the wedge effect will be reduced.

しかして、上記のごと(構成した電子回路基板は、その
複数枚を積層状に接合して、多層体とし。
Therefore, the electronic circuit board constructed as described above is made into a multilayer body by bonding a plurality of the electronic circuit boards in a laminated manner.

その後多孔質セラミック焼結体の多孔質部に樹脂を含浸
させて、多層電子回路基板とする(第1図参照)。
Thereafter, the porous portion of the porous ceramic sintered body is impregnated with resin to form a multilayer electronic circuit board (see FIG. 1).

上記積層体は、上記電子回路基板の間に多孔質中間層を
介在させて、接着することにより形成する。
The laminate is formed by interposing a porous intermediate layer between the electronic circuit boards and adhering them.

上記多孔質中間層としては、ガラス等の無機質又は金属
の多孔質体を用いる。かかる多孔質中間層としては、比
較的融点の低いガラス、或いはセラミック、アルミニウ
ム、金、l!、銅、タングステンなどがある。また、上
記のごとく多孔質状とするためには、粉末状の粒子を基
板面に塗布して。
As the porous intermediate layer, an inorganic or metal porous body such as glass is used. Such a porous intermediate layer may be made of glass having a relatively low melting point, ceramic, aluminum, gold, l! , copper, tungsten, etc. Furthermore, in order to make the substrate porous as described above, powder particles are applied to the substrate surface.

基板を重ね合せた後融点以下の温度で加熱焼結する手段
を用いる。
A method is used in which the substrates are laminated and then heated and sintered at a temperature below the melting point.

また、かかる多孔質中間層は、電子回路基板の生成形体
を積層して高温に焼成することにより。
Moreover, such a porous intermediate layer can be obtained by laminating formed bodies of electronic circuit boards and firing them at a high temperature.

形成することもできる。つまり、各電子回路基板はセラ
ミックでできているため、この焼成により両電子回路基
板間が焼結し合って多孔質中間層を形成し1両者を接着
するのである(第1実施例参照)。
It can also be formed. In other words, since each electronic circuit board is made of ceramic, the firing causes the two electronic circuit boards to sinter together, form a porous intermediate layer, and bond them together (see the first embodiment).

なお、上記多孔質層中間層として金属を用いる場合、該
中間層に面する基板面上に前記膜状素子がある場合には
、該膜状素子と多孔質中間層との間には電気絶縁層を設
ける。また、該多孔質中間層の気孔内にも後述のごとく
樹脂が含浸されることとなる。
Note that when metal is used as the porous intermediate layer, if the membrane element is on the substrate surface facing the intermediate layer, there is no electrical insulation between the membrane element and the porous intermediate layer. Provide layers. Furthermore, the pores of the porous intermediate layer are also impregnated with resin as described below.

上記焼結体中に含浸させる樹脂としては、エポキシ樹脂
、ポリイミド樹脂、トリアジン樹脂、ポリパラバン酸樹
脂、ポリアミドイミド樹脂、シリコン樹脂、エポキシシ
リコン樹脂、アクリル酸樹脂、メタクリル酸樹脂、アニ
リン酸樹脂、フェノール樹脂、ウレタン系樹脂、フラン
系樹脂、フッ素樹脂などがある。
The resins to be impregnated into the sintered body include epoxy resin, polyimide resin, triazine resin, polyparabanic acid resin, polyamideimide resin, silicone resin, epoxy silicone resin, acrylic acid resin, methacrylic acid resin, anilic acid resin, and phenol resin. , urethane resins, furan resins, fluororesins, etc.

また、これら樹脂を多孔質焼結体中に含浸させる方法と
しては、樹脂を加熱溶融しておき、この中に電子回路基
板の積層体を浸漬する方法がある。
Further, as a method of impregnating these resins into a porous sintered body, there is a method of heating and melting the resin and immersing a laminate of electronic circuit boards in the resin.

また、樹脂を溶媒に溶かして含浸させる方法、モノマー
状態の樹脂を含浸させた後ポリマー化する方法などがあ
る。この含浸の際には、上記樹脂は多孔質焼結体の中へ
直接に、または上記多孔質中間層内を経て多孔質焼結体
内に含浸される。その結果、多孔質中間層の気孔にも樹
脂が含浸する。
Other methods include a method of dissolving a resin in a solvent and impregnating it, and a method of impregnating a resin in a monomer state and then turning it into a polymer. During this impregnation, the resin is impregnated into the porous sintered body directly or through the porous intermediate layer. As a result, the pores of the porous intermediate layer are also impregnated with the resin.

また、積層体の接着は、実施例に示すごとく。In addition, the adhesion of the laminate was as shown in Examples.

加圧焼成、中間層の焼付は等により行なう。Pressure firing, baking of the intermediate layer, etc. are performed.

また、上記のごとくして得た多層電子回路基板の表面に
は、絶縁層を設け、その上に更に導体層を形成すること
もできる(第4図参照)。
Further, an insulating layer may be provided on the surface of the multilayer electronic circuit board obtained as described above, and a conductive layer may be further formed thereon (see FIG. 4).

上記絶縁層としては、樹脂又は樹脂と無機材料との複合
材を用いる。該樹脂としては、エポキシ樹脂、フェノー
ル樹脂、ポリイミド樹脂などを用いる。樹脂と無機材料
との複合材としては、ガラスファイバーとエポキシ樹脂
、ガラスファイバーとポリイミド樹脂などを用いる。
As the insulating layer, a resin or a composite material of a resin and an inorganic material is used. As the resin, epoxy resin, phenol resin, polyimide resin, etc. are used. As the composite material of resin and inorganic material, glass fiber and epoxy resin, glass fiber and polyimide resin, etc. are used.

上記導体層とは、電子回路用の導体をいう、該導体層の
形成法としては1例えば金属箔をラミネートする方法、
蒸着、スパッタリングなどの方法がある。
The above-mentioned conductor layer refers to a conductor for electronic circuits. Methods for forming the conductor layer include 1, for example, a method of laminating metal foil;
Methods include vapor deposition and sputtering.

なお9上記のごとく形成した多層電子回路基板に対して
は、樹脂を充填した後にスルーホールを形成し、無電解
銅メツキ等で回路間の導通を取ることができる。
Note that in the multilayer electronic circuit board formed as described above, through holes can be formed after filling with resin, and conduction between circuits can be established by electroless copper plating or the like.

〔作用及び効果〕[Action and effect]

本発明の多層電子回路基板は、各電子回路基板が、多孔
質セラミック焼結体の表面に、直接膜状素子を密着させ
ているため、膜状素子が上記焼結体の粒子の間にくさび
状に強固に結合しており。
In the multilayer electronic circuit board of the present invention, since each electronic circuit board has a membrane element in direct contact with the surface of the porous ceramic sintered body, the membrane element is wedged between the particles of the sintered body. It is strongly connected to the shape.

膜状素子が剥離することはない、また、膜状素子が形成
されていない部分は、気孔内に樹脂が充填されているの
で、耐高温度性、耐高温度性にも優れている。
The membrane element does not peel off, and since the pores of the part where the membrane element is not formed are filled with resin, it has excellent high temperature resistance and high temperature resistance.

また、樹脂を充填させることで基板全体の強度を増加さ
せ9割れにくくすると同時に機械加工を容易にし、カケ
、チッピング等の加工欠陥を防ぐことができる。また、
気体の透過を防ぎ使用環境からの影響を低減することに
効果的である。
In addition, filling the board with resin increases the strength of the entire board, making it less likely to crack, and at the same time making machining easier and preventing processing defects such as chips and chipping. Also,
It is effective in preventing gas permeation and reducing the influence from the usage environment.

また、積層されている各電子回路基板の間は前記多孔質
中間層が介在されている。そして、該多孔質中間層は、
無機質又は金属により構成されているので伝熱性が良い
、それ故、各電子回路基板で発生した熱は多孔質中間層
より外部へ効率良く放熱される。
Further, the porous intermediate layer is interposed between the stacked electronic circuit boards. And, the porous intermediate layer is
Since it is made of an inorganic or metal material, it has good heat conductivity. Therefore, the heat generated in each electronic circuit board is efficiently radiated to the outside through the porous intermediate layer.

したがって9本発明によれば、耐高温度性、耐高温度性
、放熱性及び機械加工性に優れた。信顛性の高い多層電
子回路基板を提供することができる。
Therefore, according to the present invention, it has excellent high temperature resistance, high temperature resistance, heat dissipation property, and machinability. A highly reliable multilayer electronic circuit board can be provided.

〔実施例〕〔Example〕

第1実施例 本発明の実施例にかかる多層電子回路基板につき、第1
図〜第3図を用いて説明する。
First Embodiment Regarding the multilayer electronic circuit board according to the embodiment of the present invention, the first embodiment
This will be explained using FIGS.

該多層電子回路基板は、第1図に示すごとく。The multilayer electronic circuit board is as shown in FIG.

中央の電子回路基板2の上下に電子回路基板1゜1を積
層し、これらを多孔質中間層6を介在させて一体的に接
着したものである。上記電子回路基板lは、第2図に示
すごとく、基板としての多孔質セラミック焼結体11の
表側面に、膜状導電性回路12と膜状抵抗体13を、ま
た裏側面には膜状導電性回路12を密着形成したもので
ある。
Electronic circuit boards 1°1 are laminated above and below a central electronic circuit board 2, and these are integrally bonded with a porous intermediate layer 6 interposed. As shown in FIG. 2, the electronic circuit board l has a film-like conductive circuit 12 and a film-like resistor 13 on the front side of a porous ceramic sintered body 11 as a substrate, and a film-like conductive circuit 12 and a film-like resistor 13 on the back side. A conductive circuit 12 is formed in close contact with each other.

また、上記の密着状態は、第3図に示すごとく。Further, the above-mentioned close contact state is as shown in FIG.

多孔質セラミック焼結体11を構成する多数のセラミッ
ク粒子IOの間の凹凸表面部分に、膜状導電性回路12
.膜状抵抗体13の下面がくさび状に喰い込んだ状態に
ある。また、多孔質セラミック焼結体11の内部におい
ては、セラミック粒子10の間に形成された気孔内に、
積層後において含浸された樹脂14が充填されている。
A film-like conductive circuit 12 is formed on the uneven surface portion between the large number of ceramic particles IO constituting the porous ceramic sintered body 11.
.. The lower surface of the film resistor 13 is wedge-shaped. Furthermore, inside the porous ceramic sintered body 11, in the pores formed between the ceramic particles 10,
After lamination, the impregnated resin 14 is filled.

また、上記電子回路基板2においても、電子回路基板1
と同様である。なお、多孔質中間層の気孔内にも上記樹
脂が含浸されている。
Also, in the electronic circuit board 2, the electronic circuit board 1
It is similar to Note that the resin is also impregnated into the pores of the porous intermediate layer.

上記のごと(2本例の多層電子回路基板は、電子回路基
板1.1の間に電子回路基板2を配置して、多孔質中間
層6により互いに接着したもので。
As mentioned above (the multilayer electronic circuit board of this example is one in which the electronic circuit board 2 is placed between the electronic circuit boards 1 and 1, and they are bonded to each other by the porous intermediate layer 6).

各電子回路基板1 1.2はその表裏両面に膜状素子を
有する。それ故1本例は6層回路の多層電子回路基板で
ある。上記多孔質中間層としては。
Each electronic circuit board 1 1.2 has film elements on both its front and back surfaces. One example therefore is a multilayer electronic circuit board with six layer circuits. As the above porous intermediate layer.

ガラスを用いた。Glass was used.

また、該多層電子回路基板は、積層体とした後に、その
全体を溶融樹脂中に浸漬して該樹脂を含浸させているの
で、その表面が該樹脂により被覆された状態にある。
Moreover, since the multilayer electronic circuit board is formed into a laminate, the entire board is immersed in a molten resin to be impregnated with the resin, so that its surface is coated with the resin.

第2実施例 本例は、第4図に示すごとく、8層回路の多層電子回路
基板であり、?&裏表面絶縁層を設けて。
Second Embodiment This example is a multilayer electronic circuit board with eight layer circuits as shown in FIG. & Provide an insulating layer on the back surface.

その上に導体層を形成したものである。A conductor layer is formed thereon.

即ち2本例の多層電子回路基板は、電子回路基板51,
52.53を積層接着してなり、また上下の最表面には
、絶縁層3を設け、その表面に導体層40を設けたもの
である。
That is, the two examples of multilayer electronic circuit boards include the electronic circuit board 51,
52 and 53 are laminated and bonded together, and an insulating layer 3 is provided on the upper and lower outermost surfaces, and a conductor layer 40 is provided on the surface thereof.

上記の各電子回路基板51,52.53は、膜状導電性
回路512,522,532.膜状抵抗体513,52
3,533.を、その表面に形成している。また、電子
回路基板51,52.53における膜状導電性回路、膜
状抵抗体の間、更に最表面の導体層40との間には、基
板一基板導通スルーホール55.基板内スルーホール5
7がそれぞれ設けである。
Each of the above-mentioned electronic circuit boards 51, 52.53 includes film-like conductive circuits 512, 522, 532. Film resistor 513, 52
3,533. is formed on its surface. Further, between the film-like conductive circuits and film-like resistors on the electronic circuit boards 51, 52, and 53, and further between the outermost conductor layer 40, there are board-to-substrate conductive through holes 55. Through hole 5 in the board
7 are provided respectively.

また、各電子回路基板51,52.53の間には多孔質
中間層6が介在されて、これらの間が接着されている。
Further, a porous intermediate layer 6 is interposed between each electronic circuit board 51, 52, 53, and these are bonded together.

上記多孔質中間層は、セラミック系材料で構成されてい
る。
The porous intermediate layer is made of a ceramic material.

これら膜状導電性回路12.膜状抵抗体13と。These film-like conductive circuits 12. and a film resistor 13.

基板としての多孔質セラミック焼結体との密着状態、多
孔質セラミック焼結体、多孔質中間層内の樹脂充填状態
などは、第1実施例に示した電子回路基板1と同様であ
る。
The state of close contact with the porous ceramic sintered body as a substrate, the porous ceramic sintered body, the resin filling state in the porous intermediate layer, etc. are the same as those of the electronic circuit board 1 shown in the first embodiment.

しかして、上記第1及び第2実施例にかかる多層電子回
路基板は、それを構成する各電子回路基板が前記のごと
き構成を存し、また各電子回路基板の間には伝熱性の良
い多孔質中間層が配置されている。また、多孔質セラミ
ック焼結体の気孔内には樹脂が含浸されている。それ故
、該多層電子回路基板は、耐高温度性、耐高温度性、放
熱性及び機械加工性に優れ、信銀性が高い。
Therefore, in the multilayer electronic circuit boards according to the first and second embodiments, each of the electronic circuit boards constituting the multilayer electronic circuit boards has the above-described structure, and porous holes with good heat conductivity are provided between the electronic circuit boards. There is a middle layer of quality. Furthermore, the pores of the porous ceramic sintered body are impregnated with resin. Therefore, the multilayer electronic circuit board has excellent high temperature resistance, high temperature resistance, heat dissipation property, and machinability, and has high reliability.

第3実施例 前記第2実施例に示した。8層回路の多層電子回路基板
(第4図参照)を作製し、テストを行った。
Third Embodiment As shown in the second embodiment above. A multilayer electronic circuit board (see FIG. 4) with an 8-layer circuit was manufactured and tested.

該多層電子回路基板は、まず電子回路基板Aと電子回路
基板Bとを作製しておき、電子回路基板A、Aの間に電
子回路基板Bを積層することにより作製した。
The multilayer electronic circuit board was manufactured by first preparing an electronic circuit board A and an electronic circuit board B, and then laminating the electronic circuit board B between the electronic circuit boards A and A.

即ち、電子回路基板Aを作製するため、平均粒径が1.
8μmのコージェライト粉末100重量部に対してポリ
ビニールアルコール2重量部、ポリエチレングリコール
1重量部、ステアリン酸0゜5重量部及び水100重量
部を配合し、ボールミル中で3時間混合した後、噴霧乾
燥した。
That is, in order to produce the electronic circuit board A, the average particle size is 1.
2 parts by weight of polyvinyl alcohol, 1 part by weight of polyethylene glycol, 0.5 parts by weight of stearic acid, and 100 parts by weight of water were mixed with 100 parts by weight of 8 μm cordierite powder, mixed in a ball mill for 3 hours, and then sprayed. Dry.

この乾燥物を適量採取し、金属製押し型を用いて1.O
L/cdの圧力で成形し、大きさが220mX250■
×1.2閣、密度1. 5 g/cd (6Qvo 1
%)のセラミックス生成形体を得た。
Collect an appropriate amount of this dried material and use a metal press to perform 1. O
Molded with a pressure of L/cd, size 220m x 250cm
×1.2 cabinets, density 1. 5 g/cd (6Qvo 1
%) ceramic-produced bodies were obtained.

この生成形体に穴明けをした後5300″Cで仮焼して
、有機系バインダーを除去した後、成形体表面にスパッ
タリングにより、厚み0.5μmの金パターンを配線し
た。
After making holes in this formed body, it was calcined at 5300″C to remove the organic binder, and then a gold pattern with a thickness of 0.5 μm was wired on the surface of the formed body by sputtering.

以上により、電子回路基板Aを作製した。Through the above steps, electronic circuit board A was manufactured.

次に、電子回路基板Bを作製するため、平均粒径が0.
68μmのアルミナ粉末50重量部に対して、平均粒径
が0.32μmのアルミナ粉末50重量部とポリアクリ
ル酸エステル12重量部。
Next, in order to produce electronic circuit board B, the average particle size is 0.
50 parts by weight of alumina powder having an average particle size of 0.32 μm and 12 parts by weight of polyacrylic acid ester for 50 parts by weight of alumina powder having an average particle size of 68 μm.

ポリエステル分散剤1重量部、ジブチルフタレート2重
量部及び酢酸エチル50重量部を配合し。
1 part by weight of a polyester dispersant, 2 parts by weight of dibutyl phthalate and 50 parts by weight of ethyl acetate were blended.

ボールミル中で3時間混合した後、シート成形した。After mixing in a ball mill for 3 hours, it was formed into a sheet.

この生成形体に穴明けをした後、300°Cで仮焼して
、有機系バインダーを除去した後、成形体表面にスパッ
タリングにより、厚み0.5μmの金パターンを配線し
た。
After making holes in this formed body, it was calcined at 300°C to remove the organic binder, and then a gold pattern with a thickness of 0.5 μm was wired on the surface of the formed body by sputtering.

以上により、電子回路基板Bを作製した。Through the above steps, electronic circuit board B was manufactured.

次に、前記多孔質コージェライト成形体からなる電子回
路基板A(第1,3層)と、前記多孔質アルミナ成形体
からなる電子回路基板B(第2層)を前記第4図のよう
に3層に積層した。そして、10kg/cjで加圧しな
がら、空気中で1350°Cで焼成した。これにより、
焼結体とした。
Next, as shown in FIG. Laminated in 3 layers. Then, it was fired at 1350°C in air while pressurizing at 10 kg/cj. This results in
It was made into a sintered body.

ここで、得られた焼結体基板につき、物性測定を行った
Here, the physical properties of the obtained sintered substrate were measured.

その結果、それぞれの層の平均気孔径、密度。As a result, the average pore size and density of each layer.

気孔率は、コージェライト層では3.0層m、1゜8 
g /d、  32%(vol)であり、一方アルミナ
層では0.52μm、  2. 54 g/c4. 3
5%であった。
The porosity is 3.0 layer m and 1°8 in the cordierite layer.
g/d, 32% (vol), while for the alumina layer, 0.52 μm, 2. 54 g/c4. 3
It was 5%.

また、前記コージェライト層とアルミナ層との間には、
Alt Os  S i Ox  MgO系の中間層が
0.5μm形成されていた。この多孔質中間層の平均気
孔径、気孔率は1.5μm、42%の多孔質層であった
。また、眉間の密着性は1. 8kg/mum”で良好
な密着性を有していた。
Moreover, between the cordierite layer and the alumina layer,
A 0.5 μm thick AltOsSiOxMgO-based intermediate layer was formed. The average pore diameter and porosity of this porous intermediate layer were 1.5 μm, and the porous layer was 42%. Also, the adhesion between the eyebrows is 1. It had good adhesion at 8 kg/mum''.

次いで、この積層体の表裏面に、平均粒径16μmの酸
化ルテニウム粒子を38%含んだ、粘度170Pa−s
のペーストを325メツシユのスクリーンで印刷を行い
、前記導体上に薄膜の抵抗体を形成した。乾燥した後、
空気中、850°Cで焼付た。この時の抵抗値は59Ω
/口であった。
Next, on the front and back surfaces of this laminate, a material with a viscosity of 170 Pa-s containing 38% of ruthenium oxide particles with an average particle size of 16 μm was applied.
The paste was printed using a 325 mesh screen to form a thin film resistor on the conductor. After drying,
Baked at 850°C in air. The resistance value at this time is 59Ω
/It was a mouth.

この段階で、この基板を85°C・85%RH(相対湿
度)で1000時間、高温、高温寿命試験を行ったとこ
ろ、抵抗値の変化率は、0.12%であり、優れた安定
性を有していた。
At this stage, this board was subjected to a high temperature and high temperature life test for 1000 hours at 85°C and 85% RH (relative humidity), and the rate of change in resistance was 0.12%, indicating excellent stability. It had

次に、該積層体に二液性のエポキシ樹脂を含浸。Next, the laminate is impregnated with a two-component epoxy resin.

硬化させて、多層電子回路基板を得た。この含浸は、基
板を真空下におき、脱泡したエポキシ樹脂を真空下で含
浸し1次いで熱硬化させることにより行った。
After curing, a multilayer electronic circuit board was obtained. This impregnation was carried out by placing the substrate under vacuum, impregnating the defoamed epoxy resin under vacuum, and then thermally curing it.

次いで、この樹脂含浸した積層体の表裏に、絶縁層とし
ての0.05閣のBTレジン系プリプレグと、更にその
上に18μmの銅箔を配置し真空プレスを行って2表裏
面にそれぞれ導体層を形成した。
Next, on the front and back sides of this resin-impregnated laminate, 0.05 μm thick BT resin prepreg is placed as an insulating layer, and 18 μm copper foil is further placed on top of that, and conductor layers are formed on each of the two front and back sides by vacuum pressing. was formed.

次いで、該積層体に、φ0.40閣のダイヤモンドドリ
ルで表裏及び中間層まで穴明けし、15μmの無電解銅
メツキを施して導通をとった後。
Next, holes were drilled in the laminate using a diamond drill with a diameter of 0.40 mm to the front, back, and intermediate layers, and 15 μm electroless copper plating was applied to ensure continuity.

表裏面の導体層をエツチングして回路形成を行った。A circuit was formed by etching the conductor layers on the front and back surfaces.

このようして得られた多層電子回路基板は8層回路であ
り、総厚みは0.86g*で極めて薄いものであった。
The thus obtained multilayer electronic circuit board was an 8-layer circuit, and had a total thickness of 0.86 g*, which was extremely thin.

しかも、この多層電子回路基板は。Moreover, this multilayer electronic circuit board.

14当たり膜状の抵抗体が26個、コンデンサー素子が
14個内蔵された極めて実装密度の高いものであった。
It had an extremely high packaging density, with 26 film-like resistors and 14 capacitor elements built-in per 14.

この多層電子回路基板につき、20℃で30秒。30 seconds at 20°C for this multilayer electronic circuit board.

260℃で30秒のオイルデイツプ繰り返し耐熱試験を
実施した。その結果、500サイクルでも断線、基板間
剥離などの不良は何ら発生しなかった。
A heat resistance test was conducted by repeatedly dipping in oil for 30 seconds at 260°C. As a result, no defects such as wire breakage or separation between substrates occurred even after 500 cycles.

また、この多層電子回路基板を85°C・85%RHで
1ooo時間、高温、高温寿命試験を行ったところ、抵
抗値の変化率は、0.18%で極めて安定であった。
Further, when this multilayer electronic circuit board was subjected to a high temperature and high temperature life test for 100 hours at 85° C. and 85% RH, the rate of change in resistance value was extremely stable at 0.18%.

また、該多層電子回路基板について、真空下におけるレ
ーザーフラッシュ試験により、熱伝導率を測定した。そ
の結果、3.6W/m−にと放熱性が高かった。なお、
多孔質中間層を設けることなく、有機系接着フィルムで
接着したものは、0゜9W/m−にであった。
Further, the thermal conductivity of the multilayer electronic circuit board was measured by a laser flash test under vacuum. As a result, the heat dissipation was as high as 3.6 W/m-. In addition,
When the porous intermediate layer was not provided and the adhesive film was bonded with an organic adhesive film, the strength was 0°9 W/m-.

なお、上記電子回路基@A、Bは、前記第2図。Note that the electronic circuit boards @A and B are shown in FIG. 2 above.

第3図に示すごとく、多孔質セラミック焼結体11の表
裏両面に膜状の導電性回路12と、膜状抵抗体13とを
強固に密着形成したものである(詳細は第1実施例参照
)。
As shown in FIG. 3, a film-like conductive circuit 12 and a film-like resistor 13 are firmly adhered to both the front and back surfaces of a porous ceramic sintered body 11 (see the first embodiment for details). ).

一方、比較のために、同様にして、多孔質コージェライ
ト焼結体を製作した後、すぐに同様の二液性のエポキシ
樹脂を含浸し、同時に銅箔を積層して基板を得た0次い
で、エツチングにより回路形成を行った。この時のビー
ル強度は1.8kg/lで、低かった。
On the other hand, for comparison, after producing a porous cordierite sintered body in the same manner, it was immediately impregnated with the same two-component epoxy resin, and at the same time a copper foil was laminated to obtain a substrate. A circuit was formed by etching. The beer strength at this time was 1.8 kg/l, which was low.

また、前記の多層電子回路基板においては、それぞれ長
さ350mm、輻250■の基板に、12万六以上の穴
明を行うことができた。このように。
In addition, in the multilayer electronic circuit boards described above, it was possible to drill more than 120,006 holes in each board with a length of 350 mm and a radius of 250 mm. in this way.

本発明の電子回路基板は強度が高く1機械加工性に優れ
ている。
The electronic circuit board of the present invention has high strength and excellent machinability.

第4実施例 第3実施例と同様のコージェライト成形体(基板A)と
アルミナ成形体(基板B)を用いて、その表面に導体回
路形成のためタングステン粉末からなるペーストをスク
リーン印刷で形成した。つまり、第3実施例における金
パターンに変えてタングステンパターンを形成した。そ
の他は、第3実施例と同様である。
Fourth Example Using the same cordierite molded body (substrate A) and alumina molded body (substrate B) as in the third example, a paste made of tungsten powder was formed on the surface by screen printing to form a conductor circuit. . That is, a tungsten pattern was formed instead of the gold pattern in the third example. The rest is the same as the third embodiment.

その結果、第4図において、スルホール内のタングステ
ン粒子は未焼結ながら導通しており接続信顧性、抵抗安
定性等が良好であった。
As a result, in FIG. 4, the tungsten particles in the through holes were electrically conductive even though they were not sintered, and the connection reliability, resistance stability, etc. were good.

第5実施例 第3実施例と同様のセラミック成形体を使用し。Fifth example The same ceramic molded body as in the third example was used.

多層電子回路基板を作製した。A multilayer electronic circuit board was fabricated.

即ち、第3実施例で示したコージェライト成形体を、空
気中、1400°Cで焼成して多孔質コージェライト焼
結体を形成した。この焼結体は、厚みが0.25mで、
密度が1.8g/ej、気孔率が30%、平均気孔径が
3.2μmの焼結体であった。
That is, the cordierite molded body shown in the third example was fired at 1400° C. in air to form a porous cordierite sintered body. This sintered body has a thickness of 0.25 m,
The sintered body had a density of 1.8 g/ej, a porosity of 30%, and an average pore diameter of 3.2 μm.

次に、上記多孔質コージェライト焼結体の表面に、平均
粒径IIμmの銀−パラジウム粒子を48%含んだ粘度
80Pa−sのペーストを、325メツシユのスクリー
ンで印刷を行い、導体回路を形成した0次いで、平均粒
径16μmの酸化ルテニウム粒子を38%含んだ粘度1
70Pa−sのペーストを、325メツシユのスクリー
ンで印刷を行い、前記導体上に膜状の抵抗体を形成した
Next, a paste with a viscosity of 80 Pa-s containing 48% silver-palladium particles with an average particle diameter of II μm was printed on the surface of the porous cordierite sintered body using a 325 mesh screen to form a conductor circuit. Then, viscosity 1 containing 38% ruthenium oxide particles with an average particle size of 16 μm
A 70 Pa-s paste was printed using a 325 mesh screen to form a film-like resistor on the conductor.

一方、第3実施例と同様のアルミナ成形体を。On the other hand, an alumina molded body similar to the third example.

大気中、1550°Cで1時間焼成して、多孔質アルミ
ナ焼結体とした。該焼結体は、厚み0.25閣、密度2
.gg/c+1.気孔率25%、平均気孔径0.29μ
mであった。
It was fired in the air at 1550°C for 1 hour to obtain a porous alumina sintered body. The sintered body has a thickness of 0.25 mm and a density of 2
.. gg/c+1. Porosity 25%, average pore diameter 0.29μ
It was m.

この多孔質アルミナ焼結体の表面に、前記多孔質コージ
ェライト焼結体の表面に印刷したと同様の銀−パラジウ
ム粒子を塗布し2回路を形成した。
Silver-palladium particles similar to those printed on the surface of the porous cordierite sintered body were applied to the surface of this porous alumina sintered body to form two circuits.

次いで、平均粒径16μmの酸化ルテニウム粒子を38
%含んだ粘度170Pa−sのペーストを。
Next, 38 ruthenium oxide particles with an average particle size of 16 μm were
% and a viscosity of 170 Pa-s.

325メツシユのスクリーンで印刷し、前記導体上に膜
状の抵抗体を形成した。
A film-like resistor was formed on the conductor by printing with a 325 mesh screen.

次に、前記第1図のように、第1.3層を多孔質コージ
ェライト焼結体、第2層を多孔質アルミナ焼結体として
積層した。このとき、多孔質中間層形成のために、各層
間に平均粒径13μmのA1、O,−3in、−TiO
オ系セラミック粉末を約100μm塗布し、張り合わせ
た。その後。
Next, as shown in FIG. 1, the first and third layers were made of a porous cordierite sintered body, and the second layer was made of a porous alumina sintered body. At this time, in order to form a porous intermediate layer, A1, O, -3in, -TiO with an average particle size of 13 μm was inserted between each layer.
Approximately 100 μm of ceramic powder was applied and the pieces were bonded together. after that.

これらを空気中で850℃で焼き付けた。These were baked at 850°C in air.

この時点での代表的抵抗値は、350Ω/口であった。The typical resistance value at this point was 350Ω/mouth.

また、中間層の平均気孔径、気孔率は5゜5μm、33
%の多孔質層であった。また9層間の密着性は4. 5
kg/sm”で良好な密着性を有していた。
In addition, the average pore diameter and porosity of the intermediate layer are 5°5 μm, 33
% porous layer. Also, the adhesion between the 9 layers is 4. 5
kg/sm" and had good adhesion.

次に、第3実施例と同様にして、二液性のエポキシ樹脂
を含浸し、硬化して多層電子回路基板を得た。
Next, in the same manner as in the third example, a two-component epoxy resin was impregnated and cured to obtain a multilayer electronic circuit board.

こうして得られた多層電子回路基板は、6層であり、総
厚は0.93mmで極めて薄いものであった。しかも、
  1cii当たり、膜状の抵抗体が56個。
The thus obtained multilayer electronic circuit board had six layers and had a total thickness of 0.93 mm, which was extremely thin. Moreover,
There are 56 film-like resistors per 1 cii.

コンデンサー素子が11個内蔵された極めて実装密度の
高いものであった。
It had an extremely high packaging density with 11 built-in capacitor elements.

この基板について、20°Cで30秒、260℃で30
秒のオイルデイツプ繰り返し耐熱試験を実施した。その
結果、500サイクルでも断線、基板間剥離などの不良
は何ら発生しなかった。
For this board, 30 seconds at 20°C and 30 seconds at 260°C.
A heat resistance test was conducted with repeated oil dips for seconds. As a result, no defects such as wire breakage or separation between substrates occurred even after 500 cycles.

また、この多層電子回路基板を85°C・85%RHで
1000時間、高温、高温寿命試験を行ったところ、抵
抗値の変化率は、0.25%で極めて安定であった。
Further, when this multilayer electronic circuit board was subjected to a high temperature and high temperature life test for 1000 hours at 85° C. and 85% RH, the rate of change in resistance value was extremely stable at 0.25%.

また、放熱性に関しては、2.9W/m−にであった。Moreover, regarding heat dissipation, it was 2.9 W/m-.

第6実施例 第5実施例と同様に2回路と膜状抵抗素子とが形成され
た多孔質コージェライト焼結体を、空気中で850°C
で焼き付けた。
Sixth Example Similar to the fifth example, a porous cordierite sintered body on which two circuits and a film resistance element were formed was heated to 850°C in air.
It was baked in.

得られた回路の密着強度は3kgであり、この時点での
代表的抵抗値は、300Ω/口であった。
The adhesion strength of the obtained circuit was 3 kg, and the typical resistance value at this point was 300 Ω/port.

一方、第5実施例と同様に多孔質アルミナ焼結体を形成
し、この表面に平均粒径18μmのランタンポライド−
酸化錫粒子を41%含んだ粘度110Pa−sのペース
トを、250メツシユのスクリーンで印刷した。そして
、乾燥した後、窒素中で900°Cで焼き付け、膜状の
抵抗体を形成した。
On the other hand, a porous alumina sintered body was formed in the same manner as in the fifth example, and lanthanum poride with an average particle size of 18 μm was coated on the surface of the porous alumina sintered body.
A paste containing 41% tin oxide particles and a viscosity of 110 Pa-s was printed with a 250 mesh screen. After drying, it was baked at 900°C in nitrogen to form a film-like resistor.

次いで、この抵抗体の上に、平均粒径8μmの銅粒子を
50%含んだ粘度120Pa−sのペーストを、250
メツシユのスクリーンで印刷を行い、導体回路を形成し
た。
Next, a paste with a viscosity of 120 Pa-s containing 50% copper particles with an average particle size of 8 μm was applied onto this resistor at 250 Pa-s.
Printing was performed using a mesh screen to form a conductor circuit.

更に、前記多孔質コージェライト焼結体を第2層に、多
孔質アルミナ焼結体を第1.第3層として積層した。こ
のとき、多孔質中間層形成のため。
Further, the porous cordierite sintered body is used as a second layer, and the porous alumina sintered body is used as a first layer. Laminated as the third layer. At this time, due to the formation of a porous intermediate layer.

各層間に平均粒径18μmのBzOs  SiO□−Z
nO系ガラス粉末を、約5011ml布し、その後窒素
中で600°Cで焼付けた。
BzOs SiO□-Z with an average grain size of 18 μm between each layer
Approximately 5011 ml of nO-based glass powder was applied to the cloth, and then baked at 600°C in nitrogen.

こうして得られた中間層の平均気孔系、気孔率は7.1
μm、21%の多孔層であった。また。
The average pore system and porosity of the intermediate layer thus obtained was 7.1.
It was a porous layer of 21% in μm. Also.

眉間の密着性は6. 9kg/ma”で良好な密着性を
有していた。
The tightness between the eyebrows is 6. It had good adhesion at 9 kg/ma''.

次に、第3実施例と同様に、二液性のエポキシ樹脂を含
浸し、硬化して多層電子回路基板を得た。
Next, as in the third example, a two-component epoxy resin was impregnated and cured to obtain a multilayer electronic circuit board.

該多層電子回路基板は6層回路であっり、総厚は0.8
3mmで橿めて薄いものであった。しかも。
The multilayer electronic circuit board is a 6-layer circuit, and the total thickness is 0.8
It was thin at 3 mm. Moreover.

11当たり膜状の抵抗体が61個、コンデンサー素子が
26個内蔵された極めて実装密度の高いものであった。
It had extremely high packaging density, with 61 film-like resistors and 26 capacitor elements built-in per No. 11.

この基板について、20℃で30秒、260°Cで30
秒のオイルデイツプ繰り返し耐熱試験を実施したところ
500サイクルでも断線、基板間剥離などの不良は何ら
発生しなかった。
For this board, 30 seconds at 20°C and 30 seconds at 260°C.
When a heat resistance test was conducted with repeated oil dips for 500 seconds, no defects such as wire breakage or separation between substrates occurred even after 500 cycles.

また、この多層電子回路基板を85°C・85%RHで
1ooo時間、高温、高温寿命試験を行った。その結果
、抵抗値の変化率は、酸化ルテニウム系で0.41%、
ランタンポライド−酸化スズ系で1.18%で極めて安
定であった。また、放熱性は2.3W/m・kであった
Further, this multilayer electronic circuit board was subjected to a high-temperature life test at 85° C. and 85% RH for 100 hours. As a result, the rate of change in resistance value was 0.41% for the ruthenium oxide system.
The lanthanumolide-tin oxide system was extremely stable at 1.18%. Moreover, the heat dissipation property was 2.3 W/m·k.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第3図は第1実施例の多層電子回路基板を示し
、第1図はその断面図、第2図は1つの電子回路基板の
断面図、第3図は要部拡大断面図。 第4図は第2実施例の多層電子回路基板の断面図である
。 1、2゜ l Oo。 11、。 l 2.。 13、。 14、。 3、。 40、。 6、。 51、 52. 53 電子回路基板。 セラミック粒子。 多孔質セラミック焼結体。 膜状導電性回路。 膜状抵抗体素子。 樹脂。 絶縁層。 導体層。 多孔質中間層。
1 to 3 show the multilayer electronic circuit board of the first embodiment, FIG. 1 is a sectional view thereof, FIG. 2 is a sectional view of one electronic circuit board, and FIG. 3 is an enlarged sectional view of main parts. . FIG. 4 is a sectional view of the multilayer electronic circuit board of the second embodiment. 1, 2゜l Oo. 11. l 2. . 13. 14. 3. 40. 6. 51, 52. 53 Electronic circuit board. ceramic particles. Porous ceramic sintered body. Membrane conductive circuit. Film resistor element. resin. insulation layer. conductor layer. Porous intermediate layer.

Claims (2)

【特許請求の範囲】[Claims] (1)多孔質セラミック焼結体の表面に膜状の導電性回
路、抵抗体、コンデンサー等の膜状素子を直接形成して
電子回路基板を作製し、その後該電子回路基板を積層す
ると共に該電子回路基板の間に無機質又は金属の多孔質
中間層を介在させて接着し、次いで上記多孔質セラミッ
ク焼結体の気孔内に樹脂を充填してなることを特徴とす
る多層電子回路基板。
(1) An electronic circuit board is produced by directly forming a film-like conductive circuit, a film-like element such as a resistor, a capacitor, etc. on the surface of a porous ceramic sintered body, and then the electronic circuit board is laminated and 1. A multilayer electronic circuit board, characterized in that the electronic circuit boards are bonded together with a porous intermediate layer of inorganic or metal interposed between them, and then the pores of the porous ceramic sintered body are filled with resin.
(2)第1請求項において、多層電子回路基板は、その
表面に樹脂又は樹脂と無機材料の複合材とからなる絶縁
層を介して、導体層を形成していることを特徴とする多
層電子回路基板。
(2) In the first claim, the multilayer electronic circuit board is characterized in that a conductor layer is formed on the surface of the multilayer electronic circuit board through an insulating layer made of resin or a composite material of resin and inorganic material. circuit board.
JP1245952A 1989-08-03 1989-09-21 Multilayer electronic circuit board Expired - Lifetime JP2803754B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP1201757A JP2787953B2 (en) 1989-08-03 1989-08-03 Electronic circuit board
JP1245952A JP2803754B2 (en) 1989-09-21 1989-09-21 Multilayer electronic circuit board
US07/556,521 US5144536A (en) 1989-08-03 1990-07-24 Electronic circuit substrate
KR1019900011819A KR100211852B1 (en) 1989-08-03 1990-08-01 Electronic circuit board and fabricating method thereof
DE69008963T DE69008963T2 (en) 1989-08-03 1990-08-02 Electronic circuit substrate.
EP90114875A EP0411639B1 (en) 1989-08-03 1990-08-02 Electronic circuit substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1245952A JP2803754B2 (en) 1989-09-21 1989-09-21 Multilayer electronic circuit board

Publications (2)

Publication Number Publication Date
JPH03108396A true JPH03108396A (en) 1991-05-08
JP2803754B2 JP2803754B2 (en) 1998-09-24

Family

ID=17141295

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1245952A Expired - Lifetime JP2803754B2 (en) 1989-08-03 1989-09-21 Multilayer electronic circuit board

Country Status (1)

Country Link
JP (1) JP2803754B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001223298A (en) * 1999-12-01 2001-08-17 Ibiden Co Ltd Package substrate
JP2005340375A (en) * 2004-05-25 2005-12-08 Murata Mfg Co Ltd Ceramic electronic component and manufacturing method thereof
US7172806B2 (en) 2003-07-14 2007-02-06 Murata Manufacturing Co. Monolithic ceramic electronic component
WO2022014358A1 (en) * 2020-07-13 2022-01-20 不二製油グループ本社株式会社 Method for producing textured protein material and textured protein material

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001223298A (en) * 1999-12-01 2001-08-17 Ibiden Co Ltd Package substrate
US7172806B2 (en) 2003-07-14 2007-02-06 Murata Manufacturing Co. Monolithic ceramic electronic component
JP2005340375A (en) * 2004-05-25 2005-12-08 Murata Mfg Co Ltd Ceramic electronic component and manufacturing method thereof
WO2022014358A1 (en) * 2020-07-13 2022-01-20 不二製油グループ本社株式会社 Method for producing textured protein material and textured protein material

Also Published As

Publication number Publication date
JP2803754B2 (en) 1998-09-24

Similar Documents

Publication Publication Date Title
US5144536A (en) Electronic circuit substrate
US7198996B2 (en) Component built-in module and method for producing the same
US6753483B2 (en) Printed circuit board and method of manufacturing the same
US6245171B1 (en) Multi-thickness, multi-layer green sheet lamination and method thereof
JPS62126694A (en) Multilayer electronic circuit substrate
WO2018163982A1 (en) Multilayered substrate
JP2006210536A (en) Method of manufacturing electronic component and wiring board therewith
JPH03108396A (en) Multilayer electronic circuit board
JP2002111219A (en) Wiring board incorporating electric element and its manufacturing method
JP2955442B2 (en) Manufacturing method of ceramic circuit board
JP2803755B2 (en) Multilayer electronic circuit board
JP2803752B2 (en) Multilayer electronic circuit board
JP2803751B2 (en) Multilayer electronic circuit board
JP2003273515A (en) Method for reducing contraction between low temperature sintering layers of ceramic
JP2001160681A (en) Multilayer ceramic board and its manufacturing method
JP2753744B2 (en) Manufacturing method of electronic circuit board
JP2753743B2 (en) Manufacturing method of electronic circuit board
JP2753741B2 (en) Manufacturing method of electronic circuit board
JP3659441B2 (en) Wiring board
JP2004095753A (en) Method for manufacturing multi-layer ceramic substrate
JP2515165B2 (en) Method for manufacturing multilayer wiring board
JPH114080A (en) Multilayered wiring board
JP3872339B2 (en) Multilayer wiring board
JP2003007367A (en) Resin sheet for mounting face of composite ceramic member, composite ceramic member and its manufacturing method
JP2006179741A (en) Electronic component and its manufacturing method, and wiring board therewith

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080717

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080717

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090717

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100717

Year of fee payment: 12

EXPY Cancellation because of completion of term
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100717

Year of fee payment: 12