JP2002111219A - Wiring board incorporating electric element and its manufacturing method - Google Patents
Wiring board incorporating electric element and its manufacturing methodInfo
- Publication number
- JP2002111219A JP2002111219A JP2000294746A JP2000294746A JP2002111219A JP 2002111219 A JP2002111219 A JP 2002111219A JP 2000294746 A JP2000294746 A JP 2000294746A JP 2000294746 A JP2000294746 A JP 2000294746A JP 2002111219 A JP2002111219 A JP 2002111219A
- Authority
- JP
- Japan
- Prior art keywords
- electric element
- wiring board
- built
- insulating
- main body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
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- Ceramic Capacitors (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、絶縁基板の内部に
コンデンサなどの電気素子を内蔵することにより、ＬＳ
Ｉチップなどの能動素子を表面に実装可能であり、配線
基板の機能性を高め、小型、高密度化できる電気素子内
蔵型配線基板とその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LS (Integrated Circuit) having a built-in electric element such as a capacitor inside an insulating substrate.
The present invention relates to a wiring board with a built-in electric element, on which an active element such as an I-chip can be mounted on the surface, the functionality of the wiring board can be enhanced, and the size and density can be increased.
【０００２】[0002]
【従来技術】近年、携帯電話を始めとする携帯情報端末
の発達やコンピューターを持ち運んで操作するいわゆる
モバイルコンピューティングの普及によって、電子機器
の小型化がますます進んでおり、回路部品の高密度、高
機能化に対応した配線基板が要求されている。このよう
な配線基板としては、例えば、特開平１１−２２０２６
２号公報に開示されているようなものが知られている。2. Description of the Related Art In recent years, with the development of portable information terminals such as cellular phones and the spread of so-called mobile computing that carries and operates a computer, the miniaturization of electronic devices has been further advanced, and the high density of circuit components, There is a demand for a wiring board that supports high functionality. As such a wiring board, for example, Japanese Patent Application Laid-Open No. H11-22026
The one disclosed in Japanese Patent Publication No. 2 is known.
【０００３】この公報に開示された配線基板では、無機
フィラーと未硬化の熱硬化性樹脂とを含む混合物からな
る絶縁シートの内部にビアホール導体を、また、該絶縁
シートの主面に配線回路層を形成し、さらに、該配線シ
ート上に電気素子を実装して形成した配線シートを複数
積層した後、硬化することによって電気素子内蔵型配線
基板を作製することができる。In the wiring board disclosed in this publication, a via hole conductor is provided inside an insulating sheet made of a mixture containing an inorganic filler and an uncured thermosetting resin, and a wiring circuit layer is provided on a main surface of the insulating sheet. Is formed, and a plurality of wiring sheets formed by mounting electric elements on the wiring sheet are laminated, and then cured, whereby a wiring board with a built-in electric element can be manufactured.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上記特
開平１１−２２０２６２号公報では、半導体素子やチッ
プ状の電気素子を配線基板に内蔵する場合、配線回路層
やビアホール導体を形成した単層の配線シートに、はん
だや導電性接着剤を用いて実装するため、未硬化の絶縁
シートを高温で加熱する必要があり、熱による絶縁シー
トの収縮や変形が生じるという問題があった。However, in Japanese Patent Application Laid-Open No. H11-220262, when a semiconductor element or a chip-like electric element is incorporated in a wiring board, a single-layer wiring having a wiring circuit layer and a via-hole conductor is formed. Since the uncured insulating sheet needs to be heated at a high temperature because it is mounted on the sheet using solder or a conductive adhesive, there is a problem that the insulating sheet contracts or deforms due to heat.
【０００５】一方、前記絶縁シートの収縮や変形が発生
しないような低い温度において、前記電気素子を前記配
線シートに実装した場合、その後のホットプレスによる
積層硬化において、前記電気素子がビアホール導体や配
線パターンの接続箇所からずれ、内蔵した電気素子と配
線基板の配線回路層との導通が得られなくなり、インダ
クタンスが大きくなるという問題があった。On the other hand, when the electric element is mounted on the wiring sheet at such a low temperature that does not cause shrinkage or deformation of the insulating sheet, the electric element may become a via-hole conductor or a wiring in the subsequent lamination hardening by hot pressing. There has been a problem in that the pattern is displaced from the connection position of the pattern, conduction between the built-in electric element and the wiring circuit layer of the wiring board cannot be obtained, and the inductance increases.
【０００６】従って、本発明は、絶縁基板の内部にコン
デンサなどの電気素子を内蔵して成る配線基板におい
て、ずれに基づくインダクタンスの増大を防止し、内蔵
された電気素子と配線基板に設けられた配線回路層との
接続信頼性に優れた電気素子内蔵型配線基板と、それを
製造する方法を提供することを目的とするものである。Accordingly, the present invention prevents an increase in inductance due to displacement in a wiring board having a built-in electric element such as a capacitor inside an insulating substrate, and is provided on the built-in electric element and the wiring board. An object of the present invention is to provide a wiring board with a built-in electric element having excellent connection reliability with a wiring circuit layer, and a method for manufacturing the same.
【０００７】[0007]
【課題を解決するための手段】本発明の電気素子内蔵型
配線基板は、少なくとも熱硬化性樹脂を含有する絶縁基
板と、該絶縁基板の表面および／または内部に形成され
た配線回路層と、前記絶縁基板内部に形成され、金属粉
末が充填されてなるビアホール導体とを具備する配線基
板内に、電気素子を内蔵した電気素子内蔵型配線基板に
おいて、前記電気素子が、電気素子本体と、該電気素子
本体の一部に設けられ、前記ビアホール導体と直接的に
接続される外部電極を具備するとともに、前記電気素子
本体の表面粗さ（Ｒａ）が０．５μｍ以上であることを
特徴とするものである。According to the present invention, there is provided a wiring board with a built-in electric element, comprising: an insulating substrate containing at least a thermosetting resin; a wiring circuit layer formed on the surface and / or inside the insulating substrate; An electric element built-in type wiring board in which an electric element is embedded in a wiring board formed inside the insulating substrate and having a via hole conductor filled with metal powder, wherein the electric element is an electric element main body, and An external electrode is provided on a part of the electric element main body and is directly connected to the via hole conductor, and a surface roughness (Ra) of the electric element main body is 0.5 μm or more. Things.
【０００８】このような構成によれば、配線基板内に内
蔵される前記電気素子が、ホットプレス等による積層硬
化において、ビアホール導体や配線パターンとの接続箇
所からのずれを抑えることができ、内蔵した電気素子と
配線基板の絶縁層との密着性を高めるとともに、前記電
気素子と配線回路層との接続信頼性を高めることができ
る。[0008] According to such a configuration, when the electric element built in the wiring board is laminated and hardened by hot pressing or the like, a deviation from a connection position with a via hole conductor or a wiring pattern can be suppressed. The adhesion between the electrical element thus formed and the insulating layer of the wiring board can be improved, and the connection reliability between the electrical element and the wiring circuit layer can be improved.
【０００９】上記電気素子内蔵型配線基板では、電気素
子本体が、セラミック質からなり、その表面が焼き上げ
面からなることが望ましい。電気素子の表面に、例え
ば、誘電体セラミックスが焼結して形成された略球状の
セラミック粒子からなる凹凸や開気孔が形成されていれ
ば、内蔵する電気素子の表面粗さをより大きくすること
ができ、熱硬化性樹脂による電気素子表面へのアンカー
効果を高めることができる。In the wiring board with built-in electric elements, it is preferable that the main body of the electric element is made of ceramic and the surface thereof is made of a baked surface. If, for example, irregularities or open pores made of substantially spherical ceramic particles formed by sintering dielectric ceramics are formed on the surface of the electric element, the surface roughness of the built-in electric element should be increased. Therefore, the anchoring effect of the thermosetting resin on the electric element surface can be enhanced.
【００１０】上記電気素子内蔵型配線基板では、前記外
部電極が前記電気素子本体の少なくとも端面に形成され
ており、前記電気素子本体を含めた前記外部電極形成部
の厚さが外部電極非形成部の厚さよりも５μｍ以上厚い
ことが望ましい。このような構成によれば、電気素子本
体に部分的に形成された外部電極のために、電気素子の
表面に自ずと外部電極による凹凸が形成され、電気素子
の外部電極が、絶縁層に埋入し、前記電気素子のずれを
抑えることができる。[0010] In the wiring board with built-in electric element, the external electrode is formed on at least an end surface of the electric element main body, and the thickness of the external electrode forming portion including the electric element main body is reduced to the external electrode non-forming portion. Is desirably 5 μm or more thicker than the thickness. According to such a configuration, unevenness due to the external electrode is naturally formed on the surface of the electric element due to the external electrode partially formed in the electric element body, and the external electrode of the electric element is embedded in the insulating layer. In addition, the displacement of the electric element can be suppressed.
【００１１】さらに、外部電極が電気素子本体よりも凸
状を形成しているために、配線回路層との接続を強める
と同時に、配線基板のビアホール導体の直上に電気素子
の外部電極を配置した場合、ビアホール導体との接合並
びにビアホール導体自体の充填密度を高め、ビアホール
導体の導電性を高めることができる。Further, since the external electrodes are formed in a more convex shape than the main body of the electric element, the connection with the wiring circuit layer is strengthened, and at the same time, the external electrodes of the electric element are arranged immediately above the via-hole conductors of the wiring board. In this case, the bonding with the via hole conductor and the filling density of the via hole conductor itself can be increased, and the conductivity of the via hole conductor can be increased.
【００１２】上記電気素子内蔵型配線基板では、電気素
子が複数の正外部電極と複数の負外部電極とを有する積
層セラミックコンデンサであることが望ましい。例え
ば、電気素子として、多端子の積層セラミックコンデン
サを内蔵することにより、高容量、低インダクタンスの
特性を容易に配線基板に付与することができ、デカップ
リング機能を高めることができる。In the wiring board with built-in electric elements, it is preferable that the electric element is a multilayer ceramic capacitor having a plurality of positive external electrodes and a plurality of negative external electrodes. For example, by incorporating a multi-terminal multilayer ceramic capacitor as an electric element, high-capacity and low-inductance characteristics can be easily imparted to a wiring board, and the decoupling function can be enhanced.
【００１３】上記電気素子内蔵型配線基板では、絶縁基
板が、粒状あるいは繊維状フィラーを含有することが望
ましい。絶縁層中に粒状あるいは繊維状フィラーを含有
することにより、絶縁層の弾性率を高め、熱膨張係数を
低くできる。また、熱硬化性樹脂は、その高いガラス転
移温度のために、高温での処理を伴う他の電気素子の表
面実装や信頼性評価においても、高い寸法安定性を有す
ることができる。In the above-mentioned wiring board with a built-in electric element, the insulating substrate preferably contains a granular or fibrous filler. By containing a granular or fibrous filler in the insulating layer, the elastic modulus of the insulating layer can be increased and the coefficient of thermal expansion can be reduced. In addition, due to its high glass transition temperature, the thermosetting resin can have high dimensional stability in surface mounting and reliability evaluation of other electric elements involving high-temperature processing.
【００１４】加えて、粒状あるいは繊維状フィラーを、
熱硬化性樹脂中に含むことにより、熱硬化性樹脂の粘性
流動に伴う絶縁層の横方向のずれを抑制できる。In addition, a granular or fibrous filler is
By including the thermosetting resin in the thermosetting resin, the lateral displacement of the insulating layer due to the viscous flow of the thermosetting resin can be suppressed.
【００１５】本発明の電気素子内蔵型配線基板の製造方
法は、未硬化の熱硬化性樹脂を含有する複数の絶縁シー
トの一部に所定の電気素子を内蔵するための空隙を加工
する工程と、前記絶縁シートに配線回路層およびビアホ
ール導体を形成する工程と、表面粗さ０．５μｍ以上の
電気素子本体と外部電極を具備する電気素子を前記絶縁
シートの空隙に配置して他の絶縁シートとともに複数積
層した仮積層体を形成する工程と、前記仮積層体を前記
未硬化の熱硬化性樹脂が溶融する温度において加熱加圧
する工程と、熱硬化性樹脂が完全に硬化する温度で加熱
加圧する工程とを含む製造である。The method of manufacturing a wiring board with a built-in electric element according to the present invention comprises the steps of: forming a gap for incorporating a predetermined electric element in a part of a plurality of insulating sheets containing an uncured thermosetting resin; Forming a wiring circuit layer and a via-hole conductor on the insulating sheet; and disposing an electric element having an electric element body having a surface roughness of 0.5 μm or more and an external electrode in a gap of the insulating sheet to form another insulating sheet. Forming a plurality of temporary laminates, heating and pressurizing the temporary laminate at a temperature at which the uncured thermosetting resin melts, and heating at a temperature at which the thermosetting resin is completely cured. Pressurizing.
【００１６】この製法によれば、先ず、絶縁層中の前記
熱硬化性樹脂の溶融温度範囲において加熱加圧すること
により、前記電気素子の表面に形成された凹凸部に充分
に熱硬化性樹脂を浸入させることができ、次に、溶融加
圧温度よりも高い温度において、再度加熱加圧して熱硬
化性樹脂を硬化することにより、電気素子の表面に形成
された凹凸部と、熱硬化性樹脂との間で強固なアンカー
を形成し、電気素子と絶縁層との接着強度を高め、電気
素子を内蔵した配線基板を一括で積層硬化する場合に前
記電気素子の外部電極と配線基板の配線回路層とのずれ
を防止することができる。According to this manufacturing method, the thermosetting resin is first heated and pressurized in the melting temperature range of the thermosetting resin in the insulating layer so that the unevenness formed on the surface of the electric element is sufficiently filled with the thermosetting resin. Then, at a temperature higher than the melting and pressing temperature, the thermosetting resin is again heated and pressed to cure the thermosetting resin, so that the unevenness formed on the surface of the electric element and the thermosetting resin Between the external electrodes of the electric element and the wiring circuit of the wiring board when the wiring board containing the electric element is collectively laminated and hardened by forming a strong anchor between the electric element and the bonding strength between the electric element and the insulating layer. The deviation from the layer can be prevented.
【００１７】[0017]
【発明の実施の形態】（配線基板）本発明の配線基板の
一形態について、図１の概略断面図をもとに詳細に説明
する。本発明の配線基板Ａは、絶縁層１、３、５を３層
積層して構成された絶縁基板７の両表面に配線回路層９
ａ、９ｂを形成して構成されている。また、絶縁層１と
絶縁層３との間、および絶縁層１と絶縁層５の間には、
配線回路層９ｃが形成され、これらの絶縁層１、３、５
には、その厚み方向に金属粉末を充填されてなるビアホ
ール導体１１が形成されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS (Wiring Board) One embodiment of the wiring board of the present invention will be described in detail with reference to the schematic sectional view of FIG. The wiring board A of the present invention has a wiring circuit layer 9 on both surfaces of an insulating substrate 7 formed by laminating three insulating layers 1, 3, and 5.
a and 9b are formed. Further, between the insulating layer 1 and the insulating layer 3 and between the insulating layer 1 and the insulating layer 5,
A wiring circuit layer 9c is formed, and these insulating layers 1, 3, 5,
Is formed with a via-hole conductor 11 filled with metal powder in the thickness direction.
【００１８】ビアホール導体１１は、絶縁基板７の表面
の配線回路層９ａ、９ｂと、絶縁基板７の内部の配線回
路層９ｃを電気的に接続し、さらに、絶縁基板７の両表
面の配線回路層９ａ、９ｂを電気的に接続している。The via-hole conductor 11 electrically connects the wiring circuit layers 9a and 9b on the surface of the insulating substrate 7 to the wiring circuit layer 9c inside the insulating substrate 7, and furthermore, the wiring circuit layers on both surfaces of the insulating substrate 7 The layers 9a and 9b are electrically connected.
【００１９】絶縁層１には、キャビティ１３が形成され
ており、その内部には、電気素子１５が収容され埋設さ
れている。これらの絶縁層１、３、５は、１層当りの厚
みが、５０〜１５０μｍ程度であって、内蔵する電気素
子１５の大きさに応じて適宜所定の厚みに積層形成され
ている。In the insulating layer 1, a cavity 13 is formed, in which an electric element 15 is accommodated and buried. These insulating layers 1, 3, and 5 have a thickness of about 50 to 150 μm per layer, and are appropriately formed in a predetermined thickness in accordance with the size of the built-in electric element 15.
【００２０】絶縁層１中に内蔵される電気素子１５は、
配線基板中のビアホール導体１１と、直接接続できるこ
とから、端部に外部電極を具備するものが好適である。
特に、小型であるという理由から、積層型コンデンサが
好ましい。The electric element 15 built in the insulating layer 1 is
Since it can be directly connected to the via-hole conductor 11 in the wiring board, one having an external electrode at the end is preferable.
In particular, a multilayer capacitor is preferable because of its small size.
【００２１】これらの電気素子１５は、キャビティ１３
の上下面の絶縁層３、５に狭持され、前記電気素子１５
の端部に形成された外部電極１７ａ、１７ｂを介して、
ビアホール導体１１と接続され、絶縁基板７の表面の配
線回路層９ａ、９ｂと電気的に接続されている。These electric elements 15 are
Between the electrical elements 15
Through external electrodes 17a and 17b formed at the ends of
It is connected to the via-hole conductor 11 and is electrically connected to the wiring circuit layers 9 a and 9 b on the surface of the insulating substrate 7.
【００２２】（絶縁層材料）本発明の配線基板Ａにおけ
る絶縁基板７の材質としては、焼成工程を必要としない
有機樹脂を含有する。絶縁層１、３、５の熱膨脹係数や
弾性率を容易に調整する上で、無機質の粒状フィラーと
有機樹脂からなる絶縁材料が、また、絶縁層１、３、５
の機械的強度を高める上で、例えば、ガラス繊維やアラ
ミド繊維などの繊維状フィラーと有機樹脂からなる絶縁
材料が望ましい。(Material for Insulating Layer) The material of the insulating substrate 7 in the wiring board A of the present invention contains an organic resin which does not require a firing step. In order to easily adjust the thermal expansion coefficient and the elastic modulus of the insulating layers 1, 3, and 5, an insulating material composed of an inorganic particulate filler and an organic resin is used.
In order to increase the mechanical strength of the resin, for example, an insulating material made of a fibrous filler such as glass fiber or aramid fiber and an organic resin is desirable.
【００２３】また、無機フィラーは、例えば、Ｓｉ
Ｏ2、Ａｌ2Ｏ3、ＢａＴｉＯ3の群から選ばれる少なくと
も１種を好適に用いることができる。無機フィラーとし
て、ＳｉＯ2を用いた場合は絶縁層の比誘電率を小さく
することができる。また、無機フィラーとして、Ａｌ2
Ｏ3を用いた場合には配線基板の熱伝導率を高めること
ができる。無機フィラーとして、ＢａＴｉＯ3を用いた
場合には絶縁層の比誘電率を高めることができる。特
に、電子機器の小型化、高性能化を目的として、高速伝
送を行うためには、低誘電率のＳｉＯ2を用いることが
望ましい。The inorganic filler is, for example, Si
At least one selected from the group consisting of O 2 , Al 2 O 3 , and BaTiO 3 can be suitably used. When SiO 2 is used as the inorganic filler, the relative dielectric constant of the insulating layer can be reduced. In addition, as an inorganic filler, Al 2
When O 3 is used, the thermal conductivity of the wiring board can be increased. When BaTiO 3 is used as the inorganic filler, the relative dielectric constant of the insulating layer can be increased. In particular, in order to perform high-speed transmission for the purpose of miniaturization and high performance of electronic devices, it is desirable to use SiO 2 having a low dielectric constant.
【００２４】また、絶縁層１、３、５の少なくとも１層
を、無機フィラーの代わりにガラス繊維やアラミド繊維
を含有したいわゆるプリプレグを使用することもでき
る。Further, at least one of the insulating layers 1, 3, and 5 may be made of a so-called prepreg containing glass fiber or aramid fiber instead of the inorganic filler.
【００２５】上記の絶縁層１、３、５に含まれる熱硬化
性樹脂としては、ポリフェニレンエーテル（ＡＰＰＥ）
系樹脂、エポキシ系樹脂およびシアネート系樹脂の群か
ら選ばれる少なくとも１種が好ましい。ＡＰＰＥ系樹脂
は比誘電率が低く、誘電損失が低く、吸水率が低く、さ
らに、ガラス転移点が高いために、高耐熱性であること
から、特に好ましい。さらに、混合物はフィラーとのぬ
れ性を改善するために、分散剤やカップリング剤を含ん
でもよい。The thermosetting resin contained in the insulating layers 1, 3, and 5 is polyphenylene ether (APPE).
At least one selected from the group consisting of a series resin, an epoxy series resin and a cyanate series resin is preferable. An APPE-based resin is particularly preferable because it has a low relative dielectric constant, a low dielectric loss, a low water absorption, and a high glass transition point, and thus has high heat resistance. Further, the mixture may contain a dispersant or a coupling agent to improve the wettability with the filler.
【００２６】（電気素子）電気素子１５は、電気素子本
体１９と、少なくとも端面に外部電極１７ａ、１７ｂと
を具備するものであり、例えば、図２（ａ）に示すよう
な積層セラミックコンデンサを用いることができる。こ
の電気素子本体１９は、内部電極層２１ａ、２１ｂと誘
電体層２３とを交互に積層して構成されている。(Electric Element) The electric element 15 includes an electric element main body 19 and external electrodes 17a and 17b on at least end faces thereof. For example, a multilayer ceramic capacitor as shown in FIG. 2A is used. be able to. The electric element body 19 is configured by alternately stacking the internal electrode layers 21a and 21b and the dielectric layer 23.
【００２７】焼結したセラミック質材料で構成される電
気素子本体１９の表面粗さ（Ｒａ）は、セラミックの素
原料の粒子径や焼結による粒子成長度によって、前記表
面粗さ（Ｒａ）を制御することができ、その表面粗さ
（Ｒａ）は、絶縁層１、３、５に用いている熱硬化性樹
脂の浸入によるアンカー効果を高めるために、０．５μ
ｍ以上が重要である。一方、表面粗さ（Ｒａ）が０．５
μｍより小さいと、熱硬化性樹脂の侵入によるアンカー
効果が低下してしまう。そして、電気素子１５と絶縁層
１、３、５との密着性をさらに高め、同時に、電気素子
本体１９に対する外部電極１７ａ、１７ｂの接合力を高
め、外部電極１７ａ、１７ｂの導電性を高める上で、特
に、０．８〜３μｍが望ましい。The surface roughness (Ra) of the electric element body 19 made of a sintered ceramic material depends on the particle diameter of the ceramic raw material and the degree of particle growth by sintering. The surface roughness (Ra) can be controlled to 0.5 μm in order to enhance the anchoring effect due to the penetration of the thermosetting resin used for the insulating layers 1, 3 and 5.
m or more is important. On the other hand, the surface roughness (Ra) is 0.5
If it is smaller than μm, the anchor effect due to the penetration of the thermosetting resin will be reduced. Then, the adhesion between the electric element 15 and the insulating layers 1, 3, and 5 is further increased, and at the same time, the bonding strength of the external electrodes 17a and 17b to the electric element body 19 is increased, and the conductivity of the external electrodes 17a and 17b is increased. In particular, 0.8 to 3 μm is desirable.
【００２８】このような表面粗さ（Ｒａ）を有する電気
素子本体１９は、例えば、図３（ａ）に示すように、セ
ラミック本体をセラミック粉末を焼成した焼き上げ面に
よって形成される観察面の長軸径が０．１〜１μｍの略
球状粒子２６からなる凹凸面によって構成される。或い
は、セラミックからなる電気素子本体１９を研磨によっ
て、図３（ｂ）に示しているように、最大径が１〜３μ
ｍの開気孔２８が形成されたセラミック焼結体の表面に
よって構成することもできる。The electric element body 19 having such a surface roughness (Ra) is, for example, as shown in FIG. 3 (a), the length of the observation surface formed by baking a ceramic body with ceramic powder. It is constituted by an uneven surface composed of substantially spherical particles 26 having an axis diameter of 0.1 to 1 μm. Alternatively, the electric element body 19 made of ceramic is polished to have a maximum diameter of 1 to 3 μm as shown in FIG.
Alternatively, it may be constituted by the surface of a ceramic sintered body in which m open pores 28 are formed.
【００２９】本発明によれば、このような電気素子１５
において、電気素子本体１９に外部電極１７ａ、１７ｂ
を形成していない外部電極非形成部の厚さをｔ１、一
方、電気素子本体１９外部電極形成部の厚さをｔ２とし
た場合、ｔ１＜ｔ２であることが望ましく、特に、ｔ１
とｔ２の差が５μｍ以上であれば、電気素子１５の外部
電極１７ａ、１７ｂが絶縁層１、３、５に埋入し、電気
素子１５のずれを効果的に抑えることができる。According to the present invention, such an electric element 15
, The external electrodes 17a, 17b
In the case where the thickness of the external electrode non-formed portion where no is formed is t1, and the thickness of the external electrode formed portion of the electric element body 19 is t2, it is preferable that t1 <t2, and in particular, t1
When the difference between t2 and t2 is 5 μm or more, the external electrodes 17a and 17b of the electric element 15 are buried in the insulating layers 1, 3, and 5, and the displacement of the electric element 15 can be effectively suppressed.
【００３０】この外部電極１７ａ、１７ｂは、例えば、
下地金属として、平均粒子径が０．５〜３μｍの略球状
粒子の金属やガラス成分を混合して調製したペーストを
使用しているために、下地金属からなる外部電極１７
ａ、１７ｂの表面粗さ（Ｒａ）は０．５μｍ以上であ
る。この外部電極には、さらに、配線基板に形成してい
るビアホール導体に用いている金属の種類によって、例
えば、順にＮｉメッキ層、Ｓｎメッキ層もしくはＳｎ−
Ｐｂ合金メッキ層を形成することも可能である。The external electrodes 17a and 17b are, for example,
As the base metal, a paste prepared by mixing a metal or glass component of substantially spherical particles having an average particle diameter of 0.5 to 3 μm is used, so that the external electrode 17 made of the base metal is used.
The surface roughness (Ra) of a and 17b is 0.5 μm or more. The external electrodes may further include, for example, a Ni plating layer, a Sn plating layer, or a Sn—
It is also possible to form a Pb alloy plating layer.
【００３１】このようにして構成された配線基板Ａの上
面には、半導体素子２９がハンダ３１により、絶縁基板
７の上面の配線回路層９ａに接続されている。A semiconductor element 29 is connected to the wiring circuit layer 9a on the upper surface of the insulating substrate 7 by solder 31 on the upper surface of the wiring substrate A thus configured.
【００３２】尚、本発明では、絶縁基板７内に電気素子
１５を内蔵した例について説明したが、配線基板Ａの表
層に電気素子１５を挿入できる凹部を設け、電気素子１
５を内蔵しない場合であってもよい。その場合、その電
気素子１５が絶縁層と接する下面の表面粗さ（Ｒａ）を
０．５μｍ以上とすれば良い。In the present invention, the example in which the electric element 15 is built in the insulating substrate 7 has been described. However, a concave portion in which the electric element 15 can be inserted is provided on the surface layer of the wiring board A, and the electric element 1 is provided.
5 may not be incorporated. In this case, the surface roughness (Ra) of the lower surface of the electric element 15 in contact with the insulating layer may be set to 0.5 μm or more.
【００３３】また、電気素子１５としてコンデンサを用
いたが、コンデンサ以外のインダクタ、ＬＣ部品等を内
蔵してもよい。Although a capacitor is used as the electric element 15, an inductor, an LC component, and the like other than the capacitor may be incorporated.
【００３４】次に、本発明の配線基板Ａに内蔵される本
体の表面粗さ（Ｒａ）が０．５μｍ以上の電気素子１５
として、積層セラミックコンデンサを例にして、その製
法を説明する。Next, the electric element 15 having a surface roughness (Ra) of 0.5 μm or more of the main body built in the wiring board A of the present invention.
The manufacturing method will be described using a multilayer ceramic capacitor as an example.
【００３５】先ず、誘電体層２３となる厚さ１．５〜１
２μｍの誘電体グリーンシートを、スリップキャスト法
を用いて作製する。誘電体材料としては、具体的には、
ＢａＴｉＯ3−ＭｎＯ−ＭｇＯ−Ｙ2Ｏ3等の誘電体粉末
と焼結助剤が好適に使用でき、主原料のＢａＴｉＯ3粉
末の合成法は粒度分布が狭く、結晶性が高いという理由
から水熱合成法が望ましい。そして、ＢａＴｉＯ3粉末
の平均粒子径は０．２〜０．５μｍが好ましい。First, the thickness of the dielectric layer 23 is set to 1.5 to 1
A 2 μm dielectric green sheet is produced using a slip casting method. As the dielectric material, specifically,
A dielectric powder such as BaTiO 3 —MnO—MgO—Y 2 O 3 and a sintering aid can be suitably used, and the method of synthesizing the main raw material BaTiO 3 powder has a narrow particle size distribution and high crystallinity. Thermal synthesis is preferred. The average particle diameter of the BaTiO 3 powder is preferably 0.2 to 0.5 μm.
【００３６】また、この誘電体層のセラミックグリーン
シートの厚みは、１２μｍ以下が好ましく、特に、小
型、大容量化という理由から２．５〜４．５μｍの範囲
が望ましい。The thickness of the ceramic green sheet of the dielectric layer is preferably 12 μm or less, and particularly preferably in the range of 2.5 to 4.5 μm from the viewpoint of miniaturization and large capacity.
【００３７】次に、この誘電体層のセラミックグリーン
シートの表面に、スクリーン印刷法などにより内部電極
パターンを形成する。内部電極パターンの厚みは、コン
デンサの小型、高信頼性化という点から２．４μｍ以
下、特には０．６〜１．２μｍの範囲であることが望ま
しい。Next, an internal electrode pattern is formed on the surface of the ceramic green sheet of the dielectric layer by a screen printing method or the like. The thickness of the internal electrode pattern is desirably 2.4 μm or less, particularly preferably in the range of 0.6 to 1.2 μm, from the viewpoint of reducing the size and increasing the reliability of the capacitor.
【００３８】そして、内部電極パターンが形成された誘
電体層のセラミックグリーンシートを複数枚積層圧着し
た後、粗さ０．５〜１μｍのダイヤモンド砥粒をコート
したダイシングソーを用いて切断し、電子部品本体成形
体を得る。Then, a plurality of ceramic green sheets of a dielectric layer on which an internal electrode pattern is formed are laminated and pressed, and then cut using a dicing saw coated with diamond abrasive grains having a roughness of 0.5 to 1 μm. A molded part body is obtained.
【００３９】次に、この電気素子本体成形体を大気中２
５０〜３００℃または酸素分圧０．１〜１Ｐａの低酸素
雰囲気中５００〜８００℃で脱バイした後、非酸化性雰
囲気で１１００〜１３００℃で２〜３時間焼成し、電気
素子本体１９を作製する。Next, the molded body of the electric element body was placed in air 2.
After de-buying at 500 to 800 ° C. in a low oxygen atmosphere of 50 to 300 ° C. or an oxygen partial pressure of 0.1 to 1 Pa, baking is carried out at 1100 to 1300 ° C. for 2 to 3 hours in a non-oxidizing atmosphere, so that Make it.
【００４０】さらに、所望の誘電特性を得るために、酸
素分圧が０．１〜１０-4Ｐａ程度の低酸素分圧下、９０
０〜１１００℃で３〜１０時間熱処理を施すこともあ
る。Further, in order to obtain a desired dielectric property, the oxygen partial pressure is set to 90.degree. C. under a low oxygen partial pressure of about 0.1 to 10.sup.- 4 Pa.
Heat treatment may be performed at 0 to 1100 ° C. for 3 to 10 hours.
【００４１】ここで、必要によっては、得られた電気素
子本体１９を平均粒子径０．５〜３ｍｍのアルミナボー
ルを用いて、ボールミリング方式のバレル研磨機によ
り、電気素子本体１９の表面の研磨を行う。研磨の程度
は、アルミナボールの粒子径と研磨時間によって調整す
ることができる。Here, if necessary, the surface of the electric element main body 19 is polished by a ball milling barrel polishing machine using alumina balls having an average particle diameter of 0.5 to 3 mm. I do. The degree of polishing can be adjusted by the particle size of the alumina ball and the polishing time.
【００４２】最後に、得られた電気素子本体１９に対
し、各端面に非金属あるいは貴金属ペーストを塗布し、
６００〜９００℃の温度で焼き付けを行い、内部電極層
２１ａ、２１ｂと電気的に接続された外部電極１７ａ、
１７ｂを形成して積層セラミックコンデンサを作製す
る。さらに、Ｎｉ／Ｓｎメッキを行うこともできる。Finally, a non-metal or noble metal paste is applied to each end face of the obtained electric element body 19,
Baking is performed at a temperature of 600 to 900 ° C., and the external electrodes 17a, which are electrically connected to the internal electrode layers 21a and 21b,
17b is formed to produce a multilayer ceramic capacitor. Further, Ni / Sn plating can be performed.
【００４３】上記の製法によれば、電気素子本体１９の
表面粗さ（Ｒａ）は、特に、焼き上げ面によって構成す
る場合は、原料の粒子径と焼成条件によって制御でき、
研磨面によって構成する場合は、バレル研磨に用いるア
ルミナボール径と研磨時間によって制御できる。According to the above manufacturing method, the surface roughness (Ra) of the electric element main body 19 can be controlled by the particle diameter of the raw material and the firing conditions, particularly when the electric element main body 19 is constituted by a baked surface.
In the case of using a polished surface, it can be controlled by the diameter of the alumina ball used for barrel polishing and the polishing time.
【００４４】（製法）次に、本発明の電気素子を内蔵し
て配線基板の製造方法について説明する。(Manufacturing Method) Next, a method of manufacturing a wiring board incorporating the electric element of the present invention will be described.
【００４５】先ず、絶縁層形成用として、ポリフェニレ
ンエーテル系樹脂、エポキシ系樹脂などの熱硬化性樹脂
と、ＳｉＯ2、Ａｌ2Ｏ3などの不定形の無機質フィラー
との混合材料からなる厚さ８０〜１５０μｍの未硬化状
態の絶縁シートをドクターブレード法により作製する。First, for forming an insulating layer, a thickness 80 of a mixed material of a thermosetting resin such as a polyphenylene ether resin or an epoxy resin and an amorphous inorganic filler such as SiO 2 or Al 2 O 3 is used. An uncured insulating sheet having a thickness of 150 μm is produced by a doctor blade method.
【００４６】そして、図４（ａ）、（ｃ）に示すよう
に、絶縁層３、５となる絶縁シート４１、４５にビアホ
ール４７を炭酸ガスレーザーやパンチングなどによって
形成する。次に、図４（ｂ）に示すように、上記絶縁層
１となる絶縁シート４９に対して、電気素子１５を内蔵
するキャビティ５１、およびビアホール４７を形成す
る。Then, as shown in FIGS. 4A and 4C, via holes 47 are formed in the insulating sheets 41 and 45 to be the insulating layers 3 and 5 by a carbon dioxide laser or punching. Next, as shown in FIG. 4B, a cavity 51 containing the electric element 15 and a via hole 47 are formed in the insulating sheet 49 serving as the insulating layer 1.
【００４７】次に、図４（ｄ）に示すように、絶縁シー
ト４１、４５、４９のビアホール４７に、Ｃｕ粉末を含
有する導電性ペーストを充填して、ビアホール導体５１
を形成する。Next, as shown in FIG. 4D, the via holes 47 of the insulating sheets 41, 45, and 49 are filled with a conductive paste containing Cu powder to form the via hole conductors 51.
To form
【００４８】その後、この絶縁シート４１、４５、４９
の表面に、配線回路層５３を形成する。これらの配線回
路層５３は、例えば、銅箔、Ａｌ箔などの金属箔を絶縁
シート４１、４５、４９の表面に転写した後、レジスト
塗布、露光、現像、エッチング、レジスト除去の工程に
よって、所定のパターンの導体層を形成する方法、また
は、あらかじめ、樹脂フィルムの表面に前記絶縁シート
の表面に転写する方法がある。このうち、後者の方法
は、絶縁シートがエッチング液などにさらされることが
なく、絶縁シートが劣化することがない点で後者の方が
好適である。Thereafter, the insulating sheets 41, 45, 49
The wiring circuit layer 53 is formed on the surface of the substrate. These wiring circuit layers 53 are formed, for example, by transferring a metal foil such as a copper foil or an Al foil onto the surfaces of the insulating sheets 41, 45, and 49, and then performing a resist coating, exposure, development, etching, and resist removal steps. Or a method in which the conductor layer is transferred to the surface of the insulating sheet in advance on the surface of the resin film. Among them, the latter method is preferable in that the insulating sheet is not exposed to an etchant or the like and the insulating sheet is not deteriorated.
【００４９】そして、絶縁シート４９のキャビティ５１
内に電気素子１５を設置し、この絶縁シート４９の上下
に、前記絶縁シート４１、４５を積層する。その後、こ
の積層物を前記絶縁シート中の熱硬化性樹脂が溶融する
温度範囲よりも、低い温度８０〜１１０℃、圧力２〜１
０ｋｇ／ｃｍ2で一旦加熱加圧を行い、電気素子１５の
表面に形成された凹凸部に絶縁層１、３、５を形成して
いる熱硬化性樹脂を十分に含浸させる。The cavity 51 of the insulating sheet 49
The electric element 15 is installed in the inside, and the insulating sheets 41 and 45 are laminated on and under the insulating sheet 49. Thereafter, the laminate is heated at a temperature lower than a temperature range in which the thermosetting resin in the insulating sheet melts, at a temperature of 80 to 110 ° C. and a pressure of 2-1.
Heating and pressurization is performed once at 0 kg / cm 2 to sufficiently impregnate the unevenness formed on the surface of the electric element 15 with the thermosetting resin forming the insulating layers 1, 3 and 5.
【００５０】その後、熱硬化性樹脂の溶融温度よりも高
い温度１７０〜２４０℃において、圧力１２〜４０ｋｇ
／ｃｍ2で加熱加圧を行い、内蔵した電気素子１５と絶
縁層１、３、５の界面を強固に接着するとともに、絶縁
層１、３、５どうしを積層密着して配線基板Ａを作製す
る。Thereafter, at a temperature of 170 to 240 ° C. higher than the melting temperature of the thermosetting resin, a pressure of 12 to 40 kg
/ Cm 2 , and the interface between the built-in electric element 15 and the insulating layers 1, 3, and 5 is firmly adhered, and the insulating layers 1, 3, and 5 are laminated and adhered to each other to produce a wiring board A I do.
【００５１】このように、無機フィラーと熱硬化性樹脂
との混合材料からなる未硬化の絶縁シート４１、４５、
４９にビアホール導体５１や配線回路層５３を形成した
後、積層して配線基板Ａを作製することから、高密度実
装用の配線基板Ａを作製することができる。As described above, the uncured insulating sheets 41 and 45 made of the mixed material of the inorganic filler and the thermosetting resin,
After the via-hole conductor 51 and the wiring circuit layer 53 are formed on the substrate 49 and laminated to form the wiring board A, the wiring board A for high-density mounting can be manufactured.
【００５２】また、このような配線基板Ａは絶縁層１、
３、５の少なくとも一層に、プリプレグを用いる場合に
おいても、上記の形態と同様の製法で作製できる。Further, such a wiring board A has an insulating layer 1,
Even when a prepreg is used for at least one of the layers 3 and 5, it can be manufactured by the same manufacturing method as in the above embodiment.
【００５３】[0053]
【実施例】先ず、内蔵する電気素子として、例えば、積
層セラミックコンデンサを次のように作製した。ＢａＴ
ｉＯ3系の複数のセラミック誘電体シートの表面に、Ｎ
ｉの金属ペーストを用いて図２（ｂ）、（ｃ）に示した
ような内部電極パターンをスクリーン印刷した。その
後、それらのシートを温度５５℃、圧力１５０ｋｇ／ｃ
ｍ2下で積層密着して積層体を作製し、所定の粗さのダ
イヤモンド砥粒をコートしたダイシングソーを用いて切
断して電気素子本体成形体を得た。次に、この電気素子
本体成形体を大気中２５０℃、０．１Ｐａの低酸素雰囲
気中７００℃の条件で、脱バイを行った。その後、非酸
化性雰囲気下１２５０℃の温度において焼成し、更に、
低酸素分圧下１１００℃において酸化処理を行い、電気
素子本体１９となる厚さ０．２ｍｍのコンデンサ素体を
作製した。EXAMPLES First, as a built-in electric element, for example, a multilayer ceramic capacitor was manufactured as follows. BaT
The surface of a plurality of iO 3 -based ceramic dielectric sheets is
An internal electrode pattern as shown in FIGS. 2B and 2C was screen-printed using the metal paste i. Thereafter, the sheets were heated at a temperature of 55 ° C. and a pressure of 150 kg / c.
A laminated body was prepared by lamination and adhesion under m 2 , and cut using a dicing saw coated with diamond abrasive grains of a predetermined roughness to obtain an electric element body molded body. Next, the electric element main body was deburied under the conditions of 250 ° C. in the air and 700 ° C. in a low oxygen atmosphere of 0.1 Pa. Then, it is fired at a temperature of 1250 ° C. in a non-oxidizing atmosphere.
Oxidation treatment was performed at 1100 ° C. under a low oxygen partial pressure to prepare a 0.2 mm thick capacitor element to be the electric element body 19.
【００５４】次に、このコンデンサ素体の表面を平均の
直径が２ｍｍのアルミナボールを用いたボールミリング
法によりバレル研磨を行い、表１に示すように、バレル
研磨の時間を変更することによって、コンデンサ素体の
表面粗さ（Ｒａ）を調整した。試料数は、各バレル条件
に対して、ｎ＝１００とした。また、コンデンサ素体の
表面粗さ（Ｒａ）は、原子間力顕微鏡（ＡＦＭ）を用い
て測定した。測定個数は各バレル条件に対して、試料数
＝５とし、１サンプルについて、測定領域を１ｍｍ2と
し、各試料を３箇所測定した。Next, the surface of the capacitor body was subjected to barrel polishing by a ball milling method using alumina balls having an average diameter of 2 mm, and as shown in Table 1, the barrel polishing time was changed. The surface roughness (Ra) of the capacitor body was adjusted. The number of samples was n = 100 for each barrel condition. The surface roughness (Ra) of the capacitor body was measured using an atomic force microscope (AFM). The number of measurements was 5 for each barrel condition, and the measurement area was 1 mm 2 for one sample, and each sample was measured at three locations.
【００５５】次に、このコンデンサ素体の表面に、Ｃｕ
／Ｎｉのペーストを外部電極形成部に塗布して温度８５
０℃で焼付け、図２（ａ）に示したようなセラミックコ
ンデンサを作製した。なお、このコンデンサは、その寸
法が１．６ｍｍ×１．２ｍｍ×０．３ｍｍ、静電容量が
１０ｎＦ、自己インダクタンスが５４０ｐＨであった。Next, Cu was added to the surface of the capacitor body.
/ Ni paste is applied to the external electrode forming portion and the temperature is 85
Baking was performed at 0 ° C. to produce a ceramic capacitor as shown in FIG. The dimensions of the capacitor were 1.6 mm × 1.2 mm × 0.3 mm, the capacitance was 10 nF, and the self-inductance was 540 pH.
【００５６】次に、図１に示すような電気素子内蔵型配
線基板を作製した。Next, an electric element built-in type wiring board as shown in FIG. 1 was manufactured.
【００５７】また、Ｃｕ／Ｎｉペーストの塗布量を制御
して外部電極形成部の厚みｔ２が異なる種々のコンデン
サを作製した。Further, various capacitors having different thicknesses t2 of the external electrode forming portions were manufactured by controlling the amount of the Cu / Ni paste applied.
【００５８】先ず、ＡＰＰＥ樹脂に対し、不定形のシリ
カ粉末を所定量の割合となるように、ワニス状態の樹脂
と粉末を混合し、ドクターブレード法により、厚さ１２
０μｍの絶縁シートを作製し、それらの絶縁シートに、
炭酸ガスレーザーにより、ビアホール（直径０．１ｍ
ｍ）を形成し、そのビアホールに、Ｃｕ粉末を含有する
導電性ペーストを充填してビアホール導体を形成し、図
１の絶縁層３、５となる絶縁シート４１、４５を作製し
た。First, the resin and powder in a varnish state were mixed with the APPE resin so that the amorphous silica powder had a predetermined ratio, and the mixture was applied to a thickness of 12 by a doctor blade method.
0 μm insulating sheets are produced, and the insulating sheets are
Via holes (0.1 m diameter)
m) was formed, and the via holes were filled with a conductive paste containing Cu powder to form via-hole conductors, and insulating sheets 41 and 45 to be the insulating layers 3 and 5 in FIG. 1 were produced.
【００５９】次に、上記絶縁シート４１、４５と同等の
試料厚の絶縁シート４９に、炭酸ガスレーザーによるト
レパン加工により、収納するコンデンサの大きさよりも
わずかに大きいキャビティ用貫通孔と、同じく、炭酸ガ
スレーザーにより、ビアホール（直径０．１ｍｍ）を形
成し、そのビアホールに、Ｃｕ粉末を含有する導電性ペ
ーストを充填してビアホール導体を形成し、図１の絶縁
層１となる絶縁シート４９を作製した。Next, an insulating sheet 49 having a sample thickness equivalent to that of the insulating sheets 41 and 45 was formed by trepanning using a carbon dioxide gas laser to form a through hole for a cavity slightly larger than the size of the capacitor to be stored. Via holes (diameter: 0.1 mm) are formed by a gas laser, and the via holes are filled with a conductive paste containing Cu powder to form via hole conductors, thereby producing an insulating sheet 49 to be the insulating layer 1 in FIG. did.
【００６０】次に、ポリエチレンテレフタレート（ＰＥ
Ｔ）樹脂からなる転写シートの表面に接着剤を塗布し、
厚さ１２μｍ、表面粗さ０．８μｍの銅箔を一面に接着
した。そして、ドライフィルムレジストを貼り、露光、
現像を行った後、これを塩化第二鉄溶液を用いたスプレ
ー式エッチング装置を用いて、非パターン部をエッチン
グ除去して、銅箔からなる導体層を形成した転写シート
を作製した。Next, polyethylene terephthalate (PE)
T) applying an adhesive to the surface of the transfer sheet made of resin,
A copper foil having a thickness of 12 μm and a surface roughness of 0.8 μm was bonded to one surface. Then, apply a dry film resist, expose,
After the development, the non-pattern portion was removed by etching using a spray-type etching apparatus using a ferric chloride solution to prepare a transfer sheet on which a conductor layer made of a copper foil was formed.
【００６１】そして、ビアホール導体を含む絶縁シート
４１、４５、４９の表面に、転写シートの導体層側を１
３０℃、２０ｋｇ／ｃｍ2の条件で圧着した後、転写シ
ートを剥がして、導体層を絶縁シート４１、４５、４９
に転写した。Then, the conductor layer side of the transfer sheet is placed on the surface of the insulating sheets 41, 45, and 49 including the via hole conductor.
After pressure-bonding at 30 ° C. and 20 kg / cm 2 , the transfer sheet was peeled off, and the conductor layers were separated from the insulating sheets 41, 45 and 49.
Transferred to
【００６２】次に、キャビティ用貫通孔、およびビアホ
ール導体を形成した絶縁シート４９のキャビティ内に積
層セラミックコンデンサを仮設置した。Next, the multilayer ceramic capacitor was temporarily installed in the cavity of the insulating sheet 49 in which the through hole for the cavity and the via hole conductor were formed.
【００６３】そして、その絶縁シート４９の表面および
裏面に、上記の工程を経て作製された導体層およびビア
ホール導体を有する絶縁シート４１、４５を仮積層し
た。Then, on the front and back surfaces of the insulating sheet 49, insulating sheets 41 and 45 having the conductor layer and the via-hole conductor manufactured through the above steps were temporarily laminated.
【００６４】そして、この積層物を真空ホットプレス装
置内に置き、圧力１０ｋｇ／ｃｍ2、昇温速度７℃／ｍ
ｉｎ．で加熱し、１００℃に到達したところで、３０分
間の保持を行い、積層セラミックコンデンサを絶縁層に
固着した。その後、同じ昇温速度で、圧力４０ｋｇ／ｃ
ｍ2で、２２０℃まで昇温し、最高温度２２０℃で、１
時間加熱して、完全硬化させて、絶縁層１、３、５の厚
みが０．１ｍｍの図１に示した電気素子内蔵型配線基板
を作製した。そして、作製した電気素子内蔵配線基板に
対して、以下の検討を行った。Then, the laminate was placed in a vacuum hot press apparatus, and the pressure was 10 kg / cm 2 , and the temperature was raised at a rate of 7 ° C./m.
in. When the temperature reached 100 ° C., holding was performed for 30 minutes to fix the multilayer ceramic capacitor to the insulating layer. Then, at the same heating rate, pressure of 40 kg / c
m 2 , the temperature was raised to 220 ° C.
Heating was performed for a period of time to complete the curing, thereby producing the wiring board with a built-in electric element shown in FIG. 1 in which the thickness of the insulating layers 1, 3, and 5 was 0.1 mm. The following study was performed on the manufactured wiring board with built-in electric elements.
【００６５】内蔵した電気素子１５の配線基板Ａ内部で
のずれ量は、配線基板Ａのクロスセクション試料を作製
し、デジタルマイクロスコープを用いて、倍率５０〜１
００倍にて、観察により求めた。The amount of displacement of the built-in electric element 15 inside the wiring board A can be determined by preparing a cross-section sample of the wiring board A and using a digital microscope at a magnification of 50 to 1.
It was determined by observation at × 00.
【００６６】配線基板Ａのインダクタンスは、インピー
ダンスアナライザを用いて、周波数１．０ＭＨｚ〜１．
８ＭＨｚにおいて、まず、インピーダンスの周波数特性
を測定し、同時に、１ＭＨｚでのコンデンサの静電容量
を測定し、そして、ｆ0＝１／（２π（Ｌ／Ｃ）1/2）
（式中、ｆ0：共振周波数（Ｈｚ）、Ｃ：静電容量
（Ｆ）、Ｌ：インダクタンス（Ｈ））に基づいて、共振
周波数からインダクタンスを計算で求めた（Ｌ（室
温））。なお、この測定は熱衝撃試験を１００サイクル
行った後にも測定し、（Ｌ（ＴＳ後））、試験前と比較
した。尚、熱衝撃試験の条件は、温度範囲が−５５〜１
２５℃、最高最低温度での保持時間は各５分とした。The inductance of the wiring board A can be measured at a frequency of 1.0 MHz to 1.
At 8 MHz, first measure the frequency characteristics of the impedance, at the same time measure the capacitance of the capacitor at 1 MHz, and then f 0 = 1 / (2π (L / C) 1/2 )
(Where f 0 : resonance frequency (Hz), C: capacitance (F), L: inductance (H)), the inductance was calculated from the resonance frequency (L (room temperature)). This measurement was also performed after 100 cycles of the thermal shock test (L (after TS)) and compared with the value before the test. In addition, the conditions of the thermal shock test are as follows.
The holding time at 25 ° C. and the maximum and minimum temperatures was 5 minutes each.
【００６７】[0067]
【表１】 [Table 1]
【００６８】表１の結果から明らかなように、本発明に
基づき作製した配線基板Ａにおいて、電気素子１５の表
面粗さ（Ｒａ）を０．５μｍ以上に調整した試料Ｎｏ．
１〜８では、配線基板Ａ内でのビアホール導体１１から
の電気素子１５のずれ量を、６５μｍ以下と小さくで
き、電気素子１５を内蔵した配線基板Ａのインダクタン
スが安定し、室温と熱衝撃試験後のインダクタンスの差
を７０ｐＨ以下に低減できた。一方、バレル研磨時間を
５０分まで長くして、表面粗さ（Ｒａ）を０．１μｍと
した試料Ｎｏ．９では、ずれ量が大きく、室温と熱衝撃
試験後のインダクタンスの差が増大した。また、ｔ２−
ｔ１≧５μｍとすることにより、ずれ量を小さくできる
ことがわかった。As is clear from the results shown in Table 1, in the wiring board A manufactured according to the present invention, the sample No. 1 in which the surface roughness (Ra) of the electric element 15 was adjusted to 0.5 μm or more was used.
In Nos. 1 to 8, the deviation of the electric element 15 from the via-hole conductor 11 in the wiring board A can be reduced to 65 μm or less, the inductance of the wiring board A incorporating the electric element 15 is stabilized, and the room temperature and the thermal shock test are performed. The subsequent difference in inductance could be reduced to 70 pH or less. On the other hand, the barrel polishing time was extended to 50 minutes, and the surface roughness (Ra) was set to 0.1 μm. In No. 9, the deviation was large, and the difference between the room temperature and the inductance after the thermal shock test was increased. Also, t2-
It was found that the deviation amount can be reduced by setting t1 ≧ 5 μm.
【００６９】[0069]
【発明の効果】上述した通り、本発明によれば、配線基
板に内蔵する電気素子の表面粗さ（Ｒａ）を０．５μｍ
以上とすることにより、前記凹凸部に絶縁層を構成する
熱硬化性樹脂を浸入させ、熱硬化性樹脂によるアンカー
効果を高めることにより、内蔵した電気素子を固定し、
配線基板のビアホール導体と電気素子の接続端子間との
接続を確実に行うことができる。As described above, according to the present invention, the surface roughness (Ra) of the electric element incorporated in the wiring board is 0.5 μm.
By doing the above, the thermosetting resin constituting the insulating layer is infiltrated into the uneven portion, and the anchoring effect of the thermosetting resin is enhanced, thereby fixing the built-in electric element,
The connection between the via-hole conductor of the wiring board and the connection terminal of the electric element can be reliably performed.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の電気素子内蔵型配線基板の概略断面図
である。FIG. 1 is a schematic sectional view of a wiring board with a built-in electric element of the present invention.
【図２】本発明で用いられる電気素子（コンデンサ素
子）を説明するためのものであって、（ａ）は全体斜視
図、（ｂ）、（ｃ）は内部電極のパターン図である。FIGS. 2A and 2B are views for explaining an electric element (capacitor element) used in the present invention, wherein FIG. 2A is an overall perspective view, and FIGS. 2B and 2C are pattern diagrams of internal electrodes.
【図３】本発明で用いられる電気素子（コンデンサ素
子）を説明するものであって、（ａ）は焼き上げ面の略
球状粒子の模式図、（ｂ）は研磨した断面の開気孔の模
式図である。3A and 3B are diagrams illustrating an electric element (capacitor element) used in the present invention, wherein FIG. 3A is a schematic view of a substantially spherical particle on a baked surface, and FIG. It is.
【図４】本発明の電気素子内蔵型配線基板の工程図であ
る。FIG. 4 is a process drawing of the wiring board with a built-in electric element of the present invention.
Ａ 配線基板 ７ 絶縁基板 ９ａ、９ｂ、９ｃ 配線回路層 １１ ビアホール導体 １３ キャビティ １５ 電気素子 １７ａ、１７ｂ 外部電極 １９ 電気素子本体 ２６ 略球状粒子 ２８ 開気孔 Reference Signs List A Wiring board 7 Insulating substrate 9a, 9b, 9c Wiring circuit layer 11 Via hole conductor 13 Cavity 15 Electric element 17a, 17b External electrode 19 Electric element main body 26 Substantially spherical particle 28 Open pore
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｇ 1/035 Ｅ Ｆターム(参考） 5E346 AA02 AA04 AA12 AA15 AA29 AA32 AA43 BB20 CC04 CC05 CC08 CC32 CC34 CC53 EE09 EE12 EE13 EE14 EE19 EE20 FF01 FF18 FF22 FF27 GG15 HH07 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01G 1/035 EF term (Reference) 5E346 AA02 AA04 AA12 AA15 AA29 AA32 AA43 BB20 CC04 CC05 CC08 CC32 CC34 CC53 EE09 EE12 EE13 EE14 EE19 EE20 FF01 FF18 FF22 FF27 GG15 HH07
Claims (6)
板と、該絶縁基板の表面および／または内部に形成され
た配線回路層と、前記絶縁基板内部に形成され、金属粉
末が充填されてなるビアホール導体とを具備する配線基
板内に、電気素子を内蔵した電気素子内蔵型配線基板に
おいて、前記電気素子が、電気素子本体と、該電気素子
本体の一部に設けられ、前記ビアホール導体と直接的に
接続される外部電極を具備するとともに、前記電気素子
本体の表面粗さ（Ｒａ）が０．５μｍ以上であることを
特徴とする電気素子内蔵型配線基板。1. An insulating substrate containing at least a thermosetting resin, a wiring circuit layer formed on the surface and / or inside of the insulating substrate, and a metal powder formed inside the insulating substrate and filled with metal powder. An electric element built-in type wiring board in which an electric element is embedded in a wiring board having a via hole conductor, wherein the electric element is provided in an electric element main body and a part of the electric element main body, and is directly connected to the via hole conductor. An electric element built-in type wiring board, comprising external electrodes which are electrically connected, and wherein the surface roughness (Ra) of the electric element body is 0.5 μm or more.
その表面が焼き上げ面からなることを特徴とする請求項
１記載の電気素子内蔵型配線基板。2. The electric element body is made of a ceramic material.
2. The wiring board with a built-in electric element according to claim 1, wherein the surface is a baked surface.
くとも端面に形成されており、前記電気素子本体を含め
た前記外部電極形成部の厚さが外部電極非形成部の厚さ
よりも５μｍ以上厚いことを特徴とする請求項１または
２記載の電気素子内蔵型配線基板。3. The external electrode is formed on at least an end face of the electric element main body, and the thickness of the external electrode forming portion including the electric element main body is 5 μm or more than the thickness of the external electrode non-forming portion. The wiring board with a built-in electric element according to claim 1, wherein the wiring board is thick.
部電極を有する積層セラミックコンデンサであることを
特徴とする請求項１乃至３のうちいずれかに記載の電気
素子内蔵型配線基板。4. The wiring board with a built-in electric element according to claim 1, wherein the electric element is a multilayer ceramic capacitor having a plurality of positive external electrodes and a plurality of negative external electrodes.
を含有することを特徴とする請求項１乃至４のうちいず
れかに記載の電気素子内蔵型配線基板。5. The wiring board with a built-in electric element according to claim 1, wherein the insulating substrate contains a granular or fibrous filler.
縁シートの一部に所定の電気素子を内蔵するための空隙
を加工する工程と、前記絶縁シートに配線回路層および
ビアホール導体を形成する工程と、表面粗さ０．５μｍ
以上の電気素子本体と外部電極を具備する電気素子を前
記絶縁シートの空隙に配置して他の絶縁シートとともに
複数積層した仮積層体を形成する工程と、前記仮積層体
を前記未硬化の熱硬化性樹脂が溶融する温度において、
加熱加圧する工程と、熱硬化性樹脂が完全に硬化する温
度で加熱加圧する工程とを具備することを特徴とする電
気素子内蔵型配線基板の製造方法。6. A process for forming a gap for incorporating a predetermined electric element in a part of a plurality of insulating sheets containing an uncured thermosetting resin, and forming a wiring circuit layer and a via-hole conductor on the insulating sheet. Forming step, surface roughness 0.5 μm
A step of arranging the electric element including the electric element body and the external electrode in the gap of the insulating sheet to form a temporary laminated body in which a plurality of electric elements are laminated together with other insulating sheets; At the temperature at which the curable resin melts,
A method for producing a wiring board with a built-in electric element, comprising: a step of heating and pressing; and a step of heating and pressing at a temperature at which a thermosetting resin is completely cured.
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|---|---|---|---|
| JP2000294746A JP4610067B2 (en) | 2000-09-27 | 2000-09-27 | Manufacturing method of wiring board with built-in electric element |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000294746A JP4610067B2 (en) | 2000-09-27 | 2000-09-27 | Manufacturing method of wiring board with built-in electric element |
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| Publication Number | Publication Date |
|---|---|
| JP2002111219A true JP2002111219A (en) | 2002-04-12 |
| JP4610067B2 JP4610067B2 (en) | 2011-01-12 |
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ID=18777285
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|---|---|---|---|
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| JP2009529233A (en) * | 2006-03-10 | 2009-08-13 | ジョインセット カンパニー リミテッド | Ceramic component element, ceramic component and manufacturing method thereof |
| JP4744609B2 (en) * | 2006-03-10 | 2011-08-10 | ジョインセット カンパニー リミテッド | Ceramic component element, ceramic component and manufacturing method thereof |
| JP2008066712A (en) * | 2006-08-09 | 2008-03-21 | Murata Mfg Co Ltd | Multilayer capacitor, circuit substrate, circuit module, and manufacturing method for multilayer capacitor |
| JP2011129688A (en) * | 2009-12-17 | 2011-06-30 | Tdk Corp | Electronic component and terminal electrode |
| CN103854852A (en) * | 2012-12-04 | 2014-06-11 | 三星电机株式会社 | Embedded multilayer ceramic electronic component and method of manufacturing the same, and printed circuit board having embedded multilayer ceramic electronic component therein |
| JP2014110417A (en) * | 2012-12-04 | 2014-06-12 | Samsung Electro-Mechanics Co Ltd | Board built-in multilayer ceramic electronic component and manufacturing method therefor, printed circuit board including board built-in multilayer ceramic electronic component |
| US10887995B2 (en) | 2012-12-27 | 2021-01-05 | Samsung Electro-Mechanics Co., Ltd. | Method for manufacturing a printed circuit board including an embedded electronic component |
| US9370102B2 (en) | 2012-12-28 | 2016-06-14 | Samsung Electro-Mechanics Co., Ltd. | Embedded multilayer ceramic electronic component and printed circuit board having embedded multilayer ceramic electronic component |
| JP2014130987A (en) * | 2012-12-28 | 2014-07-10 | Samsung Electro-Mechanics Co Ltd | Board built-in multilayer ceramic electronic component and multilayer ceramic electronic component built-in printed circuit board |
| KR101499721B1 (en) * | 2013-08-09 | 2015-03-06 | 삼성전기주식회사 | Embedded multilayer ceramic electronic part and print circuit board having embedded multilayer ceramic electronic part |
| US9424989B2 (en) | 2013-08-09 | 2016-08-23 | Samsung Electro-Mechanics Co., Ltd. | Embedded multilayer ceramic electronic component and printed circuit board having the same |
| WO2017038791A1 (en) * | 2015-09-02 | 2017-03-09 | 株式会社村田製作所 | Resin circuit board and component-mounting resin circuit board |
| JPWO2017038791A1 (en) * | 2015-09-02 | 2018-03-01 | 株式会社村田製作所 | Resin circuit board, component-mounted resin circuit board |
| US10278289B2 (en) | 2015-09-02 | 2019-04-30 | Murata Manufacturing Co., Ltd. | Resin circuit board and resin circuit board having component mounted thereon |
| US20170345571A1 (en) * | 2016-05-24 | 2017-11-30 | Tdk Corporation | Multilayer ceramic capacitor |
| CN107424842A (en) * | 2016-05-24 | 2017-12-01 | Tdk株式会社 | Multi-layer ceramic capacitor |
| US10381159B2 (en) * | 2016-05-24 | 2019-08-13 | Tdk Corporation | Multilayer ceramic capacitor |
| CN107424842B (en) * | 2016-05-24 | 2020-05-05 | Tdk株式会社 | Laminated ceramic capacitor |
| JP2019079915A (en) * | 2017-10-24 | 2019-05-23 | 京セラ株式会社 | Chip-type electronic component and module |
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