JPS5818640B2 - scale time signal - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a scale time signal that oscillates a time signal using a scale. It comprises a frequency divider that outputs one pulse per hour, a shift register driven by the output thereof, and a flip-flop circuit, and the output terminal of the flip-flop circuit and the second output terminal of the frequency divider are connected by an AND gate. The output terminal of the last stage of the ring counter is connected to the reset terminal of the flip-flop circuit, and each output terminal of the corresponding order of the ring counter and the shift register is connected to an AND circuit. The output terminals of these AND circuits are connected to the control poles of the respective gate circuits interposed in the passage circuits for a plurality of sound source signals.

The second invention is based on the first invention, by providing a circuit that connects the output terminals of each gate circuit in common and outputting the output directly and a circuit that outputs the output via a frequency divider, and intervening the gate circuit in each of these circuits. The control poles of these gate circuits are connected to one and the other output terminals of a flip-flop circuit connected to the output terminal of the time unit frequency divider via a frequency divider.

Next, embodiments of the present invention will be described with reference to the attached drawings.

In Fig. 1, 1 is a plug connected to a commercial AC power supply, 2 is a voltage regulator, and 3 is a frequency divider that outputs one pulse per hour, and the first to third frequency dividers 3a + 3b, 3c The first frequency divider 3a has a frequency division ratio of 50 or 60 depending on the frequency of the commercial power supply, and the second and third frequency dividers 3b and 3c have a frequency division ratio of 60.

Before, the output terminal of the frequency divider 3 is connected to the set terminal of the flip-flop circuit 5 through the monostable multi-bi break-4.
It was connected to the input terminal of the shift register 6.

The output terminal of the flippf amplifier circuit 5 and the output terminal of the first frequency divider 3a were connected to an AND gate 7, and the output terminal was connected to the input terminal of a ring counter 8.

The register 6 and the ring counter 8 each have 12 stages, and the output terminal of each stage is connected to an AND circuit 9-1.
...Connected to 9-12.

The output terminals of these AND circuits 9-1...9-12 are connected to the sound source signal passing circuits 10-1...10-12.
Gate circuits 11-1...11-12 that intervened in
connected to each.

12-1...12-12 each indicate a sound source signal generator that generates a musical scale.

And those sound source signal passing circuits 10-1...
The output terminals 10-12 were connected in common and connected to a speaker 16 via an envelope forming circuit 13, a filter 14, and an amplifier 15.

The output terminal of the last stage of the ring counter 8 was connected to the reset terminal of the flip-flop circuit 5 through a monostable multi-by-break 17 activated by the falling edge of the output pulse obtained therefrom.

In addition, the output terminal of the AND circuit 9-12 is a monostable multi-bi break-1 which operates on the falling edge of the pulse obtained there.
Said shift register via 8.

Connected to the reset terminal of Star 6.

Next, the operation of this device will be explained.

Now, the first to third frequency dividers 3 a y 3 b of the frequency divider 3
+3c and after one hour of counting the frequency of the commercial AC power supply, "1" is output from the output terminal of the third frequency divider 3c, and the rising part (therefore, the monostable multi-bi break -4 A trigger pulse is outputted from the trigger pulse and inputted to the flip-flop circuit 5 and the shift register 6.

The flip-flop circuit 5 is set, its output terminal becomes "1", and the output pulse of the first frequency divider 3a is ANDed.
It passes through gate 7 and is added to ring counter 8, and "1" is output from its first output terminal.

On the other hand, "1" is also output from the first output terminal of the shift register 6, "1" is output from the first A and ND circuit 9-1, the gate circuit 11-1 is opened, and the sound source is C sound is obtained from the speaker 16.

The pulses from the first frequency divider 3a are sequentially sent to the next stage, and the signals are sequentially output from the second to twelfth output terminals. Since it is activated only by the output pulse 3c and maintains the set state of the first stage, no output signal is output to the second to twelfth output terminals.

Thus, only the ring counter 8 repeats its operation, and at the falling edge of the pulse obtained from the last output terminal, the monostable multi-bi break-17 operates to generate a reset pulse and reset the flip-flop circuit 5.

Thus, only the C note is obtained, which signals, for example, 1 o'clock.

Next, after one hour has passed, the third frequency divider 3c outputs “1”.
When this is output, the second stage of the shift register 6 is also activated following the first stage, and the second stage is outputted to the first and second output terminals.

The output pulse of the first frequency divider 3a sequentially operates each stage of the ring counter 8 to issue output signals to the first to twelfth output terminals.
A, ND circuits 9-1 and 9-2 are made conductive, and the first and second gate circuits are sequentially opened (opened) to pass the signal of C sound 0# sound to obtain C sound and O# sound. Announces 2 o'clock.

Next, when another hour has passed, the first to third stages of the shift resin taro are activated, and the first, second, third, and third gates 9-1, 9-2, and 9-3 are opened as the ring counter 8 is activated in sequence. The sound of C, 0#, and D are heard in sequence, indicating 3 o'clock.

When the time signal is thus given until 12 o'clock, the shift register 6 is reset by the output of the monostable multi-high router 18, and a new time signal is given from 1 o'clock.

FIG. 2 shows a system in which, after reporting until 12 o'clock as described above, the pitch of the time signal is changed when a new report is made from 1 o'clock, and the gate circuits 11-1...11- 1
Circuit 19 that connects the two output terminals in common and outputs directly
and a circuit 21 for output via a frequency divider 20 with a frequency division ratio of 2, and these circuits 19.21 are connected to respective gate circuits 22.21.
23 and its control poles were connected to the output terminal of the third frequency divider 3c with a frequency division ratio of 12, and to one and the other output terminals of a flip-flop circuit 25 connected via a frequency divider 24 of 12. .

26 is a monostable multibibreak.

Thus, when the time signal continues until 12 o'clock as described above, the output terminal of the frequency divider 24 becomes "1", and at the rising edge of the signal, the monostable multi-pie break-26 is activated and the flip-flop circuit 25 is activated. Then, the gate circuit 23 is opened.

Thus, each sound source signal generator 12-1...12
The sound signal emitted from -12 is reduced to frequency A by a frequency divider 20, and a time signal one octave lower is produced.

Note that the output terminal Q of the flip-flop circuit 25.

When changing the page and connecting to each gate circuit 22, 23, the time signal is made at a low tone until 12 o'clock and at a high temperature from 13 o'clock.

You can also change the scale according to your preference.

In addition, the input pulse to the frequency divider 3 is not limited to the commercial power supply.
For example, it can be obtained from an oscillator using a crystal resonator or the like.

As described above, according to the present invention, it is possible to easily tell the time using a musical scale, and by changing the pitch, it is possible to tell the accurate time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of another embodiment. 3... Frequency divider, 5... Flip-flop circuit, 6... Shift register, 7...
・AND gate, 8...Ring counter, 9
-1...9-12...AND circuit, 1
0-1...10-12...Sound source signal groove circuit, 11-1...11-12...
Gate circuit, 20... Frequency divider, 22.23...
...Gate circuit, 24... Frequency divider, 25.
...Flip-flop circuit.

Claims (1)

[Claims] 1. A frequency divider that outputs one pulse per hour by dividing the frequency of a commercial power source or a frequency obtained from an oscillator using a crystal oscillator, etc., and a shift driven by one pulse with the output thereof. Comprising a register and a flip-flop circuit, the 797771
The output terminal of the 71 circuit and the second unit output terminal of the frequency divider are connected to a ring counter via an AND gate, and the output terminal of the last stage of the ring counter is connected to the second unit output terminal of the frequency divider.
171 circuit, each output terminal of the ring counter and the shift register in the corresponding order is connected to an AND circuit, and the output terminals of these AND circuits are connected to a plurality of sound source signal passing circuits. A scale time signal characterized by being connected to a control pole of a gate circuit. 2. A frequency divider that divides the frequency of a commercial power supply or a frequency obtained from an oscillator using a crystal oscillator, etc. and outputs one pulse per hour, and a shift register and flip-flop circuit driven by the output. , the output terminal of the flip-flop circuit and the output terminal in seconds of the frequency divider are connected to A.
It is connected to a ring counter via an ND gate, the output terminal of the last stage of the ring counter is connected to the reset terminal of the flip-flop circuit, and the corresponding output terminals of the ring counter and the shift register are ANDed. circuit, and the output terminals of these ANp circuits are connected to the control poles of gate circuits intervening in a plurality of sound source signal passing circuits, in which the output terminals of these gate circuits are connected in common and output directly. A circuit and a circuit for outputting through a frequency divider are provided, a gate circuit is interposed in each of these circuits, and the control poles of these gate circuits are connected to the output terminal of the frequency divider in units of time through the frequency divider. A scale time signal is connected to one output terminal and the other output terminal of a flip-flop circuit connected to each other.