JPS585393B2 - electronic clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece, and more particularly to an electronic timepiece having means for slowing or slowing down the time of the timepiece without slowing down or slowing down the standard signal from a time standard signal generator.

In addition to traditional balance-type mechanical watches, electric clocks, and tuning fork watches, quartz watches all use direct means to set the time using standard oscillators (ex1 balance, tuning fork, crystal oscillator, etc.) that make up the time standard signal generator. This has been done by changing this value by adding a 100% oscillator, or by inserting a capacitor etc. into a part of the oscillation circuit, thereby changing the apparent resonance point and changing the period of the time standard signal itself.

In this case, either mechanical changes are made to the standard resonator, or
Or, since a means to change the resonance point must be inserted, the stability is much worse than that of the standard resonator, and the resonant frequency of the standard resonator must be made within a frequency range that can be adjusted rapidly. I needed to leave it there.

The above-mentioned drawbacks are caused by using a speed control means in the standard signal generator. Therefore, the present invention allows the standard signal generator to be left as it is and to generate the standard signal at the frequency of the time display (seconds, minutes, hours). , day of the week, day of the week, etc.) by having a means for changing the division ratio of the frequency divider, which steps down the frequency by up to 100 degrees.

By doing this, not only the stability of the standard vibrator is maintained, but also the resonant frequency of the vibrator does not need to be made exactly as described above, so that the vibrator can be made stably.

Next, the present invention will be explained in detail.

FIG. 1 is one embodiment of the present invention.

A is a standard signal oscillator, B is a frequency divider, F is a converter,
G is a display section.

If the display section G includes an electrical element such as a liquid crystal or a light emitting diode that displays electrical signals, the converter F can be used as a frequency divider to the required time such as seconds, minutes, hours, day of the week, etc. , and a decoder for converting the signal into a signal to be displayed.

The frequency divider B may be any circuit capable of frequency division, such as a shift register decimal counter, but here, a case will be described in which a binary counter using a flip-flop is used.

Each stage of the binary counter B is set to 0 and receives a standard signal f1 from the standard oscillator A.

However, if the period t1 of the i-second signal f1 is different and is not 1 second, then exactly 1 second can be obtained as follows.

Now, let us assume that tl-1+△t1, from signal f1,
The reset pulse generator is triggered and a reset pulse R is generated.

By resetting each stage of the binary counter up to the stage through the gate circuits 01 to Gk, first, △
Add only the time corresponding to t.

(If Δt1 is negative, reset to decrease.

) After this, the standard signal f.

As a result, counting is performed, fl becomes exactly 1 second, and this operation is repeated thereafter.

Of course, fl need not be limited to 1 second.

Here, the gate circuit Gi has the function of passing the stages corresponding to Δt1 and blocking the passage of (k+1) to n stages, and also either adding or subtracting depending on the sign of Δt1. It has the function of selecting whether to reset the reset signal and setting the binary counter to 0 or 1 through which the reset signal is passed.

In this case, the reset selection is made deliberately based on the observation of fl.

Of course, what has been described above may not be applied to all of the frequency dividing stages, but only a part of them may be used.

For example, it can be applied up to the first stage.

The speed at this time is not 0 to 1/2 seconds, but is 0 to 1/2 seconds.

In addition, C-MOS-IC is used in electronic circuits,
When the frequency is high, C
-MOS-IC, and even Sigate IC are used.

This is because the diffusion capacitance at the drain is reduced, and if each MOS transistor is separated and made independent, the gate, drain, stray capacitance, etc. can be reduced, which not only improves the frequency response but also reduces the capacitance. This is because power consumption can be extremely reduced.

The advantage of the present invention is that the frequency can be adjusted over a certain range without having to adjust it to a single point, so the oscillator can be made very inexpensively, and the oscillation circuit can be modified. High stability can be obtained because there is no

Also, the higher the frequency, the more advantageous it is.

This is because 1/fo becomes very small, so for example,
If the frequency is 2 MHz, it is possible to speed up the production of io...6 sheets.

[Brief explanation of the drawing]

FIG. 1 shows one specific example of the present invention.

Claims (1)

[Claims] 1. In an electronic watch having a standard signal oscillator, a frequency divider composed of a plurality of frequency division stages, a converter, and a display section, a plurality of selections connected to each of the plurality of frequency division stages constituting the frequency divider are provided. a gate circuit and a pulse generator that triggers the selection gate circuit by the output signal of the frequency divider, and the plurality of selection gate circuits are triggered by the signal of the pulse generator to trigger the selection gate circuit. An electronic timepiece characterized in that each corresponding frequency division stage is selectively set to a predetermined lead state or delay state.