JPS60172808A - Frequency divider circuit - Google Patents

Abstract

PURPOSE:To obtain an optional non-integer frequency dividing ratio with simple circuit constitution by utilizing a 1/n frequency divider or an n-multiplier so as to attain the frequency division of n/(n+ or -1). CONSTITUTION:An external input signal (frequency fa) and an output signal (frequency fb) of a 1/n frequency divider 12 are inputted to an analog multiplier 10, from which an output signal of frequencies fa+fb and fa-fb is obtained. A band-pass filter BPF11 passes through a frequency component of, e.g., fa-fb. Said output signal is outputted to a terminal 9 and also inputted to the 1/n frequency divider 12, where the signal is subjected to 1/n frequency division and the result is fed back to the multiplier 10. The output frequency (fa-fb)/n of the frequency divider 12 is equal to said frequency (fb) inputted to the multiplier 10. Thus, the frequency of the frequency division output signal outputted from the terminal 9 is nfa(n+1). That is, an n/(n+1) frequency division circuit is constituted. In setting the passing frequency of the BPF11 as fa+fb, an n/(n-1) multiplier circuit is formed. This is attained similarly by the constitution as shown in Fig. B.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a frequency dividing circuit that divides and outputs an external input signal input at a constant repetition period.

2. Description of the Related Art A frequency divider that divides the period of an external input signal into l/n (n is an integer) and outputs the divided signal is well known. FIG. 1 is a circuit diagram showing an example of a frequency divider when n=2. That is, eight two-man powered NOR circuits 1 are connected as shown in the figure, an external input signal of a constant period is inputted from the external signal input terminal 2, and a signal obtained by inverting the external input signal iu is inputted from the inverted external signal input terminal 3. By inputting the frequency f of the external input signal
.

A signal with a frequency of 1/2 is output from the frequency divider output terminal 4.

When the number of frequency divisions is large, a frequency division circuit as shown in FIG. 2 is used. FIG. 2 shows the case where n=32, that is, l
A conventional example of a /32 frequency divider is shown.

In this case, five l/2 frequency dividers 5 are connected in series to form a l/32 frequency divider as a whole. Therefore, the frequency division ratio is 2.

It is straightforward to create a 1/n frequency divider for any n. Moreover, monolithic ICs packaged in l-chip packages are commercially available for specific frequency division ratios, and by using these ICs, large-scale circuits can be constructed extremely compactly. However, there are not so many types of frequency dividers commercially available as monolithic ICs, and most of them are of the Bakumatsu ratio of 2. When creating a frequency divider with other frequency division numbers, it is necessary to configure it by combining many l/2 frequency dividers and basic gate circuits, and as the frequency division number increases, the practical circuit configuration becomes complicated. This also increases the power consumption of the circuit and increases the failure rate.

The above-mentioned drawback becomes even more noticeable when frequency division or multiplication by a non-integer multiple is performed. For example, when constructing an m/1 (m, 1 is a mutually prime positive integer) frequency divider, the third
As shown in the figure, it is constructed by connecting an m multiplier 7 to the output of a 1/text frequency divider 6. In this case, if the 1/u frequency divider 6 cannot be configured using a commercially available IC-based frequency divider, it is necessary to newly design the l/u frequency divider 6, and the circuit configuration is It becomes even more complicated. This has the effect of narrowing the usable range of the rrr/1 frequency divider, for example, causing problems such as having to prepare multiple clock sources to operate the system. There is.

OBJECTS OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional drawbacks and to
Provides a frequency divider circuit that can divide the frequency by n/(n±1) using an n frequency divider or an n multiplier, and easily adjusts any non-integer frequency division ratio to T'l with a simple circuit configuration. There are many things.

Structure of the Invention The frequency dividing circuit of the present invention includes an analog multiplier that multiplies a column input signal input from an external input terminal by an output signal of a 1/n frequency divider described later, and an analog multiplier that multiplies the output signal of the analog q multiplier. Above 2
A band-pass filter that passes one of the sum or difference frequencies of the two signal frequencies and outputs it to the frequency divider output terminal, and the output of the band-pass filter is
/ n frequency divider and input to one input terminal of the analog multiplier, so that the external input signal is divided by n/(n-1) or n/(n+1). The analog multiplier is characterized in that it outputs a frequency-divided output signal. A band-pass filter that passes the frequency of either the sum or difference of the frequencies of the two signals, and the output of the band-pass filter is multiplied by 1 and output to the frequency dividing circuit output terminal. By feeding back the frequency dividing circuit output signal output from the n multiplier to the power input terminal of the analog multiplier, the external input signal becomes n/(n-1) or n
A frequency-divided output signal whose frequency is divided by /(n+1) can be output.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

FIG. 4 is a block diagram showing one embodiment of the present invention. That is, the external input signal input from the external input terminal I8 is inputted to one input terminal 13 of the analog multiplier lO, and inputted to the other input terminal 14 of the analog multiplier 10.
i, input the output of the 1/n frequency divider 12 described later. Assuming that the frequency of the external input signal input to the terminal 13 is fa, and the frequency of the signal input to the terminal 14 is fb, the output signal of the analog multiplier IO has a component of frequency fa + fb and a component of frequency fa - fb. is output.

Bandpass filter 11. is a filter that passes, for example, a frequency component of frequencies fa-fb among the above two frequency components. Therefore, the frequency fa-fb is output at the frequency division output terminal (-9).The signal is also input to the l/n frequency divider 12, and is divided by l/n to the analog multiplier lO. It is fed back to one input terminal 14.

Now, the output frequency of the bandpass filter 11, and thus the divided output frequency, is fa-fb, and the output frequency of the 1/n frequency divider 10 is (fa-fb)/n. This is equal to the frequency fb input to the analog multiplier 10. That is, ft+= (fa-fb)/n (holds true. From equation (1), f'b = fa / (n+'l) (2) is obtained. Therefore, from the frequency dividing circuit output terminal 9 The frequency of the divided output signal is:

(fa'-fb)=fa-fa/ (n+1)=nfa
(n+1) −·”(3) In other words, an n/(n+1) frequency dividing circuit is configured as a whole.

If the pass frequency of the band pass filter 11 is set to fa+fb, the output frequency of the 1/n frequency divider 12 is (fa
fb)/n, and fb = (fa + fb)/n, (4) holds true. Therefore, in this case, f b = fa'/ (n -1) (5).

Therefore, the frequency of the frequency divider output signal output from the frequency divider output terminal 9 is (fa + fb) = fa ffc / (n-1) = n
fa/(n-1) - (I().In other words, the circuit shown in Figure 4 is n/(n-1)
This shows that a multiplier circuit is formed. Note that the frequency dividing circuit of the present invention includes such a circuit in which the numerator is larger than the denominator.

FIG. 5 is a block diagram showing another embodiment of the invention. That is, one input terminal 13 of the analog multiplier lO
In this case, an external input signal having a frequency fa is input to the external input terminal 8, and the output signal of the frequency dividing circuit is fed back to the other input terminal '14.

The output of the analog multiplier IO is multiplied by nIAII G+'ji l5 through the bandpass f/f converter 11, and the output of the n multiplier I5 is output to the frequency dividing circuit output terminal f7. The output of the n4 multiplier 15 is also fed back to the input terminal f14 of the analog multiplier 10. The output terminal r/9 of the frequency dividing circuit is connected to the external input signal n, as described later.
The frequency divided by /(n+1) or multiplied by n/(n-1) is output.

Now, the signal input to the terminal 14 of the analog multiplier 10 (
If the frequency of the n multiplier 15 (output) is fc, the output signal of the analog multiplier 1O includes a frequency component fa ffc. For example, when the pass frequency of the band pass filter 11 is multiplied to fa-fc,...;1) The output frequency of the sphere pass filter 11 becomes fa-fc, and the output frequency fc of the n multiplier 15 becomes n (fa -fc). Therefore, the frequency fc inputted to the terminal 14 satisfies fc = n (fa - fc ) (7).

Therefore, fc = nfa/(n+1), (8). On the other hand, the frequency of the output signal from the frequency divider output terminal 9 is n (fa - fc), and by substituting equation (8) into this, n (f'a - fc ) = nfa (1 - n/ (n+1)) = n fa / (n+1) ・---(9)
Then, by the configuration shown in Fig. 5, n / '(n + i
) A frequency divider circuit is constructed.

The pass frequency of the band pass filter 11 in FIG. 5 is fa f
When set to fc, the output frequency of the bandpass filter 11 becomes fa ffc, and the output frequency of the n multiplier 15 becomes n (fa ffc). Therefore, the frequency fc input to the terminal 14 of the analog converter IO is fc = n (fa ffc) (10), that is, fc = -n fa / (n -1) (11), as shown in the above equation. The frequency has a negative sign, which means that π is added to the phase term. Now, the frequency of the output signal of the frequency dividing circuit output terminal 9 is n (fa + fc
), so by substituting equation (11) into this, n (fa + fc ) = nfa (1-n/ (n-, 1)) = -nfa /
(n-1) -...(+2) or (1).

The negative sign in equation (12) also means that π is added to the phase term, and its absolute value indicates that the circuit in Figure 5 constitutes an n/(n-1) multiplier circuit. .

Effects of the Invention As described in 1-, in the present invention, an external human input signal is multiplied by an output signal of a 1/n frequency divider described later by an analog multiplier, and the two frequency components output from the analog multiplier are is passed through a bandpass filter and outputted to the frequency divider output terminal, and the frequency divider output is 1/n.
Since the frequency is divided and fed back to one input terminal of the analog transducer, an external human input signal can be easily input to n/(n+1) or n/(n
'-1) Can be divided. Therefore, there is an advantage that a frequency dividing circuit with an arbitrary non-integer frequency dividing ratio can be easily created using a commercially available frequency divider.

Further, the output of the bandpass filter connected to the output of the analog multiplier is input to an n-multiplier, and the output of the n-multiplier is used as a frequency dividing circuit output, and is fed back to one input of the analog multiplier. Even if configured as follows, the input signal can be frequency-divided by n/(n+1) or n/(n-1). In this case, a frequency dividing circuit with an arbitrary non-integer frequency division ratio can be easily created using a commercially available multiplier or the like.

Note that the circuit configuration of the present invention is simple, and it is possible to reduce the circuit scale, reduce the failure rate, and reduce power consumption.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an example of a conventional 172 frequency divider;
FIG. 3 is a block diagram showing an example of a conventional 17n frequency divider, FIG. 3 is a block diagram showing an example of a conventional m/1 frequency divider, and FIG. 4 is a block diagram showing an embodiment of the present invention. FIG. 5 is a block diagram showing another embodiment of the present invention. In the figure, 1: 2 manual NOR circuit, 2: external signal input terminal, 3: inverted external signal input terminal, 4: frequency divider output terminal, 5: 1/2 frequency divider, 6: 1/2 frequency divider 7: m multiplier, 8: external input terminal, 9: divider circuit output terminal, lO:
Analog multiplier, 11: bandpass filter, 12:1/
n frequency divider, 13.14: analog multiplier input terminal, 1
5: n multiplier. Applicant: Nippon Telegraph and Telephone Public Corporation Agent Patent Attorney: Toshi Souga Sumita 1 [ne] ぢ12 Figure 3

Claims (2)

[Claims] (1) An analog multiplier that multiplies the external input signal input from the external input terminal and the output signal of the 1/n frequency divider described later, and the sum or difference of the frequencies of the two signals output from the analog multiplier. a bandpass filter that passes one of the frequencies and outputs it to the frequency divider output terminal; and a bandpass filter that divides the output of the bandpass filter by l/n and outputs it to one input terminal of the analog multiplier. and a 1/n frequency divider to input the external input signal.
A frequency dividing circuit that outputs a frequency-divided output signal whose frequency is divided by (n-1) or n/(n+1). (2) An analog multiplier that multiplies the external input signal input from the external input terminal by the output signal of the frequency dividing circuit described below, and either the sum or difference of the frequencies of the two signals output from the analog multiplier. A frequency dividing circuit comprising a band pass filter that passes one of the frequencies, and an n multiplier that multiplies the output of the band pass filter by n and outputs the result to a frequency dividing circuit output terminal, and outputs the output from the n multiplier. The output signal is fed back to one input terminal of the analog multiplier, so that the external input signal is n/(n-1) or n/(
n+1) A frequency dividing circuit that outputs a frequency-divided output signal.