JPS58182869A - Insulated gate field effect semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To minimize the size of an element by processing twice an Si3N4 film as an oxidation resistant mask and effectively self-aligning a gate electrode to a field SiO2 film and source, drain regions. CONSTITUTION:A gate oxidized film 2, a polysilicon film 3 and an Si3N4 film 4 are sequentially laminated on a P type silicon substrate 1, etched, and boron ions are implanted, thereby forming a channel stopper ion implanted region 5. The periphery of an Si3N4 film 4 is oxidized, an element isolating field SiO2 film 6 is grown, the Si3N4 film 4 and the film 3 are etched, and the gate electrode forming laminate is allowed to remain. Phosphorus or As ion beam 7 is emitted to implant ions to the substrate 1. The periphery of the film 4 is oxidized, an SiO2 film 10 for covering an N type source region 8 and a drain region 9 is grown, the second electrode 11 is formed, a phosphorus glass film 12 is covered, and aluminum source and drain electrode wirings 13, 14 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect semiconductor device, particularly an MIS.
FET (Metal In5lator Sem1
conductor F”1eld Effect
'l'ransistor) and its manufacturing method
It is something that

In a conventional MISFET, when forming a silicon gate structure, the source and drain regions are formed by ion implantation using the gate electrode as a mask, so that they are self-aligned (self-aligned) with the gate electrode. However, since the end of the gate electrode is generally extended over the field 5i02 film, the end of the gate electrode is
*There is no self-alignment line for the film, and a certain mask alignment allowance is required during processing, and this is the field Si0
It has been found that this is one of the obstacles to reducing the area of the g film (and therefore reducing the chip size). Further, when extending the gate electrode wiring toward the source or drain region, a large area is required for connection with other wiring.

Accordingly, it is an object of the present invention to provide self-alignment between the regions to achieve the smallest confectionery size.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

To explain the manufacturing process of the MISFET according to this embodiment, first, as shown in FIGS. 1A and 2A, gates are formed on the entire surface of the P-type silicon substrate 1 according to known semiconductor technology. Oxide film 2. A polysilicon film 3 and Si, N4 films 4 are sequentially laminated.

(An oxide film may be inserted between the polysilicon film 3 and the Si, N4 film 4.) The polysilicon film 3 is doped with impurities by phosphorus treatment or the like to lower its resistance.

Next, as shown in Figures 1B and 2B, define the confectionery area. Using a mask pattern, 5t8N, film 4, and if necessary, lower polysilicon film 3 and gate oxide film 2 are formed in the same pattern. Etching.

In this state, a P-type impurity such as boron is ion-implanted to form an ion-implanted region 5 for a channel stopper. Note that in the following drawings, the ion implantation region is omitted for the sake of simplification of explanation.

Next, as shown in FIGS. 1C and 2C, LOCO8 (Local Ox+datio
The periphery of the Si3N4 film 4 as an oxidation-resistant film is oxidized by using oxidation-resistant film 4, and a field 5in2 film 6 for element isolation is grown.

Next, as shown in FIGS. 1D and 2D, Si and N were added.

The film 4 and the polysilicon film 3 are etched in the same pattern in the width direction, and Si, N is etched in the shape of a gate electrode at an intermediate position.
, leaving a stack of the film 4 and the polysilicon film 3. and,
Ni) Ion beam 7 of impurities, e.g. phosphorus or As
is irradiated, and ions are implanted into the substrate 1 using the stacked body and the field 5iQ2 film 6 as a mask.

Next, as shown in FIGS. 1E and 2E, the periphery of the Si, N4 film 4 is oxidized by a known thermal oxidation technique, and a 5iOz film 10 covering the N+ type source region 8 and drain region 9 is grown.

Next, as shown in FIGS. 1F and 2F, after removing the gate electrode 300] Si and the N4 film 4 by etching, a second electrode 11 (for example, Mo, W, etc.) is deposited on the exposed gate electrode 3.
Refractory metal wiring such as 'l'a or in some cases A-
e arrangement) is formed by known vapor deposition and patterning. Furthermore, a phosphorus glass film 1 is formed using a known chemical vapor deposition technique.
2 is increased, it is processed by photoetching, and electrode wirings 13 and 14 are provided for the sources and drains of A, , and e in the contact holes formed.

If it is desired to simplify the process, contact holes may be formed in the 5i02 film 10 and metal wiring may be provided in the source, gate, and drain regions without depositing the phosphorus glass film 12.

In the MISFET created in this way, the width of the gate electrode 3 (almost the same as the channel width) is the width of the field 5.
The width of the field 5iO1 film 6 and the source region 8 . A self-alignment line is formed with respect to the drain region 9.

In particular, compared to the conventional MISFET ET, the end of the gate electrode 3 (in the channel width direction) is connected to the field 5iQ2 film 6.
- Since it does not extend to the edge of the gate electrode 3 and coincides with the edge of the confectionery area, there is no need for alignment margin when aligning the mask to determine the edge of the gate electrode 3, and the isolation area of the transistor (field 5in2 film 6) The area can be minimized and the template size can be reduced. Moreover, the second electrode wiring 11 can be provided relatively freely, and the gate electrode 3
Since the contact can be made directly above the confectionery, a large area is not required for the connection, which also contributes to reducing the size of the confectionery.

Furthermore, regarding the manufacturing process, as mentioned above, by processing the Si8N4 film as an oxidation-resistant mask twice, it is possible to reliably realize a self-alignment between the gate electrode, the field 5i02 film, and the source and drain regions. This is a typical characteristic.

The embodiments described above can be further modified based on the technical idea of the present invention, for example, the element pattern, conductivity type of each semiconductor region, used impurity range, etc. may be changed. Furthermore, the MISFET 1'' according to the present invention can be applied to various types of devices such as highly integrated memories.

[Brief explanation of the drawing]

The drawings show embodiments of the present invention, and include Figures 1A to 1A.
FIG. 1F is each cross-sectional view showing the MISFET in the manufacturing process 111, and FIGS. 2A to 2F are plan views corresponding to FIGS.
The pongee is omitted. ). In addition, in the symbols shown in the drawings, 3...polysilicon film or gate electrode, 4...Sl, N4 film, 6...
Field SiQ! Films 8 and 9: Source or drain region, 10: SiQ, film, 11: Second electrode wiring. 1st AID Figure 2A

Claims (1)

[Claims] 1. A gate electrode is provided in a region surrounded by the field oxide film in the width direction of this region, and a gate electrode is provided in the region surrounded by the gate electrode and the field oxide film. An insulated gate field effect semiconductor device, wherein source and drain regions are respectively formed, and the gate electrode, the field oxide film, and the source and drain regions are formed in self-alignment with each other. 2. A gate insulating film, a gate electrode material 1, and an oxidation-resistant mask layer are sequentially laminated over the entire surface of the semiconductor substrate, and then a small amount of the oxidation-resistant mask layer is processed to leave an island shape; Next, a field oxide film is grown around this island-shaped oxidation-resistant mask layer by oxidation treatment, and then the island-shaped oxidation-resistant mask layer and the lower gate electrode material layer are processed into the same pattern to form a stack of gate electrode shapes. A method for manufacturing an insulated gate field effect semiconductor device, characterized in that impurities for forming a source and drain region g4 are introduced into the semiconductor substrate using the stacked body and the field oxide film as a mask.