JPS58182866A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a bipolar semiconductor device which has high reliability without production of product which affects the advarse influence to the emitter and base junction as PtxAsy even when As is used as an impurity by converting an undoped semiconductor film into a metal silicide layer. CONSTITUTION:An N<+> type buried layer 22 is formed in a P<-> type silicon substrate 21, an N type epitaxial layer is grown, a thermal oxidation is performed, an isolated oxidized film 25 is buried, and an N type semiconductor layer 26 is formed. A thermally oxidized film 27 is formed, B<+> ions are implanted to form a P type base region 29. Holes 301, 302 are formed, As<+> ions are implanted, thereby forming an N<+> type emitter region 31 an dan N<+> type collector contact region 32. Non-doped polycrystalline silicon film patterns 331, 332 are formed, a window 34 is formed, Pt is deposited, heat treatment is then performed, and converted into PtSi layers 351, 352, PtSi layer 36. Aluminum is deposited to form an emitter electrode 371, a base electrode 372, collector electrode 373.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an emitter region suitable for a high-speed bipolar device.

[Technical background of the invention and its problems]

Bipolar devices can be interconnected by applying shallow junction formation techniques and oxide isolation techniques. Conventionally, a bipolar NPN transistor, for example, shown in FIG. 1, to which these techniques are applied, has been manufactured by the following method.

First, after forming an N+ type buried region 2 partially on the surface of a P- type silicon substrate 1, an N type epitaxial layer is grown on the entire surface. Next, an isolation oxide film 3 reaching the N+ type buried region 2 is buried in the N type epitaxial layer 1- by a normal selective oxidation method, and an M3-shaped N type semiconductor layer is separated by this isolation oxide film 3. (Collector region) 4 is formed. After forming a wide thermal oxide film 5 on the surface of this N-type semiconductor layer (collector region) 4, using a photorenost layer (not shown) as a mask, the N-type semiconductor layer (
A P-type base region 6 is formed by ion-implanting P-type impurities into a part of the collector region 4. After removing the photorenost glossy turn by poking, the P of the thermal oxide film 5 is removed.
Opening portions 71*71 are selectively formed in a portion corresponding to the mold base region 6 and a portion corresponding to the collector region 4. Next, for example, an As-doped polycrystalline silicon film is deposited over the entire surface and patterned to form at least the openings 7, . 7. Then, the As-doped polycrystalline silicon film turns 8I and 8□ are formed. Continuing, these As-doped polycrystalline silicon film quantity turns 8. ．． 8. A shallow N+ type emitter region 9 and an N+ type collector contact region 10 are formed by thermal diffusion using as a diffusion source. Subsequently, an opening window 11 is selectively formed in a portion of the thermal oxide film 6 corresponding to the P-type base region 6 . Next, after depositing wiring metal on all ■,
4 turns and emitter 11 pole 121, base electrode 1
2. Collector electrode 12. to form bipolar NPN
Transistor f: Manufactured.

In the above conventional method, As-doped polycrystalline silicon film 9 main 8. serves not only as a source of diffusion of impurities, but also to prevent the wiring metal from being in contact with the emitter 9 paste junction and reducing the withstand voltage.

However, in the bipolar transistor to which the above-mentioned oxide film isolation technology is applied, the thick isolation oxide film 3 is
Since the semiconductor layer is forcibly buried in the type epitaxial layer, defects are likely to occur in the vicinity of the isolation oxide film 3 in the N-type semiconductor layer (collector region) 4. When the N+ type emitter region 9 is formed in the N type semiconductor layer ('collector region) 4 in which the defect has occurred by diffusing N type impurities into the IcPIc− source region 6 by thermal diffusion as in the conventional method described above, an N+ type emitter region 9 is formed. It is known that the diffusion length of impurities increases at locations where defects exist.Especially, in the case of fC using Aa as the N-type impurity, As diffusion by thermal diffusion is extremely sensitive to the presence of defects, etc. Therefore, its diffusion length is significantly increased.
As shown in the figure, as a result of the deep formation of the N+ type emitter region 9 due to the above-mentioned abnormal diffusion near the isolation oxide film 3, the width of the PM base region 6 becomes narrower and the transistor breakdown voltage (
This has the disadvantage that VCICQ) decreases.

Furthermore, when forming a Schottky diode together with a transistor, or when reducing emitter series resistance, for example, the As-doped polycrystalline silicon film on the N-type upper region 9 and the turn 8□ are made of metal silicide. (e.g. pts to pigeon). However, when the A8 doped polycrystalline silicon film 5-8I is silicided using the above conventional method, % Vi! Problems such as a decrease in IIQ and shorting of the emitter-base junction may occur. The cause of this is not fully understood, but the grain bound of polycrystalline silicon
It is thought that this is because PtxAay, which is generated by the reaction between As and pt precipitated in the ary, has the property of being easily diffused and diffuses to a considerable extent into the N+ type upper vine region 9. .

[Purpose of the invention]

The present invention applies oxide film separation technology and shallow junction technology^
The object of the present invention is to provide a method for manufacturing a bipolar conductor device that can achieve reliability.

[Summary of the invention]

The present invention includes a step of forming an island-shaped first conductor layer separated by a thick oxide film on a conductor substrate, and selectively forming an impurity region of a second conductor layer on the conductor layer. 1 glue is formed on the conductor layer and the 2nd insulating film is formed on the conductor layer.
Impurity of conductivity type −6= A step of selectively pre-forming an opening in a portion corresponding to the material region, and impurity region of the first conductivity type exposed from the opening by ion implantation into the impurity region of the second conductivity type. a step of forming an impurity region; and a step of forming an impurity region to support at least the opening.
This method is characterized by comprising a step of depositing a metal conductor film and a step of converting a nuclear conductor group into gold bullion silicide 1-.

In the method of the present invention, the impurity region of the first conductivity type is
After ion-implanting impurities of the first conductivity type into the impurity region of the conductivity type, crystal defects caused by the ion implantation are removed, and the impurity'
? r:fit is formed by moving it to the dislocation neck and subjecting it to a safe minimum heat treatment to make it electrically active (E), so even if AS is used as an impurity, no abnormality will occur near the thick isolation oxide film. This does not cause a decrease in V.ico due to diffusion. ``Since the unconducted conductive film deposited on the first conductivity type impurity region is converted into a metal silicide layer, There is no generation of products that have negative effects on the emitter-base junction.LFC allows for a high-speed and highly reliable bibo-conductor device to be produced. can be built.

[Embodiments of the invention]

Hereinafter, an embodiment in which the present invention is applied to a bipolar NPN (NPN) lannostar will be described with reference to FIGS. 3(a) to 3(g).

Embodiment First, an N+ type buried region 22 with a resistivity of ρ8-20-30ΩA is formed on a P− type silicon substrate 21 with a specific resistance of 2 to 6Ω. Specific resistance 0.2~
An N-type epitaxial layer of 0.4Ω-(1) and 1.5 μm thick was grown. Next, a buffer oxide film pattern 23 with a thickness of 500X and a silicon nitride film pattern 24 with a thickness of 100X are sequentially formed on the surface of this N-type epitaxial layer. After removing the mold epitaxial layer by etching to a predetermined depth, the silicon nitride film pattern 24 is removed.
By performing thermal oxidation treatment using as a mask, an N1 oxide film 25 with a thickness of 1.6 μm is formed on the N-type epitaxial layer.
Immediately after this is buried, an island-shaped N-type collector layer (collector region) 26 separated by this isolation oxide film 25 is formed fc (as shown in FIG. 3(a)).

Next, after the silicon nitride film pattern 25 and the Hi-Huffer oxide film pattern 24 are sequentially etched away, the N-type medium 414. Layer (collector region) 26 on the surface with a thickness of 20
A thermal oxide film 27 of 00J is formed, fc8 is attached, and the thickness is 1
Using the 0 μm photorenost square turn 28 as a mask, a part of the N-type medium conductor layer (collector region) 26 is selectively irradiated with B0 at an energy of 85 keV and a dose of -jllX10.
Ion implantation was performed under cIn conditions (as shown in FIG. 3(b)).

Next, after removing the photoresist turn 28, heat treatment was performed at 1000° C. for 100 minutes in a nitrogen atmosphere to form a P-type base region 29 with ρa = 600Ω/hole and a depth of 0.5 μm (Fig. #13). ,) as shown).

Next, portions of the thermal oxide film 27 corresponding to the P-type base=9− region 29 and the N-type collector region 26 are selectively etched away to form openings so,
, so, and 'fco', and then these openings so
, , the P type base region 29 exposed from so□ and N
88 to the mold collector region 26 and energy 60 ke
Ion implantation was performed under the conditions of V and a dose of lXl0 cm (as shown in FIG. 3(d)).

Next, heat treatment was performed at 1000°C for 30 minutes in a nitrogen atmosphere to form an N+fix+ of ρB-20Ω/hole and a depth of 0.3μm.
A collector region 31 and an N++ collector contact region 32 were formed. Subsequently, a non-dosed polycrystalline silicon film with a thickness of 500× is deposited on the entire surface, and then gloss-turned to form the openings SO.

301. A non-done polycrystalline silicon film pattern 33. +33t was formed. Subsequently, a portion of the thermal oxide film 27 corresponding to the P-type base region 29 was selectively etched away to form an opening window 34 (as shown in FIG. 3).

Next, PT with a thickness of 600× is deposited on the entire surface, and heat treatment is performed at 550° C. for 15 minutes in a 10-nitrogen atmosphere to form the non-done polycrystalline silicon film pattern 3 on the N++ emitter region 31 and the N++ collector contact region 32.
3. ．． 33. All ptst layers 35. Converted to +352. At the same time, the surface of the P-type base inertia 29 exposed through the aperture window 34 was also converted into a Pt81 layer 36. Subsequently, unreacted pt (c-) was removed by aqua regia treatment (as shown in FIG. 3(f)).

Next, Atf was vapor-deposited on the entire surface, and after fc, it was turned to form an electrode 378, a base electrode 378, and a collector electrode 373, thereby manufacturing a bipolar NPN transistor (as shown in FIG. 3(g)). .

However, according to the manufacturing method of the above I-P embodiment, as shown in FIG.
i) In the process shown in the figure, Am is doped by ion implantation, and in the process shown in FIG. As■. A shallow N++ emitter region 31 can be formed without causing an 8o drop. In addition, the and-node polycrystalline silicon film pattern 331 deposited to cover the opening 30K in the step shown in FIG.
(F) Since the low-resistance PTS is converted into the layer 35 in the process shown in FIG. Therefore, it is possible to manufacture a bipolar NPN trannostar with high speed and high reliability. In addition, P above the vine area 3
tS 1 layer 35. Because it has a low resistance, it can be used as a programmable read-only tube memory (FROM) as shown in Figure 4.
) can be effectively used as foods.

Incidentally, when using the unand-button multi-MIj & silicon film pattern 331 in the step shown in FIG. 3(e) as in the above embodiment, the ptst layer 35.
When converting to , only the vicinity of the surface of the and/dono polycrystalline silicon film pattern 33 □ is silicided, and there is a possibility that high-resistance polycrystalline silicon remains. Add As to an extent that does not adversely affect the emitter-base junction.

A polycrystalline silicon film/f-turn doped with an impurity such as P may also be used.

〔Effect of the invention〕

According to the present invention, it is possible to provide a method for manufacturing a conductor device such as a bipolar transistor that can achieve high speed and high reliability.

[Brief explanation of the drawing]

Figures 1 and 2 are cross-sectional views showing a bipolar NPN) lannostar manufactured by a conventional method, and Figures 3 (,)~
(g) is a cross-sectional view showing the manufacturing method of a bipolar NPN) lansoster according to an embodiment of the present invention in the order of steps, and FIG. 4 is a circuit diagram showing a programmable read-only memory. 21... P- type silicon substrate, 22... N+ type buried region 23... Banner oxidation [pattern, 24...
Silicon nitride M/f turn, 25 minutes 1! lII oxide film, 26...N-type medium conductor Ni (collector region), 2
7... Thermal oxide film, 28... Photoresist pattern,
29...P type base region, 30□, 30R...opening portion, 3 -...N++ emitter region, 32...N
+ type collector 13- Jin tact area, 33,733. ...Non-doped polycrystalline silicon film/yaturn, 34...Opening window, 35,
, ． 96. + 36-Pt81 No-1, s7. -・-x Mitter 11L &, 37 g
...Base ti'fLJ7g ...Collector electrode. Applicant's agent Patent attorney Takehiko Suzue-14-' Figure 3 B÷ Figure 3 7 Figure 4-296-

Claims (3)

[Claims] (1) A step of forming an island-like fourteenth dragon-shaped semi-quadruple layer separated by a thick oxide film on a semiconductor substrate, and selectively applying a second conductive layer to the semiconductor layer. 8! ! forming an aperture 11t in a selected shape in a portion of an insulating film formed on the semiconductor layer corresponding to the second conductivity type impurity region; forming a first conductivity type impurity region by ion implantation in the second conductivity type impurity region exposed from the second conductivity type impurity region; depositing an and-node semiconductor film so as to cover at least the opening;
A method for manufacturing a semiconductor device, comprising the step of converting the semiconductor layer into a metal silicide layer. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the impurity is arsenic. (3) The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer is made of polycrystalline silicon. (4) The method for manufacturing a semiconductor device according to item 1, characterized in that the metal silicide J- is formed as a fuse of a programmable lead-only ψ memory.