JPH0222544B2 - - Google Patents
Info
- Publication number
- JPH0222544B2 JPH0222544B2 JP55053350A JP5335080A JPH0222544B2 JP H0222544 B2 JPH0222544 B2 JP H0222544B2 JP 55053350 A JP55053350 A JP 55053350A JP 5335080 A JP5335080 A JP 5335080A JP H0222544 B2 JPH0222544 B2 JP H0222544B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- diffusion layer
- conductor pattern
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 49
- 229910052710 silicon Inorganic materials 0.000 claims description 49
- 239000010703 silicon Substances 0.000 claims description 49
- 239000004065 semiconductor Substances 0.000 claims description 47
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 46
- 239000000758 substrate Substances 0.000 claims description 39
- 239000004020 conductor Substances 0.000 claims description 38
- 238000009792 diffusion process Methods 0.000 claims description 28
- 230000003647 oxidation Effects 0.000 claims description 23
- 238000007254 oxidation reaction Methods 0.000 claims description 23
- 229910021332 silicide Inorganic materials 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 238000002844 melting Methods 0.000 claims description 21
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 21
- 239000012535 impurity Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 230000008018 melting Effects 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 9
- 238000000605 extraction Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 5
- 239000000470 constituent Substances 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims 1
- 229910016006 MoSi Inorganic materials 0.000 description 21
- 229910052581 Si3N4 Inorganic materials 0.000 description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 12
- 229910004298 SiO 2 Inorganic materials 0.000 description 11
- 230000010354 integration Effects 0.000 description 7
- 229910052785 arsenic Inorganic materials 0.000 description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 5
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018182 Al—Cu Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- 229910020968 MoSi2 Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910018594 Si-Cu Inorganic materials 0.000 description 1
- 229910008465 Si—Cu Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
- H01L21/8226—Bipolar technology comprising merged transistor logic or integrated injection logic
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体集積回路の製造方法に関し、特
にI2L素子を有するバイポーラ型の集積回路の製
造方法に係る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit, and particularly to a method for manufacturing a bipolar integrated circuit having an I 2 L element.
I2L(Integrated Injection Logic)は逆構造形
のバーテイカルトランジスタ(例えばnpnトラン
ジスタ)と、このトランジスタのベースをコレク
タとする上記トランジスタとは相補形のラテラル
トランジスタ(pnpトランジスタ)との複合構造
をもつ論理素子である。かかるI2Lはラテラルト
ランジスタが前記逆構造のバーテイカルトランジ
スタのベースに電荷を注入するインジエクタとし
て作用し、逆構造のバーテイカルトランジスタが
インバータとして動作するものである。このた
め、I2Lは論理振幅が小さく、高速かつ低消費電
力の動作が可能な素子として近年注目されてい
る。また、I2Lはバーテイカルトランジスタとラ
テラルトランジスタの素子間分離が不要であるこ
とから、集積度が高く、大規模集積回路の応用に
適している。更に、I2Lはバイポーラプロセス技
術であることから、同一チツプ上に容易に他のバ
イポーラ回路、例えばリニア回路やECL
(Emitter、Coupled Logic)を共存させることが
でき、複合機能集積回路を実現できる。 I 2 L (Integrated Injection Logic) has a composite structure of an inverted vertical transistor (e.g. npn transistor) and a complementary lateral transistor (pnp transistor) whose collector is the base of this transistor. It is a logic element. In such I 2 L, the lateral transistor acts as an injector that injects charge into the base of the vertical transistor with the reverse structure, and the vertical transistor with the reverse structure operates as an inverter. For this reason, I 2 L has attracted attention in recent years as an element that has a small logic amplitude and can operate at high speed and with low power consumption. Furthermore, since I 2 L does not require isolation between vertical transistors and lateral transistors, it has a high degree of integration and is suitable for large-scale integrated circuit applications. Furthermore, since I 2 L is a bipolar process technology, it is easy to integrate other bipolar circuits, such as linear circuits and ECL circuits, on the same chip.
(Emitter, Coupled Logic) can coexist, making it possible to realize multifunctional integrated circuits.
ところで、上述したI2Lを高速動作をさせるた
めに多くの研究がなされており、スイツチングト
ランジスタのエミツタ及びベース領域に蓄積され
る少数キヤリアを前段のスイツチングトランジス
タがシンクする時間、つまり蓄積時間を小さくす
ることが重要であることが、例えばIEEE
Journal of Solid−State Circuits、Vol、SC−
14、No.2、April 1979、327〜336に記載されてい
る。少数キヤリアの蓄積を少なくするためには、
エピタキシヤル半導体層及びエミツタ層の濃度プ
ロフアイルを最適化するに加え、少数キヤリアの
蓄積される領域を必要最小限にすることが効果的
である。このような観点から従来、次に示す方法
によりI2Lを製造することが考えられている。す
なわち、p型シリコン基板1に選択的にn+埋込
層2を形成し、同基板1上にn型エピタキシヤル
層3を成長された後、素子分離のための厚いフイ
ールド酸化膜4を選択酸化技術により形成する。
つづいて素子形成領域上にCVD法、写真蝕刻法
により選択的にSiO2膜5を覆つた後、このSiO2
膜5をマスクとしてボロンの熱拡散を施してp型
のベース領域6及びインジエクタ7を形成する
(第1図a図示)。次いで、全面にn型不純物であ
る砒素をドープした多結晶シリコン膜を堆積し、
更にCVD−SiO2膜を堆積した後CVD−SiO2膜を
パターニングしてCVD−SiO2パターン8a,8
bを形成し、これをマスクとして多結晶シリコン
膜を選択エツチングしてコレクタ領域形成予定部
上に多結晶シリコンパターン9a,9bを形成す
る(第1図b図示)。ひきつづき、高温熱酸化処
理を施してCVD−SiO2パターン8a,8bが設
けられた多結晶シリコンパターン9a,9bの周
囲に厚いシリコン熱酸化膜10及び露出するベー
ス領域6、インジエクタ7上に薄いシリコン熱酸
化膜(図示せず)を成長させると共に、砒素をド
ープした多結晶シリコンパターン9a,9bから
砒素をp型のベース領域6に拡散してn+型のコ
レクタ領域11a,11bを形成する。その後、
前記薄いシリコン熱酸化膜をエツチング除去して
CVD−SiO2パターン8a,8b及び厚いシリコ
ン熱酸化膜10で絶縁された多結晶シリコンパタ
ーンをコレクタ取出し電極12a,12bとした
後、全面にAl膜を堆積し、フイールド酸化膜4
及びSiO2膜5上でパターニングしてベース取出
しAl電極13、インジエクタ取出しAl電極14
を形成してI2Lを含む集積回路を製造する(第1
図c図示)。 By the way, a lot of research has been done to make the above-mentioned I 2 L operate at high speed. For example, IEEE
Journal of Solid−State Circuits, Vol, SC−
14, No. 2, April 1979, 327-336. In order to reduce the accumulation of minority carriers,
In addition to optimizing the concentration profile of the epitaxial semiconductor layer and the emitter layer, it is effective to minimize the area where minority carriers are accumulated. From this point of view, it has been conventionally considered to produce I 2 L by the following method. That is, after selectively forming an n + buried layer 2 on a p-type silicon substrate 1 and growing an n-type epitaxial layer 3 on the same substrate 1, a thick field oxide film 4 for device isolation is selected. Formed by oxidation technology.
Subsequently, after selectively covering the SiO 2 film 5 on the element forming region by CVD method or photolithography method, this SiO 2 film 5 is
Boron is thermally diffused using the film 5 as a mask to form a p-type base region 6 and an injector 7 (as shown in FIG. 1A). Next, a polycrystalline silicon film doped with arsenic, which is an n-type impurity, is deposited on the entire surface.
After further depositing a CVD-SiO 2 film, the CVD-SiO 2 film is patterned to form CVD-SiO 2 patterns 8a, 8.
b is formed, and using this as a mask, the polycrystalline silicon film is selectively etched to form polycrystalline silicon patterns 9a and 9b on the portion where the collector region is to be formed (as shown in FIG. 1b). Subsequently, a thick silicon thermal oxide film 10 is formed around the polycrystalline silicon patterns 9a and 9b on which CVD-SiO 2 patterns 8a and 8b are provided by high-temperature thermal oxidation treatment, and a thin silicon film is formed on the exposed base region 6 and injector 7. A thermal oxide film (not shown) is grown, and arsenic is diffused from arsenic-doped polycrystalline silicon patterns 9a, 9b into p-type base region 6 to form n + -type collector regions 11a, 11b. after that,
Etching and removing the thin silicon thermal oxide film
After using the CVD-SiO 2 patterns 8a, 8b and the polycrystalline silicon pattern insulated by the thick silicon thermal oxide film 10 as the collector lead-out electrodes 12a, 12b, an Al film is deposited on the entire surface, and the field oxide film 4 is formed.
And by patterning on the SiO 2 film 5, a base lead-out Al electrode 13 and an injector lead-out Al electrode 14 are formed.
to form an integrated circuit containing I 2 L (first step
Figure c).
上述したI2Lを含む集積回路の製造においては
ベースコンタクトホールを砒素ドープ多結晶シリ
コンのコレクタ取出し電極12a,12bに対し
て自己整合的に開孔でき、ベース取出し電極13
をベース領域6に対して広い面積で接触できる。
しかも、コレクタ領域11a,11bの面積に比
較してベース領域6の面積を小さくできる。した
がつて得られたI2Lは高速化できると共に、コレ
クタ、ベースの面積比(SC/SB)比が大きくなる
ことにより電流増幅率(hFE)の向上を達成でき、
更には集積度を向上できる。しかしながら、かか
る従来法にあつてはコレクタ取出し電極12a,
12bが多結晶シリコンからなるため、そのシー
ト抵抗はAl電極に比べて極端に高くなる。例え
ばコレクタ取出し電極が厚さ3000Åの砒素ドープ
多結晶シリコンからなる場合、シート抵抗は
100Ω/□〜200Ω/□程度と高くなる。したがつ
て、I2Lは高電流領域(数100μA/gate以上)で
は動作せず、しかも回路設計上の制約も受ける。
このため、多結晶シリコンからなるコレクタ電極
を途中でAl配線と結線しなければならず、大巾
な集積度の向上を望めなくなる。 In manufacturing an integrated circuit including the above-mentioned I 2 L, the base contact hole can be opened in a self-aligned manner with respect to the collector lead-out electrodes 12a and 12b of arsenic-doped polycrystalline silicon,
can be brought into contact with the base region 6 over a wide area.
Furthermore, the area of the base region 6 can be made smaller than the area of the collector regions 11a and 11b. Therefore, the speed of the obtained I 2 L can be increased, and the current amplification factor (h FE ) can be improved by increasing the area ratio (S C /S B ) of the collector and the base.
Furthermore, the degree of integration can be improved. However, in such a conventional method, the collector extraction electrode 12a,
Since 12b is made of polycrystalline silicon, its sheet resistance is extremely high compared to the Al electrode. For example, if the collector lead electrode is made of arsenic-doped polycrystalline silicon with a thickness of 3000 Å, the sheet resistance is
It will be as high as 100Ω/□ to 200Ω/□. Therefore, I 2 L does not operate in a high current region (several 100 μA/gate or more) and is also subject to circuit design constraints.
For this reason, the collector electrode made of polycrystalline silicon must be connected to the Al wiring midway, making it impossible to expect a significant improvement in the degree of integration.
これに対し、本発明者は以下に説明する研究成
果により、高集積度と高速動作化との両方を達成
した半導体集積回路の製造方法を見い出した。 In response, the inventor of the present invention has discovered a method of manufacturing a semiconductor integrated circuit that achieves both high integration and high-speed operation based on the research results described below.
すなわち、高融点金属硅化物は多結晶シリコン
膜より低抵抗であることに着目し、例えば厚さ
3000Åのモリブデンシリサイド膜(MoSi2膜)を
アニーリングすると、第2図に示すようにMo2Si
膜の抵抗変化特性曲線S1が得られる。この第2図
より、低温アニール(500℃程度)においても
MoSi2膜の抵抗は40Ω程度、更に高温アニール
(1000℃程度)を施せば2Ω程度となり、同膜厚の
多結晶シリコン(100〜200Ω/□)に比べて極端
に低抵抗ができることがわかつた。 In other words, focusing on the fact that high melting point metal silicide has lower resistance than polycrystalline silicon film, for example,
When a 3000 Å thick molybdenum silicide film (MoSi 2 film) is annealed, it becomes Mo 2 Si as shown in Figure 2.
A resistance change characteristic curve S 1 of the membrane is obtained. From this figure 2, even in low temperature annealing (approximately 500℃)
The resistance of the MoSi 2 film is approximately 40Ω, and if it is further annealed at a high temperature (approximately 1000℃), it becomes approximately 2Ω, which is an extremely low resistance compared to polycrystalline silicon of the same thickness (100 to 200Ω/□). .
しかるに、上記高融点金属硅化物膜、例えば厚
さ3000ÅのMoSi2膜をシリコン基板のn+拡散層
(抵抗10Ω/□)上に直接接触させて設け、
MoSi2膜を低抵抗化するための熱処理を施して電
極配線を形成することを試みた。しかしながら、
こうした状態での熱処理によるシリコン基板−
MoSi2膜のコンタクト抵抗を調べると、第3図の
ようなMoSi2膜のコンタクト抵抗変化特性曲線S2
となり、高温処理を施した場合、コンタクト抵抗
は異常に増大し、最後にはシヨツトキー化して拡
散層の取出し配線等として機能できなくなる。 However, the above-mentioned high melting point metal silicide film, for example, a MoSi 2 film with a thickness of 3000 Å, is provided in direct contact on the n + diffusion layer (resistance 10 Ω/□) of a silicon substrate,
We attempted to form electrode wiring by applying heat treatment to the MoSi 2 film to lower its resistance. however,
Silicon substrates subjected to heat treatment under these conditions
When we examine the contact resistance of the MoSi 2 film, we find that the contact resistance change characteristic curve S 2 of the MoSi 2 film is shown in Figure 3.
Therefore, when high-temperature treatment is performed, the contact resistance increases abnormally, and eventually it becomes a shot key and cannot function as a lead-out wiring for the diffusion layer.
そこで、本発明者は上記問題点を踏えて鋭意研
究し、第1導電型(例えばp型)のシリコン基板
上に第2導電型(n型)の高濃度不純物を含む多
結晶シリコン膜を直接堆積し、更にこの上に高融
点金属硅化物膜(例えば厚さ3000ÅのMoSi2膜)
を堆積した後、MoSi2膜の低抵抗化のための熱処
理を施した。その結果、同第3図に示す如くシリ
コン基板に対するMoSi2/n+pol−Siのコンタク
ト抵抗変化特性曲線Fが得られ、高温処理を施し
た場合でも高濃度不純物を含む多結晶シリコンを
介在させることにより、基板に対するコンタクト
抵抗の増大を防止できることがわかつた。こうし
たことにより第1導電型のシリコン基板上に第2
導電型の高濃度不純物を含む高融点金属硅化物膜
を堆積し、これらをパターニングした後、高温熱
処理(例えば1000℃程度)を施すことによつてシ
リコン基板に対するコンタクト抵抗の増大を招く
ことなく(第3図のFより10μm□で1Ω程度)、
高融点金属硅化物膜の低抵抗化(第2図のS1より
4Ω程度)を達成でき、ひいては基板との低抵抗
接触が確保され、シート抵抗の小さい二層構造の
電極配線を形成し得ることを究明した。しかも、
この高温熱酸化処理により第2導電型の高濃度不
純物を含む多結晶シリコンから第2導電型の不純
物が第1導電型のシリコン基板に、熱拡散して所
望の第2導電型の拡散層を形成できた。 Therefore, the inventors of the present invention conducted extensive research based on the above problems, and directly deposited a polycrystalline silicon film containing high concentration impurities of a second conductivity type (n type) on a silicon substrate of a first conductivity type (for example, p type). A high melting point metal silicide film (e.g. 3000 Å thick MoSi 2 film) is deposited on top of this.
After depositing the MoSi 2 film, heat treatment was performed to lower the resistance of the MoSi 2 film. As a result, as shown in Fig. 3, a contact resistance change characteristic curve F of MoSi 2 /n + pol-Si with respect to a silicon substrate was obtained, and even when high-temperature treatment is performed, polycrystalline silicon containing high concentration impurities is present. It has been found that this makes it possible to prevent an increase in contact resistance to the substrate. Due to this, the second conductivity type is placed on the silicon substrate of the first conductivity type.
After depositing a high-melting point metal silicide film containing conductive type impurities at a high concentration and patterning these, high-temperature heat treatment (for example, around 1000°C) can be performed without increasing the contact resistance to the silicon substrate ( (approximately 1Ω at 10μm□ from F in Figure 3),
Lower resistance of high melting point metal silicide film (from S 1 in Figure 2)
We have found that it is possible to achieve a resistance of approximately 4Ω), thereby ensuring low resistance contact with the substrate, and forming a two-layer structure of electrode wiring with low sheet resistance. Moreover,
Through this high-temperature thermal oxidation treatment, impurities of the second conductivity type are thermally diffused from the polycrystalline silicon containing highly concentrated impurities of the second conductivity type into the silicon substrate of the first conductivity type to form a desired diffusion layer of the second conductivity type. I was able to form it.
また、高融点金属硅化物は酸化レートが通常の
アンドープ多結晶シリコンと同等であることか
ら、第2導電型の不純物を含む多結晶シリコン膜
上に高融点金属硅化物膜を堆積し、これらをパタ
ーニングした後、低抵抗化のための高温熱処理を
酸化性雰囲気中で行なうことによつて、高融点金
属硅化物の低抵抗と共に、多結晶シリコンと高融
点金属硅化物の二層構造の周囲にシリコン熱酸化
膜を成長でき、該二層構造の電極配線上を横切る
別の電極配線に対して絶縁化できることを究明し
た。 In addition, since the oxidation rate of high-melting point metal silicide is equivalent to that of ordinary undoped polycrystalline silicon, a high-melting point metal silicide film is deposited on a polycrystalline silicon film containing impurities of the second conductivity type. After patterning, by performing high-temperature heat treatment in an oxidizing atmosphere to lower the resistance, the resistance of the high-melting point metal silicide is low, and the surroundings of the two-layer structure of polycrystalline silicon and high-melting point metal silicide are We have discovered that it is possible to grow a silicon thermal oxide film and to insulate the two-layered electrode wiring from another electrode wiring that crosses over it.
しかして、本発明者は上述した知見にもとづき
第1導電型の半導体基板等に第2導電型の不純物
を含む多結晶シリコン膜及び高融点金属硅化物膜
を順次堆積し、これら膜をパターニングして二層
構造の導電体パターンを形成した後、高温熱酸化
処理を施すことによつて、多結晶シリコン膜か
らの第2導電型の不純物拡散により基板等に第2
導電型の拡散層を形成でき、この拡散層と導電
体パターンとのコンタクト抵抗の増大を招くこと
なく高融点金属硅化物の低抵抗、ひいては導電体
パターンの低抵抗化を達成でき、導電体パター
ン周囲にシリコン熱酸化膜を、露出する半導体基
板等部分にもシリコン熱酸化膜を、成長できた。
しかるに、露出する半導体基板部分のシリコン熱
酸化膜を選択的に除去した後、電極配線材料層を
堆積することによつて、第2導電型の拡散層と低
抵抗接触し、かつシート抵抗の小さい二層構造の
電極配線を形成できると共に、この電極配線に対
してその周囲のシリコン熱酸化膜で主に絶縁され
た別の電極配線を形成でき、著しく短縮された工
程で高集積度と高速動作化との両方を達成した半
導体集積回路を製造し得る方法を見い出した。 Therefore, based on the above-mentioned knowledge, the present inventor sequentially deposited a polycrystalline silicon film containing impurities of a second conductivity type and a high melting point metal silicide film on a semiconductor substrate of a first conductivity type, and patterned these films. After forming a conductor pattern with a two-layer structure, a high-temperature thermal oxidation treatment is performed to diffuse a second conductivity type impurity from the polycrystalline silicon film to form a second conductive pattern on the substrate, etc.
It is possible to form a conductive type diffusion layer, and it is possible to achieve low resistance of the high-melting point metal silicide, and thus of the conductor pattern, without increasing the contact resistance between this diffusion layer and the conductor pattern. We were able to grow a silicon thermal oxide film around the periphery and also on the exposed parts of the semiconductor substrate.
However, by selectively removing the silicon thermal oxide film on the exposed portion of the semiconductor substrate and then depositing an electrode wiring material layer, it is possible to form a layer with low resistance and low sheet resistance with the diffusion layer of the second conductivity type. In addition to forming a two-layer structure of electrode wiring, it is also possible to form another electrode wiring that is mainly insulated from the surrounding silicon thermal oxide film, resulting in high integration and high-speed operation with a significantly shortened process. We have discovered a method for manufacturing semiconductor integrated circuits that achieves both
すなわち、本発明は第1導電型の半導体基板も
しくは半導体層上に、直接又は絶縁膜を介して第
2導電型の不純物を含む多結晶シリコン膜及び高
融点金属硅化物膜を順次堆積した後、これら膜を
パターニングして二層構造の導電体パターンを形
成する工程と、高温熱酸化処理を施して前記二層
構造の導電体パターンの周囲に厚いシリコン熱酸
化膜を、露出する基板もしくは半導体層部分に薄
いシリコン熱酸化膜を成長させると共に導電体パ
ターンと直接接触した半導体基板もしくは半導体
層部分に第2導電型の拡散層を形成する工程と、
前記半導体基板もしくは半導体層上の薄いシリコ
ン熱酸化膜をエツチングにより除去した後、全面
に電極配線材料層を堆積して、前記二層構造の導
電体パターンに対してその周囲に設けられた厚い
シリコン熱酸化膜で絶縁された電極配線を形成す
る工程とを具備したことを特徴とするものであ
る。 That is, the present invention sequentially deposits a polycrystalline silicon film containing impurities of a second conductivity type and a high melting point metal silicide film on a semiconductor substrate or a semiconductor layer of a first conductivity type, either directly or via an insulating film, and then A process of patterning these films to form a two-layer conductor pattern, and performing high-temperature thermal oxidation treatment to form a thick silicon thermal oxide film around the two-layer conductor pattern on the exposed substrate or semiconductor layer. a step of growing a thin silicon thermal oxide film on the portion and forming a second conductivity type diffusion layer on the semiconductor substrate or semiconductor layer portion that is in direct contact with the conductive pattern;
After removing the thin silicon thermal oxide film on the semiconductor substrate or semiconductor layer by etching, an electrode wiring material layer is deposited on the entire surface, and a thick silicon layer is formed around the two-layer conductor pattern. The method is characterized by comprising a step of forming electrode wiring insulated with a thermal oxide film.
本発明における第1導電型の半導体層として
は、例えばp型の拡散層、より具体的にはp型の
ベース領域等である。 The semiconductor layer of the first conductivity type in the present invention is, for example, a p-type diffusion layer, more specifically, a p-type base region.
本発明における第2導電型の不純物を含む多結
晶シリコン膜及び高融点金属硅化物膜はパターニ
ングにより導電体パターンとなるものである。か
かる第2導電型の不純物を含む多結晶シリコンと
しては、例えば基板もしくは半導体層がp型の場
合、砒素や燐などのn型不純物がドープされた多
結晶シリコンを挙げることができる。こうした不
純物ドープ多結晶シリコン膜は高温熱酸化処理に
際して、第1導電型の半導体基板もしくは半導体
層より厚いシリコン熱酸化膜を成長できると共に
その不純物が熱拡散して第2導電型の拡散層を形
成できる利点を有する。なお、このような目的か
ら多結晶シリコン膜中の不純物濃度は1021/cm3以
上にすることが臨ましい。また、高融点金属硅化
物としては、例えばモリブデンシリサイド、タン
グステンシリサイド、タンタルシリサイド、白金
シリサイド等を挙げることができる。 In the present invention, the polycrystalline silicon film and the high melting point metal silicide film containing impurities of the second conductivity type are patterned to form a conductor pattern. Examples of such polycrystalline silicon containing impurities of the second conductivity type include polycrystalline silicon doped with n-type impurities such as arsenic and phosphorus when the substrate or semiconductor layer is p-type. When such an impurity-doped polycrystalline silicon film is subjected to high-temperature thermal oxidation treatment, it is possible to grow a silicon thermal oxide film that is thicker than the first conductivity type semiconductor substrate or semiconductor layer, and the impurities are thermally diffused to form a second conductivity type diffusion layer. It has the advantage of being able to Note that for this purpose, it is preferable that the impurity concentration in the polycrystalline silicon film is 10 21 /cm 3 or more. Further, examples of the high melting point metal silicide include molybdenum silicide, tungsten silicide, tantalum silicide, and platinum silicide.
本発明における高温熱酸化処理は第2導電型
の不純物を含む多結晶シリコン膜及び高融点金属
硅化物膜からなる二層構造の導電体パターンと、
半導体基板もしくは半導体層と、の間の酸化レー
トの差を利用して、該導電体パターン周囲に比較
的厚いシリコン熱酸化膜を、露出する半導体基板
もしくは半導体層部分に比較的薄いシリコン熱酸
化膜を成長させること、半導体基板もしくは半
導体層に直接接触した導電体パターンにおいて、
その多結晶シリコン膜から第2導電型の不純物を
基板等に拡散して拡散層を形成すること、導電
体パターンの一構成材である高融点金属硅化物を
アニーリングして低抵抗化すること、を目的とす
るものである。このような目的から、高温熱酸化
処理の温度としては800〜1100℃の範囲にするこ
とが望ましい。 The high-temperature thermal oxidation treatment in the present invention involves forming a conductor pattern with a two-layer structure consisting of a polycrystalline silicon film containing second conductivity type impurities and a high melting point metal silicide film;
By utilizing the difference in oxidation rate between the semiconductor substrate or semiconductor layer, a relatively thick silicon thermal oxide film is formed around the conductor pattern, and a relatively thin silicon thermal oxide film is formed on the exposed semiconductor substrate or semiconductor layer. In a conductor pattern in direct contact with a semiconductor substrate or semiconductor layer,
Diffusing impurities of a second conductivity type from the polycrystalline silicon film into a substrate or the like to form a diffusion layer, annealing high melting point metal silicide, which is a constituent material of the conductor pattern, to lower the resistance; The purpose is to For this purpose, it is desirable that the temperature of the high-temperature thermal oxidation treatment be in the range of 800 to 1100°C.
本発明における半導体基板もしくは半導体層上
の薄いシリコン熱酸化膜のエツチング除去手段と
しては、例えば全面エツチングにより除去する方
法、或いは導電体パターン周囲(特に上面)をマ
スクした後、基板面に対して略垂直に入射する気
状イオンによるエツチング、例えば反応性イオン
エツチングで選択的に除去する方法等を採用し得
る。特に、高融点金属硅化物は不純物ドープ多結
晶シリコンに比べて酸化レートがそれ程大きくな
いため、後者のエツチング手段により半導体基板
等の薄いシリコン熱酸化膜を除去することが望ま
しい。 In the present invention, the thin silicon thermal oxide film on the semiconductor substrate or semiconductor layer can be removed by etching, for example, by etching the entire surface, or after masking the periphery of the conductor pattern (particularly the upper surface), the thin silicon thermal oxide film is etched away approximately from the substrate surface. Etching using perpendicularly incident gaseous ions, for example, a selective removal method using reactive ion etching, etc., may be employed. In particular, since the oxidation rate of high melting point metal silicide is not as high as that of impurity-doped polycrystalline silicon, it is desirable to use the latter etching method to remove thin silicon thermal oxide films on semiconductor substrates and the like.
本発明における電極配線材料としては、例えば
AlもしくはAl−Cu、Al−Si、Al−Si−Cuなどの
Al合金、又はMo、W、Ta、Ptなどの高融点金
属、或いは金属硅化物等を挙げることができる。 Examples of the electrode wiring material in the present invention include
Al or Al-Cu, Al-Si, Al-Si-Cu, etc.
Examples include Al alloys, high melting point metals such as Mo, W, Ta, and Pt, and metal silicides.
次に、本発明をI2Lの製造に適用した例につい
て第4図a〜fを参照して説明する。 Next, an example in which the present invention is applied to the production of I 2 L will be described with reference to FIGS. 4a to 4f.
実施例
〔i〕 まず、p型シリコン基板21にSbを選択拡
散してn+埋込層22を形成し、更にn型のシ
リコンエピタキシヤル層23を成長させた後、
選択酸化技術により素子分離のための厚さ1.5μ
mのフイールド酸化膜24を形成した。ひきつ
づき、シリコンエピタキシヤル層23にCVD
法、写真蝕刻法によりSiO2膜25を設け、該
SiO2膜25及びフイールド酸化膜24をマス
クとしてボロンを選択的に拡散してp+型拡散
層であるベース領域26及びインジエクタ27
を形成した。その後、熱酸化処理を施してシリ
コン熱酸化膜を成長させ、この熱酸化膜を写真
蝕刻法によりパターニングしてフイールド酸化
膜24からベース領域26の一部に延在した熱
酸化膜28を形成した後、全面に砒素濃度
1021/cm3、厚さ3000Åの砒素ドープ多結晶シリ
コン膜29、厚さ3000Åのモリブデンシリサイ
ド膜30(MoSi2膜)及びシリコン窒化膜31
をCVD法により順次堆積した(第4図a図
示)。Example [i] First, after selectively diffusing Sb into a p-type silicon substrate 21 to form an n + buried layer 22 and further growing an n-type silicon epitaxial layer 23,
1.5μ thickness for element isolation using selective oxidation technology
A field oxide film 24 of m was formed. Continuing with CVD on the silicon epitaxial layer 23
A SiO 2 film 25 is provided using a photolithography method and a photolithography method.
Using the SiO 2 film 25 and field oxide film 24 as masks, boron is selectively diffused to form a base region 26 and an injector 27, which are p + type diffusion layers.
was formed. Thereafter, thermal oxidation treatment was performed to grow a silicon thermal oxide film, and this thermal oxide film was patterned by photolithography to form a thermal oxide film 28 extending from the field oxide film 24 to a part of the base region 26. After that, arsenic concentration was found on the entire surface.
10 21 /cm 3 , an arsenic-doped polycrystalline silicon film 29 with a thickness of 3000 Å, a molybdenum silicide film 30 (MoSi 2 film) with a thickness of 3000 Å, and a silicon nitride film 31
were sequentially deposited by the CVD method (shown in Figure 4a).
〔〕 次いで、シリコン窒化膜31をパターニン
グしてシリコン窒化膜パターン32a,32
b,32cを形成した後、これらパターンをマ
スクとしてMoSi2膜30、多結晶シリコン膜2
9をオーバーエツチングして多結晶シリコン、
MoSi2からなる二層構造の導電体パターン33
a,33b,33cを形成すると共に、これら
導電体パターン33a,33b,33cに対し
てシリコン窒化膜パターン32a,32b,3
2cをオーバーハング構造とした(第4図b図
示)。その後、シリコン窒化膜パターン32a,
32b,32cをマスクとして熱酸化膜28を
反応性イオンエツチングによりパターニングし
てシリコン窒化膜パターン32cに対してセル
フアラインとなる熱酸化膜パターン34を形成
した(第4図c図示)。[] Next, the silicon nitride film 31 is patterned to form silicon nitride film patterns 32a, 32.
After forming patterns b and 32c, MoSi 2 film 30 and polycrystalline silicon film 2 are formed using these patterns as masks.
Polycrystalline silicon by over-etching 9.
Two-layer conductor pattern 33 made of MoSi 2
a, 33b, 33c, and silicon nitride film patterns 32a, 32b, 33c are formed on these conductor patterns 33a, 33b, 33c.
2c has an overhang structure (as shown in FIG. 4b). After that, the silicon nitride film pattern 32a,
Using 32b and 32c as masks, the thermal oxide film 28 was patterned by reactive ion etching to form a thermal oxide film pattern 34 that was self-aligned with the silicon nitride film pattern 32c (as shown in FIG. 4c).
〔〕 次いで、900℃の高温ウエツト雰囲気中で
熱酸化処理を施した。この時、第4図dに示す
ように砒素ドープ多結晶シリコン及びMoSi2か
らなる導電体パターン33a,33b,33c
と露出するシリコンエピタキシヤル層23(ベ
ース、インジエクタ領域)の酸化レートの差、
並びに導電体パターン33a,33b,33c
上のシリコン窒化膜パターン32a,32b,
32cの酸化剤遮蔽作用により、導電体パター
ン33a,33b,33cの周側面のみに厚い
シリコン熱酸化膜35、露出するベース領域2
6及びインジエクタ27上に薄いシリコン熱酸
化膜36が成長された。しかも、ベース領域2
6と直接接した導電体パターン33a,33b
の砒素ドープ多結晶シリコン膜29からベース
領域26に砒素が拡散されn+型拡散層である
深いコレクタ領域37,37が形成された。ま
た、同時に導電体パターン33a,33b,3
3cのMoSi2膜30が十分アニーリングされ低
抵抗化すると共に、導電体パターン33a,3
3bがコレクタ領域37,37に対して低抵抗
でコンタクトされた。[] Next, thermal oxidation treatment was performed in a high temperature wet atmosphere at 900°C. At this time, as shown in FIG. 4d, conductor patterns 33a, 33b, 33c made of arsenic-doped polycrystalline silicon and MoSi2 are formed.
and the difference in the oxidation rate of the exposed silicon epitaxial layer 23 (base, injector region),
and conductor patterns 33a, 33b, 33c
Upper silicon nitride film patterns 32a, 32b,
Due to the oxidizing agent shielding effect of 32c, a thick silicon thermal oxide film 35 is formed only on the peripheral sides of the conductor patterns 33a, 33b, and 33c, and the base region 2 is exposed.
A thin silicon thermal oxide film 36 was grown on the injector 6 and the injector 27. Moreover, base area 2
Conductor patterns 33a, 33b in direct contact with 6
Arsenic is diffused from the arsenic-doped polycrystalline silicon film 29 into the base region 26 to form deep collector regions 37, 37, which are n + -type diffusion layers. At the same time, conductor patterns 33a, 33b, 3
The MoSi 2 film 30 of 3c is sufficiently annealed to have a low resistance, and the conductor patterns 33a, 3
3b was in contact with the collector regions 37, 37 with low resistance.
〔〕 次いで、反応性イオンエツチングを全面に
施した。この時、シリコン窒化膜パターン32
a,32b,32cがマスクとして作用し、こ
のオーバーハングの陰となる部分、つまり導電
体パターン33a,33b,33c周側面の厚
いシリコン熱酸化膜35は全くエツチングされ
ず、ベース領域26及びインジエクタ27上の
薄いシリコン熱酸化膜36が選択的に除去さ
れ、ベース領域26及びインジエクタ27の大
部分が露出すると共に、厚いシリコン熱酸化膜
35及びシリコン窒化膜パターン32a,32
bで覆われ、コレクタ領域37,37と接触し
た導電体パターンはコレクタ取出し電極38,
38となり、同熱酸化膜35、シリコン窒化膜
パターン32cで覆われ熱酸化膜パターン34
を介してベース領域26上に配置された導電体
パターンはジヤンパ配線39となる(第4図e
図示)。その後、全面にAl層を堆積し、ベース
領域26とインジエクタ27の境界に位置する
SiO2膜25、及びフイールド酸化膜24上で
Al層をラフな写真蝕刻法でパターニングした。
この時、第4図fに示すようにコレクタ取出し
電極38,38、ジヤンパ配線39に対して厚
いシリコン熱酸化膜35、シリコン窒化膜パタ
ーン32a,32b,32cで絶縁され、ベー
ス領域26と広い面積で接触したベース取出し
電極40及びインジエクタ取出し電極41が形
成されI2Lが製造された。[] Next, reactive ion etching was applied to the entire surface. At this time, the silicon nitride film pattern 32
a, 32b, and 32c act as a mask, and the thick silicon thermal oxide film 35 on the circumferential side of the conductor patterns 33a, 33b, and 33c, which is in the shadow of this overhang, is not etched at all, and the base region 26 and injector 27 are completely etched. The upper thin silicon thermal oxide film 36 is selectively removed to expose most of the base region 26 and injector 27, and the thick silicon thermal oxide film 35 and silicon nitride film patterns 32a, 32 are removed.
The conductor pattern covered with b and in contact with the collector regions 37, 37 is the collector extraction electrode 38,
38, the thermal oxide film pattern 34 is covered with the same thermal oxide film 35 and the silicon nitride film pattern 32c.
The conductor pattern placed on the base region 26 via the jumper wiring 39 (see Fig. 4e)
(Illustrated). After that, an Al layer is deposited on the entire surface and is located at the boundary between the base region 26 and the injector 27.
On the SiO 2 film 25 and the field oxide film 24
The Al layer was patterned using a rough photo-etching method.
At this time, as shown in FIG. 4f, the collector lead-out electrodes 38, 38 and the jumper wiring 39 are insulated by the thick silicon thermal oxide film 35 and silicon nitride film patterns 32a, 32b, 32c, and the base region 26 and wide area A base lead-out electrode 40 and an injector lead-out electrode 41 which were in contact with each other were formed, and I 2 L was manufactured.
得られたI2Lはベース領域26とこの領域に
形成されたコレクタ領域37,37とが砒素ド
ープ多結晶シリコン及びMoSi2からなる導電体
パターンの厚い酸化膜35で分離されているた
め、コレクタ領域37,37の面積を増大で
き、電流増幅率の向上化が達成できた。また、
砒素ドープ多結晶シリコンとMoSi2からなる二
層構造のコレクタ取出し電極38,38は高温
熱酸化処理でのMoSi2のアニーリングによる低
抵抗により、砒素ドープ多結晶シリコンのみか
らなるコレクタ取出し電極に比較して抵抗値を
数Ω/□(砒素ドープ多結晶シリコンのみでは
約100〜200Ω/□)と著しく低くでき、高速動
作化、高電流領域での使用が可能となつた。事
実、本実施例で製造されたI2Lのリングオシレ
ータによる遅延出力を調べると第5図に示す特
性図となり伝播遅延速度(tpd)は最小1nsec以
下となり、従来のI2Lに比べて高速化できるこ
とがわかる。また、砒素ドープ多結晶シリコン
及びMoSi2からなる二層構造の導電体パターン
をコレクタ取出し電極38,38やジヤンパ配
線39として利用でき、ベース取出しAl電極
40とは多層電極構造になつていることから、
I2Lの高集積度化が可能となつた。 The obtained I 2 L is isolated from the base region 26 and the collector regions 37, 37 formed in this region by a thick oxide film 35 of a conductor pattern made of arsenic-doped polycrystalline silicon and MoSi 2 . The areas of the regions 37, 37 could be increased, and the current amplification factor could be improved. Also,
The collector lead-out electrodes 38, 38, which have a two-layer structure made of arsenic-doped polycrystalline silicon and MoSi 2 , have low resistance due to the annealing of MoSi 2 during high-temperature thermal oxidation treatment, compared to collector lead-out electrodes made only of arsenic-doped polycrystalline silicon. As a result, the resistance value can be significantly lowered to several Ω/□ (approximately 100 to 200 Ω/□ with arsenic-doped polycrystalline silicon alone), and high-speed operation and use in high current ranges are now possible. In fact, when examining the delay output from the ring oscillator of the I 2 L manufactured in this example, the characteristic diagram shown in Figure 5 shows that the propagation delay speed (TPD) is at least 1 nsec, which is faster than the conventional I 2 L. It turns out that it can be converted into In addition, a two-layer conductor pattern made of arsenic-doped polycrystalline silicon and MoSi 2 can be used as the collector lead-out electrodes 38, 38 and jumper wiring 39, and the base lead-out Al electrode 40 has a multilayer electrode structure. ,
High integration of I 2 L has become possible.
なお、本発明は上記実施例の如くI2Lの製造
のみに限定されず、通常のバイポーラ型集積回
路、ECL(Emitter Coupled Logic)等にも同
様に適用でき、更に同一基板内にI2Lと通常の
バイポーラ型集積回路、ECLを製造しても同
様な効果が期待できる。 Note that the present invention is not limited to the production of I 2 L as in the above embodiment, but can be similarly applied to ordinary bipolar integrated circuits, ECL ( Emitter Coupled Logic), etc. A similar effect can be expected by manufacturing a normal bipolar integrated circuit or ECL.
以上詳述した如く、本発明によれば第1導電型
の半導体基板もしくは半導体層上に直接又は絶縁
膜を介して第2導電型の不純物を含む多結晶シリ
コン及び高融点金属硅化物からなる2層構造の導
電体パターンを形成した後、高温熱酸化処理を施
すことによつて、半導体基板等に第2導電型の
拡散層を形成でき、第2導電型の拡散層とのコ
ンタクト抵抗の増大を招くことなく高融点金属硅
化物の低抵抗化、ひいては導電体パターンの低抵
抗化を達成でき、導電体パターン周囲に比較的
厚いシリコン熱酸化膜を、露出する半導体基板等
の部分にも比較的薄いシリコン熱酸化膜を成長で
き、その後露出する半導体基板部分のシリコン熱
酸化膜を除去し、電極配線材料層を堆積すること
により、第2導電型の拡散層と低抵抗接触し、か
つシート抵抗の小さい二層構造の電極配線を形成
できると共に、この電極配線に対してその周囲の
シリコン熱酸化膜で主に絶縁された別の電極配線
を形成できる。したがつて、著しく短縮された工
程で高集積化と高速動作化との両方を達成した半
導体集積回路を製造し得る方法を提供できるもの
である。 As described in detail above, according to the present invention, a semiconductor substrate or semiconductor layer of a first conductivity type is formed of polycrystalline silicon and a refractory metal silicide containing impurities of a second conductivity type directly or through an insulating film. By performing high-temperature thermal oxidation treatment after forming a layered conductor pattern, a second conductivity type diffusion layer can be formed on a semiconductor substrate, etc., and contact resistance with the second conductivity type diffusion layer can be increased. It is possible to lower the resistance of high-melting point metal silicides and, in turn, lower the resistance of conductor patterns without causing any A thin silicon thermal oxide film can be grown, and then the silicon thermal oxide film on the exposed semiconductor substrate portion is removed and an electrode wiring material layer is deposited to make low resistance contact with the second conductivity type diffusion layer and form a sheet. It is possible to form an electrode wiring having a two-layer structure with low resistance, and also to form another electrode wiring that is mainly insulated from the electrode wiring by the silicon thermal oxide film surrounding it. Therefore, it is possible to provide a method for manufacturing a semiconductor integrated circuit that achieves both high integration and high-speed operation with a significantly shortened process.
第1図a〜cは従来法によるI2Lの製造工程を
示す断面図、第2図はアニーリング処理によるモ
リブデンシリサイド膜(MoSi2)の抵抗変化を示
す特性図、第3図はアニーリング処理による
MoSi2膜のみからなる取出し電極或いは砒素ドー
プ多結晶シリコン及びMoSi2の二層構造からなる
取出し電極と基板の拡散層とのコンタクト抵抗の
変化を示す特性図、第4図a〜fは本発明の実施
例におけるI2Lの製造工程を示す断面図、第5図
は本発明の実施例で得られたI2Lのリングオシレ
ータによる遅延出力を示す特性図である。
21……p型シリコン基板、22……n+埋込
層、23……n型シリコンエピタキシヤル層、2
4……フイールド酸化膜、26……p+ベース領
域、27……インジエクタ、29……砒素ドープ
多結晶シリコン膜、30……モリブデンシリサイ
ド膜、32a,32b,32c……シリコン窒化
膜パターン、33a,33b,33c……導電体
パターン、35……厚いシリコン熱酸化膜、36
……薄いシリコン熱酸化膜、37,37……n+
型コレクタ領域、38,38……コレクタ取出し
電極、39……ジヤンパ配線、40……ベース取
出しAl電極、41……インジエクタ取出しAl電
極。
Figures 1 a to c are cross-sectional views showing the manufacturing process of I 2 L using the conventional method, Figure 2 is a characteristic diagram showing the resistance change of a molybdenum silicide film (MoSi 2 ) due to annealing treatment, and Figure 3 is a cross-sectional view showing the manufacturing process of I 2 L using the conventional method.
Characteristic diagrams showing changes in contact resistance between an extraction electrode made of only a MoSi 2 film or a two-layer structure of arsenic-doped polycrystalline silicon and MoSi 2 and a diffusion layer of the substrate, FIGS. FIG. 5 is a cross-sectional view showing the manufacturing process of I 2 L in the embodiment of the present invention, and FIG. 5 is a characteristic diagram showing the delayed output by the ring oscillator of I 2 L obtained in the embodiment of the present invention. 21...p-type silicon substrate, 22...n + buried layer, 23... n-type silicon epitaxial layer, 2
4...Field oxide film, 26...P + base region, 27...Injector, 29...Arsenic-doped polycrystalline silicon film, 30...Molybdenum silicide film, 32a, 32b, 32c...Silicon nitride film pattern, 33a , 33b, 33c...Conductor pattern, 35...Thick silicon thermal oxide film, 36
...Thin silicon thermal oxide film, 37,37...n +
Mold collector area, 38, 38... Collector lead-out electrode, 39... Jumper wiring, 40... Base lead-out Al electrode, 41... Injector lead-out Al electrode.
Claims (1)
に、直接又は絶縁膜を介して第2導電型の不純物
を含む多結晶シリコン膜及び高融点金属硅化物膜
を順次堆積した後、これら膜を選択エツチングし
て二層構造の導電体パターンを形成する工程と、
高温熱酸化処理を施して前記二層構造の導電体パ
ターンの周囲に厚いシリコン熱酸化膜を、露出す
る基板もしくは半導体層部分に薄いシリコン熱酸
化膜を成長させると共に導電体パターンと直接接
触した半導体基板もしくは半導体層に第2導電型
の拡散層を形成する工程と、前記半導体基板もし
くは半導体層上の薄いシリコン熱酸化膜をエツチ
ングにより除去した後、全面に電極配線材料層を
堆積して、前記二層構造の導電体パターンに対し
てその周囲に設けた厚いシリコン熱酸化膜で絶縁
された電極配線を形成する工程とを具備したこと
を特徴とする半導体集積回路の製造方法。 2 第1導電型の半導体層がp型の拡散層で、二
層構造の導電体パターンの一構成材としての第2
導電型の多結晶シリコン膜がn+型のもので、高
温熱酸化処理により導電体パターンと接するp型
の拡散層にバイポーラトランジスタのエミツタ或
いはコレクタの拡散層を形成すると共に、p型の
拡散層と接する導電体パターンをエミツタ或いは
コレクタの拡散層の取出し電極、絶縁物上の導電
体パターンをジヤンパ配線とし、かつ該取出し電
極、ジヤンパ配線を前記p型拡散層の取出し電極
に対し多結晶シリコンと高融点金属硅化物のシリ
コン熱酸化膜で絶縁された自己整合構造とするこ
とを特徴とする特許請求の範囲第1項記載の半導
体集積回路の製造方法。 3 第1導電型の半導体層がI2Lゲートのnpnト
ランジスタのベース及び同ゲートのpnpトランジ
スタのエミツタで高温熱酸化処理により二層構造
の導電体パターンと接する第1導電型の領域中に
該パターンの一構成材である多結晶シリコンから
第2導電型の不純物を拡散してI2Lゲートのnpn
トランジスタのコレクタを形成することを特徴と
する特許請求の範囲第1項記載の半導体集積回路
の製造方法。 4 同一半導体基板内に、導電体パターンの高温
熱酸化処理により形成されるI2Lのnpnトランジ
スタのコレクタ拡散層を設けると共に、該導電体
パターンをコレクタ拡散層の取出し電極とし、か
つ同高温熱酸化処理により形成されるnpnバイポ
ーラトランジスタのエミツタ或いはコレクタの拡
散層を設けると共に該導電体パターンをエミツタ
或いはコレクタの拡散層の取出し電極とすること
を特徴とする特許請求の範囲第1項記載の半導体
集積回路の製造方法。[Claims] 1. A polycrystalline silicon film containing impurities of a second conductivity type and a high melting point metal silicide film are sequentially deposited on a semiconductor substrate or a semiconductor layer of a first conductivity type, either directly or via an insulating film. After that, a step of selectively etching these films to form a two-layer conductor pattern,
A thick silicon thermal oxide film is grown around the two-layered conductor pattern by high-temperature thermal oxidation treatment, and a thin silicon thermal oxide film is grown on the exposed substrate or semiconductor layer, and the semiconductor is in direct contact with the conductor pattern. After forming a second conductivity type diffusion layer on the substrate or semiconductor layer and removing the thin silicon thermal oxide film on the semiconductor substrate or semiconductor layer by etching, depositing an electrode wiring material layer on the entire surface, 1. A method for manufacturing a semiconductor integrated circuit, comprising the step of forming an electrode wiring insulated by a thick silicon thermal oxide film provided around a two-layer conductor pattern. 2. The first conductive type semiconductor layer is a p-type diffusion layer, and the second conductive layer is a component of a two-layer conductor pattern.
The conductivity type of the polycrystalline silicon film is n + type, and the emitter or collector diffusion layer of the bipolar transistor is formed in the p-type diffusion layer in contact with the conductor pattern by high-temperature thermal oxidation treatment, and the p-type diffusion layer is The conductor pattern in contact with the p-type diffusion layer is an extraction electrode of the emitter or collector diffusion layer, and the conductor pattern on the insulator is a jumper wiring, and the extraction electrode and jumper wiring are connected to the extraction electrode of the p-type diffusion layer with polycrystalline silicon. 2. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit has a self-aligned structure insulated by a silicon thermal oxide film made of a high melting point metal silicide. 3 The semiconductor layer of the first conductivity type is applied to the base of the npn transistor with the I 2 L gate and the emitter of the pnp transistor with the same gate into the first conductivity type region in contact with the conductor pattern of the two-layer structure by high-temperature thermal oxidation treatment. The npn of the I 2 L gate is formed by diffusing second conductivity type impurities from polycrystalline silicon, which is a constituent material of the pattern.
2. The method of manufacturing a semiconductor integrated circuit according to claim 1, further comprising forming a collector of a transistor. 4 In the same semiconductor substrate, a collector diffusion layer of an I 2 L npn transistor is formed by high-temperature thermal oxidation treatment of a conductive pattern, and the conductive pattern is used as an extraction electrode of the collector diffusion layer, and the same high-temperature thermal oxidation process is performed. The semiconductor according to claim 1, characterized in that an emitter or collector diffusion layer of an npn bipolar transistor formed by oxidation treatment is provided, and the conductor pattern is used as an extraction electrode of the emitter or collector diffusion layer. A method of manufacturing integrated circuits.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5335080A JPS56150850A (en) | 1980-04-22 | 1980-04-22 | Manufacture of semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5335080A JPS56150850A (en) | 1980-04-22 | 1980-04-22 | Manufacture of semiconductor integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56150850A JPS56150850A (en) | 1981-11-21 |
JPH0222544B2 true JPH0222544B2 (en) | 1990-05-18 |
Family
ID=12940322
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5335080A Granted JPS56150850A (en) | 1980-04-22 | 1980-04-22 | Manufacture of semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56150850A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0534632B1 (en) * | 1991-09-24 | 2002-01-16 | Matsushita Electronics Corporation, Ltd. | Semiconductor integrated circuit device and method of fabricating the same |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52117579A (en) * | 1976-03-30 | 1977-10-03 | Nec Corp | Semiconductor device |
JPS53142196A (en) * | 1977-05-18 | 1978-12-11 | Hitachi Ltd | Bipolar type semiconductor device |
-
1980
- 1980-04-22 JP JP5335080A patent/JPS56150850A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52117579A (en) * | 1976-03-30 | 1977-10-03 | Nec Corp | Semiconductor device |
JPS53142196A (en) * | 1977-05-18 | 1978-12-11 | Hitachi Ltd | Bipolar type semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPS56150850A (en) | 1981-11-21 |
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