JPH0222544B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit, and particularly to a method for manufacturing a bipolar integrated circuit having an I ² L element.

I ² L (Integrated Injection Logic) has a composite structure of an inverted vertical transistor (e.g. npn transistor) and a complementary lateral transistor (pnp transistor) whose collector is the base of this transistor. It is a logic element. In such I ² L, the lateral transistor acts as an injector that injects charge into the base of the vertical transistor with the reverse structure, and the vertical transistor with the reverse structure operates as an inverter. For this reason, I ² L has attracted attention in recent years as an element that has a small logic amplitude and can operate at high speed and with low power consumption. Furthermore, since I ² L does not require isolation between vertical transistors and lateral transistors, it has a high degree of integration and is suitable for large-scale integrated circuit applications. Furthermore, since I ² L is a bipolar process technology, it is easy to integrate other bipolar circuits, such as linear circuits and ECL circuits, on the same chip.
(Emitter, Coupled Logic) can coexist, making it possible to realize multifunctional integrated circuits.

By the way, a lot of research has been done to make the above-mentioned I ² L operate at high speed. For example, IEEE
Journal of Solid−State Circuits, Vol, SC−
14, No. 2, April 1979, 327-336. In order to reduce the accumulation of minority carriers,
In addition to optimizing the concentration profile of the epitaxial semiconductor layer and the emitter layer, it is effective to minimize the area where minority carriers are accumulated. From this point of view, it has been conventionally considered to produce I ² L by the following method. That is, after selectively forming an n ⁺ buried layer 2 on a p-type silicon substrate 1 and growing an n-type epitaxial layer 3 on the same substrate 1, a thick field oxide film 4 for device isolation is selected. Formed by oxidation technology.
Subsequently, after selectively covering the SiO ₂ film 5 on the element forming region by CVD method or photolithography method, this SiO ₂ film 5 is
Boron is thermally diffused using the film 5 as a mask to form a p-type base region 6 and an injector 7 (as shown in FIG. 1A). Next, a polycrystalline silicon film doped with arsenic, which is an n-type impurity, is deposited on the entire surface.
After further depositing a CVD-SiO ₂ film, the CVD-SiO ₂ film is patterned to form CVD-SiO ₂ patterns 8a, 8.
b is formed, and using this as a mask, the polycrystalline silicon film is selectively etched to form polycrystalline silicon patterns 9a and 9b on the portion where the collector region is to be formed (as shown in FIG. 1b). Subsequently, a thick silicon thermal oxide film 10 is formed around the polycrystalline silicon patterns 9a and 9b on which CVD-SiO ₂ patterns 8a and 8b are provided by high-temperature thermal oxidation treatment, and a thin silicon film is formed on the exposed base region 6 and injector 7. A thermal oxide film (not shown) is grown, and arsenic is diffused from arsenic-doped polycrystalline silicon patterns 9a, 9b into p-type base region 6 to form n ⁺ -type collector regions 11a, 11b. after that,
Etching and removing the thin silicon thermal oxide film
After using the CVD-SiO ₂ patterns 8a, 8b and the polycrystalline silicon pattern insulated by the thick silicon thermal oxide film 10 as the collector lead-out electrodes 12a, 12b, an Al film is deposited on the entire surface, and the field oxide film 4 is formed.
And by patterning on the SiO ₂ film 5, a base lead-out Al electrode 13 and an injector lead-out Al electrode 14 are formed.
to form an integrated circuit containing I ² L (first step
Figure c).

In manufacturing an integrated circuit including the above-mentioned I ² L, the base contact hole can be opened in a self-aligned manner with respect to the collector lead-out electrodes 12a and 12b of arsenic-doped polycrystalline silicon,
can be brought into contact with the base region 6 over a wide area.
Furthermore, the area of the base region 6 can be made smaller than the area of the collector regions 11a and 11b. Therefore, the speed of the obtained I ² L can be increased, and the current amplification factor (h _FE ) can be improved by increasing the area ratio (S _C /S _B ) of the collector and the base.
Furthermore, the degree of integration can be improved. However, in such a conventional method, the collector extraction electrode 12a,
Since 12b is made of polycrystalline silicon, its sheet resistance is extremely high compared to the Al electrode. For example, if the collector lead electrode is made of arsenic-doped polycrystalline silicon with a thickness of 3000 Å, the sheet resistance is
It will be as high as 100Ω/□ to 200Ω/□. Therefore, I ² L does not operate in a high current region (several 100 μA/gate or more) and is also subject to circuit design constraints.
For this reason, the collector electrode made of polycrystalline silicon must be connected to the Al wiring midway, making it impossible to expect a significant improvement in the degree of integration.

In response, the inventor of the present invention has discovered a method of manufacturing a semiconductor integrated circuit that achieves both high integration and high-speed operation based on the research results described below.

In other words, focusing on the fact that high melting point metal silicide has lower resistance than polycrystalline silicon film, for example,
When a 3000 Å thick molybdenum silicide film (MoSi ₂ film) is annealed, it becomes Mo ₂ Si as shown in Figure 2.
A resistance change characteristic curve S ₁ of the membrane is obtained. From this figure 2, even in low temperature annealing (approximately 500℃)
The resistance of the MoSi ₂ film is approximately 40Ω, and if it is further annealed at a high temperature (approximately 1000℃), it becomes approximately 2Ω, which is an extremely low resistance compared to polycrystalline silicon of the same thickness (100 to 200Ω/□). .

However, the above-mentioned high melting point metal silicide film, for example, a MoSi ₂ film with a thickness of 3000 Å, is provided in direct contact on the n ⁺ diffusion layer (resistance 10 Ω/□) of a silicon substrate,
We attempted to form electrode wiring by applying heat treatment to the MoSi ₂ film to lower its resistance. however,
Silicon substrates subjected to heat treatment under these conditions
When we examine the contact resistance of the MoSi ₂ film, we find that the contact resistance change characteristic curve S ₂ of the MoSi ₂ film is shown in Figure 3.
Therefore, when high-temperature treatment is performed, the contact resistance increases abnormally, and eventually it becomes a shot key and cannot function as a lead-out wiring for the diffusion layer.

Therefore, the inventors of the present invention conducted extensive research based on the above problems, and directly deposited a polycrystalline silicon film containing high concentration impurities of a second conductivity type (n type) on a silicon substrate of a first conductivity type (for example, p type). A high melting point metal silicide film (e.g. 3000 Å thick MoSi ₂ film) is deposited on top of this.
After depositing the MoSi 2 film, heat treatment was performed to lower the resistance of the MoSi ₂ film. As a result, as shown in Fig. 3, a contact resistance change characteristic curve F of MoSi ₂ /n ⁺ pol-Si with respect to a silicon substrate was obtained, and even when high-temperature treatment is performed, polycrystalline silicon containing high concentration impurities is present. It has been found that this makes it possible to prevent an increase in contact resistance to the substrate. Due to this, the second conductivity type is placed on the silicon substrate of the first conductivity type.
After depositing a high-melting point metal silicide film containing conductive type impurities at a high concentration and patterning these, high-temperature heat treatment (for example, around 1000°C) can be performed without increasing the contact resistance to the silicon substrate ( (approximately 1Ω at 10μm□ from F in Figure 3),
Lower resistance of high melting point metal silicide film (from S ₁ in Figure 2)
We have found that it is possible to achieve a resistance of approximately 4Ω), thereby ensuring low resistance contact with the substrate, and forming a two-layer structure of electrode wiring with low sheet resistance. Moreover,
Through this high-temperature thermal oxidation treatment, impurities of the second conductivity type are thermally diffused from the polycrystalline silicon containing highly concentrated impurities of the second conductivity type into the silicon substrate of the first conductivity type to form a desired diffusion layer of the second conductivity type. I was able to form it.

In addition, since the oxidation rate of high-melting point metal silicide is equivalent to that of ordinary undoped polycrystalline silicon, a high-melting point metal silicide film is deposited on a polycrystalline silicon film containing impurities of the second conductivity type. After patterning, by performing high-temperature heat treatment in an oxidizing atmosphere to lower the resistance, the resistance of the high-melting point metal silicide is low, and the surroundings of the two-layer structure of polycrystalline silicon and high-melting point metal silicide are We have discovered that it is possible to grow a silicon thermal oxide film and to insulate the two-layered electrode wiring from another electrode wiring that crosses over it.

Therefore, based on the above-mentioned knowledge, the present inventor sequentially deposited a polycrystalline silicon film containing impurities of a second conductivity type and a high melting point metal silicide film on a semiconductor substrate of a first conductivity type, and patterned these films. After forming a conductor pattern with a two-layer structure, a high-temperature thermal oxidation treatment is performed to diffuse a second conductivity type impurity from the polycrystalline silicon film to form a second conductive pattern on the substrate, etc.
It is possible to form a conductive type diffusion layer, and it is possible to achieve low resistance of the high-melting point metal silicide, and thus of the conductor pattern, without increasing the contact resistance between this diffusion layer and the conductor pattern. We were able to grow a silicon thermal oxide film around the periphery and also on the exposed parts of the semiconductor substrate.
However, by selectively removing the silicon thermal oxide film on the exposed portion of the semiconductor substrate and then depositing an electrode wiring material layer, it is possible to form a layer with low resistance and low sheet resistance with the diffusion layer of the second conductivity type. In addition to forming a two-layer structure of electrode wiring, it is also possible to form another electrode wiring that is mainly insulated from the surrounding silicon thermal oxide film, resulting in high integration and high-speed operation with a significantly shortened process. We have discovered a method for manufacturing semiconductor integrated circuits that achieves both

That is, the present invention sequentially deposits a polycrystalline silicon film containing impurities of a second conductivity type and a high melting point metal silicide film on a semiconductor substrate or a semiconductor layer of a first conductivity type, either directly or via an insulating film, and then A process of patterning these films to form a two-layer conductor pattern, and performing high-temperature thermal oxidation treatment to form a thick silicon thermal oxide film around the two-layer conductor pattern on the exposed substrate or semiconductor layer. a step of growing a thin silicon thermal oxide film on the portion and forming a second conductivity type diffusion layer on the semiconductor substrate or semiconductor layer portion that is in direct contact with the conductive pattern;
After removing the thin silicon thermal oxide film on the semiconductor substrate or semiconductor layer by etching, an electrode wiring material layer is deposited on the entire surface, and a thick silicon layer is formed around the two-layer conductor pattern. The method is characterized by comprising a step of forming electrode wiring insulated with a thermal oxide film.

The semiconductor layer of the first conductivity type in the present invention is, for example, a p-type diffusion layer, more specifically, a p-type base region.

In the present invention, the polycrystalline silicon film and the high melting point metal silicide film containing impurities of the second conductivity type are patterned to form a conductor pattern. Examples of such polycrystalline silicon containing impurities of the second conductivity type include polycrystalline silicon doped with n-type impurities such as arsenic and phosphorus when the substrate or semiconductor layer is p-type. When such an impurity-doped polycrystalline silicon film is subjected to high-temperature thermal oxidation treatment, it is possible to grow a silicon thermal oxide film that is thicker than the first conductivity type semiconductor substrate or semiconductor layer, and the impurities are thermally diffused to form a second conductivity type diffusion layer. It has the advantage of being able to Note that for this purpose, it is preferable that the impurity concentration in the polycrystalline silicon film is 10 ²¹ /cm ³ or more. Further, examples of the high melting point metal silicide include molybdenum silicide, tungsten silicide, tantalum silicide, and platinum silicide.

The high-temperature thermal oxidation treatment in the present invention involves forming a conductor pattern with a two-layer structure consisting of a polycrystalline silicon film containing second conductivity type impurities and a high melting point metal silicide film;
By utilizing the difference in oxidation rate between the semiconductor substrate or semiconductor layer, a relatively thick silicon thermal oxide film is formed around the conductor pattern, and a relatively thin silicon thermal oxide film is formed on the exposed semiconductor substrate or semiconductor layer. In a conductor pattern in direct contact with a semiconductor substrate or semiconductor layer,
Diffusing impurities of a second conductivity type from the polycrystalline silicon film into a substrate or the like to form a diffusion layer, annealing high melting point metal silicide, which is a constituent material of the conductor pattern, to lower the resistance; The purpose is to For this purpose, it is desirable that the temperature of the high-temperature thermal oxidation treatment be in the range of 800 to 1100°C.

In the present invention, the thin silicon thermal oxide film on the semiconductor substrate or semiconductor layer can be removed by etching, for example, by etching the entire surface, or after masking the periphery of the conductor pattern (particularly the upper surface), the thin silicon thermal oxide film is etched away approximately from the substrate surface. Etching using perpendicularly incident gaseous ions, for example, a selective removal method using reactive ion etching, etc., may be employed. In particular, since the oxidation rate of high melting point metal silicide is not as high as that of impurity-doped polycrystalline silicon, it is desirable to use the latter etching method to remove thin silicon thermal oxide films on semiconductor substrates and the like.

Examples of the electrode wiring material in the present invention include
Al or Al-Cu, Al-Si, Al-Si-Cu, etc.
Examples include Al alloys, high melting point metals such as Mo, W, Ta, and Pt, and metal silicides.

Next, an example in which the present invention is applied to the production of I ² L will be described with reference to FIGS. 4a to 4f.

Example [i] First, after selectively diffusing Sb into a p-type silicon substrate 21 to form an n ⁺ buried layer 22 and further growing an n-type silicon epitaxial layer 23,
1.5μ thickness for element isolation using selective oxidation technology
A field oxide film 24 of m was formed. Continuing with CVD on the silicon epitaxial layer 23
A SiO ₂ film 25 is provided using a photolithography method and a photolithography method.
Using the SiO ₂ film 25 and field oxide film 24 as masks, boron is selectively diffused to form a base region 26 and an injector 27, which are p ⁺ type diffusion layers.
was formed. Thereafter, thermal oxidation treatment was performed to grow a silicon thermal oxide film, and this thermal oxide film was patterned by photolithography to form a thermal oxide film 28 extending from the field oxide film 24 to a part of the base region 26. After that, arsenic concentration was found on the entire surface.
10 ²¹ /cm ³ , an arsenic-doped polycrystalline silicon film 29 with a thickness of 3000 Å, a molybdenum silicide film 30 (MoSi ₂ film) with a thickness of 3000 Å, and a silicon nitride film 31
were sequentially deposited by the CVD method (shown in Figure 4a).

[] Next, the silicon nitride film 31 is patterned to form silicon nitride film patterns 32a, 32.
After forming patterns b and 32c, MoSi ₂ film 30 and polycrystalline silicon film 2 are formed using these patterns as masks.
Polycrystalline silicon by over-etching 9.
Two-layer conductor pattern 33 made of MoSi ₂
a, 33b, 33c, and silicon nitride film patterns 32a, 32b, 33c are formed on these conductor patterns 33a, 33b, 33c.
2c has an overhang structure (as shown in FIG. 4b). After that, the silicon nitride film pattern 32a,
Using 32b and 32c as masks, the thermal oxide film 28 was patterned by reactive ion etching to form a thermal oxide film pattern 34 that was self-aligned with the silicon nitride film pattern 32c (as shown in FIG. 4c).

[] Next, thermal oxidation treatment was performed in a high temperature wet atmosphere at 900°C. At this time, as shown in FIG. 4d, conductor patterns 33a, 33b, 33c made of arsenic-doped polycrystalline silicon and _MoSi2 are formed.
and the difference in the oxidation rate of the exposed silicon epitaxial layer 23 (base, injector region),
and conductor patterns 33a, 33b, 33c
Upper silicon nitride film patterns 32a, 32b,
Due to the oxidizing agent shielding effect of 32c, a thick silicon thermal oxide film 35 is formed only on the peripheral sides of the conductor patterns 33a, 33b, and 33c, and the base region 2 is exposed.
A thin silicon thermal oxide film 36 was grown on the injector 6 and the injector 27. Moreover, base area 2
Conductor patterns 33a, 33b in direct contact with 6
Arsenic is diffused from the arsenic-doped polycrystalline silicon film 29 into the base region 26 to form deep collector regions 37, 37, which are n ⁺ -type diffusion layers. At the same time, conductor patterns 33a, 33b, 3
The MoSi ₂ film 30 of 3c is sufficiently annealed to have a low resistance, and the conductor patterns 33a, 3
3b was in contact with the collector regions 37, 37 with low resistance.

[] Next, reactive ion etching was applied to the entire surface. At this time, the silicon nitride film pattern 32
a, 32b, and 32c act as a mask, and the thick silicon thermal oxide film 35 on the circumferential side of the conductor patterns 33a, 33b, and 33c, which is in the shadow of this overhang, is not etched at all, and the base region 26 and injector 27 are completely etched. The upper thin silicon thermal oxide film 36 is selectively removed to expose most of the base region 26 and injector 27, and the thick silicon thermal oxide film 35 and silicon nitride film patterns 32a, 32 are removed.
The conductor pattern covered with b and in contact with the collector regions 37, 37 is the collector extraction electrode 38,
38, the thermal oxide film pattern 34 is covered with the same thermal oxide film 35 and the silicon nitride film pattern 32c.
The conductor pattern placed on the base region 26 via the jumper wiring 39 (see Fig. 4e)
(Illustrated). After that, an Al layer is deposited on the entire surface and is located at the boundary between the base region 26 and the injector 27.
On the SiO ₂ film 25 and the field oxide film 24
The Al layer was patterned using a rough photo-etching method.
At this time, as shown in FIG. 4f, the collector lead-out electrodes 38, 38 and the jumper wiring 39 are insulated by the thick silicon thermal oxide film 35 and silicon nitride film patterns 32a, 32b, 32c, and the base region 26 and wide area A base lead-out electrode 40 and an injector lead-out electrode 41 which were in contact with each other were formed, and I ² L was manufactured.

The obtained I ² L is isolated from the base region 26 and the collector regions 37, 37 formed in this region by a thick oxide film 35 of a conductor pattern made of arsenic-doped polycrystalline silicon and MoSi ₂ . The areas of the regions 37, 37 could be increased, and the current amplification factor could be improved. Also,
The collector lead-out electrodes 38, 38, which have a two-layer structure made of arsenic-doped polycrystalline silicon and MoSi ₂ , have low resistance due to the annealing of MoSi ₂ during high-temperature thermal oxidation treatment, compared to collector lead-out electrodes made only of arsenic-doped polycrystalline silicon. As a result, the resistance value can be significantly lowered to several Ω/□ (approximately 100 to 200 Ω/□ with arsenic-doped polycrystalline silicon alone), and high-speed operation and use in high current ranges are now possible. In fact, when examining the delay output from the ring oscillator of the I ² L manufactured in this example, the characteristic diagram shown in Figure 5 shows that the propagation delay speed (TPD) is at least 1 nsec, which is faster than the conventional I ² L. It turns out that it can be converted into In addition, a two-layer conductor pattern made of arsenic-doped polycrystalline silicon and MoSi ₂ can be used as the collector lead-out electrodes 38, 38 and jumper wiring 39, and the base lead-out Al electrode 40 has a multilayer electrode structure. ,
High integration of I ² L has become possible.

Note that the present invention is not limited to the production of I ² L as in the above embodiment, but can be similarly applied to ordinary bipolar integrated circuits, ECL ⁽ Emitter Coupled Logic), etc. A similar effect can be expected by manufacturing a normal bipolar integrated circuit or ECL.

As described in detail above, according to the present invention, a semiconductor substrate or semiconductor layer of a first conductivity type is formed of polycrystalline silicon and a refractory metal silicide containing impurities of a second conductivity type directly or through an insulating film. By performing high-temperature thermal oxidation treatment after forming a layered conductor pattern, a second conductivity type diffusion layer can be formed on a semiconductor substrate, etc., and contact resistance with the second conductivity type diffusion layer can be increased. It is possible to lower the resistance of high-melting point metal silicides and, in turn, lower the resistance of conductor patterns without causing any A thin silicon thermal oxide film can be grown, and then the silicon thermal oxide film on the exposed semiconductor substrate portion is removed and an electrode wiring material layer is deposited to make low resistance contact with the second conductivity type diffusion layer and form a sheet. It is possible to form an electrode wiring having a two-layer structure with low resistance, and also to form another electrode wiring that is mainly insulated from the electrode wiring by the silicon thermal oxide film surrounding it. Therefore, it is possible to provide a method for manufacturing a semiconductor integrated circuit that achieves both high integration and high-speed operation with a significantly shortened process.

[Brief explanation of drawings]

Figures 1 a to c are cross-sectional views showing the manufacturing process of I ² L using the conventional method, Figure 2 is a characteristic diagram showing the resistance change of a molybdenum silicide film (MoSi ₂ ) due to annealing treatment, and Figure 3 is a cross-sectional view showing the manufacturing process of I 2 L using the conventional method.
Characteristic diagrams showing changes in contact resistance between an extraction electrode made of only a MoSi ₂ film or a two-layer structure of arsenic-doped polycrystalline silicon and MoSi ₂ and a diffusion layer of the substrate, FIGS. FIG. 5 is a cross-sectional view showing the manufacturing process of I ² L in the embodiment of the present invention, and FIG. 5 is a characteristic diagram showing the delayed output by the ring oscillator of I ² L obtained in the embodiment of the present invention. 21...p-type silicon substrate, 22...n ⁺ buried layer, 23... n-type silicon epitaxial layer, 2
4...Field oxide film, 26...P ⁺ base region, 27...Injector, 29...Arsenic-doped polycrystalline silicon film, 30...Molybdenum silicide film, 32a, 32b, 32c...Silicon nitride film pattern, 33a , 33b, 33c...Conductor pattern, 35...Thick silicon thermal oxide film, 36
...Thin silicon thermal oxide film, 37,37...n ⁺
Mold collector area, 38, 38... Collector lead-out electrode, 39... Jumper wiring, 40... Base lead-out Al electrode, 41... Injector lead-out Al electrode.

Claims (1)

[Claims] 1. A polycrystalline silicon film containing impurities of a second conductivity type and a high melting point metal silicide film are sequentially deposited on a semiconductor substrate or a semiconductor layer of a first conductivity type, either directly or via an insulating film. After that, a step of selectively etching these films to form a two-layer conductor pattern,
A thick silicon thermal oxide film is grown around the two-layered conductor pattern by high-temperature thermal oxidation treatment, and a thin silicon thermal oxide film is grown on the exposed substrate or semiconductor layer, and the semiconductor is in direct contact with the conductor pattern. After forming a second conductivity type diffusion layer on the substrate or semiconductor layer and removing the thin silicon thermal oxide film on the semiconductor substrate or semiconductor layer by etching, depositing an electrode wiring material layer on the entire surface, 1. A method for manufacturing a semiconductor integrated circuit, comprising the step of forming an electrode wiring insulated by a thick silicon thermal oxide film provided around a two-layer conductor pattern. 2. The first conductive type semiconductor layer is a p-type diffusion layer, and the second conductive layer is a component of a two-layer conductor pattern.
The conductivity type of the polycrystalline silicon film is n ⁺ type, and the emitter or collector diffusion layer of the bipolar transistor is formed in the p-type diffusion layer in contact with the conductor pattern by high-temperature thermal oxidation treatment, and the p-type diffusion layer is The conductor pattern in contact with the p-type diffusion layer is an extraction electrode of the emitter or collector diffusion layer, and the conductor pattern on the insulator is a jumper wiring, and the extraction electrode and jumper wiring are connected to the extraction electrode of the p-type diffusion layer with polycrystalline silicon. 2. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit has a self-aligned structure insulated by a silicon thermal oxide film made of a high melting point metal silicide. 3 The semiconductor layer of the first conductivity type is applied to the base of the npn transistor with the I ² L gate and the emitter of the pnp transistor with the same gate into the first conductivity type region in contact with the conductor pattern of the two-layer structure by high-temperature thermal oxidation treatment. The npn of the I ² L gate is formed by diffusing second conductivity type impurities from polycrystalline silicon, which is a constituent material of the pattern.
2. The method of manufacturing a semiconductor integrated circuit according to claim 1, further comprising forming a collector of a transistor. 4 In the same semiconductor substrate, a collector diffusion layer of an I ² L npn transistor is formed by high-temperature thermal oxidation treatment of a conductive pattern, and the conductive pattern is used as an extraction electrode of the collector diffusion layer, and the same high-temperature thermal oxidation process is performed. The semiconductor according to claim 1, characterized in that an emitter or collector diffusion layer of an npn bipolar transistor formed by oxidation treatment is provided, and the conductor pattern is used as an extraction electrode of the emitter or collector diffusion layer. A method of manufacturing integrated circuits.