JPS58182273A - Manufacture of thin film semiconductor device - Google Patents
Manufacture of thin film semiconductor deviceInfo
- Publication number
- JPS58182273A JPS58182273A JP6569382A JP6569382A JPS58182273A JP S58182273 A JPS58182273 A JP S58182273A JP 6569382 A JP6569382 A JP 6569382A JP 6569382 A JP6569382 A JP 6569382A JP S58182273 A JPS58182273 A JP S58182273A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- thin film
- wiring
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000010409 thin film Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000010408 film Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000001259 photo etching Methods 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 23
- 238000005530 etching Methods 0.000 abstract description 7
- 238000009413 insulation Methods 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- JCLFHZLOKITRCE-UHFFFAOYSA-N 4-pentoxyphenol Chemical compound CCCCCOC1=CC=C(O)C=C1 JCLFHZLOKITRCE-UHFFFAOYSA-N 0.000 description 1
- 108010067035 Pancrelipase Proteins 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000001467 acupuncture Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 229940092125 creon Drugs 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 239000011669 selenium Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】
本発明は薄膜半導体装置、特に多結晶シリコンを用いた
薄膜半導体装置の製造方法に−する。DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a method of manufacturing a thin film semiconductor device, particularly a thin film semiconductor device using polycrystalline silicon.
本発明の目的は薄膜半導体装置の製造において工数を増
加させる事なく、薄膜半導体装置の特性音向上させる事
にある。An object of the present invention is to improve the characteristic sound of a thin film semiconductor device without increasing the number of steps in manufacturing the thin film semiconductor device.
近年、薄膜半導体装置を用いたスイッチングトランジス
タアレイを有する液晶表示装置がグツフィック表示が可
能であ)低消費電力である事がら情帯用機器の表示装置
として大いに注目されている。半導体薄膜としては単結
晶シリコン、多結晶シリコン、アモル7アヌシリコン、
セレン、テルル、勢が用いられるが、製造O容易さ、及
び長期信頼性から判断して、多結晶シリコンを用いる方
法が最も実用化に近い所にある。In recent years, liquid crystal display devices having switching transistor arrays using thin-film semiconductor devices have attracted much attention as display devices for consumer electronics because they are capable of graphical display and have low power consumption. Semiconductor thin films include single crystal silicon, polycrystalline silicon, amol 7 anusilicon,
Although selenium, tellurium, and silicon are used, the method using polycrystalline silicon is the closest to practical use, judging from ease of manufacture and long-term reliability.
以下図に依って評しく説明する。This will be explained in more detail below with reference to the figures.
第1図は従来の製造方法によって作られた多結晶シリコ
ンを用い友薄属半導体装置の断面図である。従来の製造
方法では半導体装置、主[M OB型半導体装置を作る
のに費するフォトエツチング工程の数音最少にする為に
半導体装置の基体となる多結晶シリコンlIlを透明絶
縁基板2上にフォトエツチングエsKよって島状に形成
し、同長結晶シリコンlIt熱酸化してゲート酸化M3
を形成する。しかる後多細晶シリプンでグーF配線4を
形成し、同ゲート配@4に自己整合してソース領域5及
びドレイシ領域6を形成する。配線間絶縁117の形成
、同絶縁展7に対す為コンタタト孔80形成、アル建起
@9の形成まてで従来の製造方法では4回のフォトエツ
チング工程ですむ。しかし、リンをドープされていなh
多結晶シリコンを酸化して形成されたシリコン酸化膜は
絶縁性が良くない事祉周知の事実である為、ゲート酸化
膜厚を厚くしなければならず、半導体装置の特性は悪く
なる。上記の欠点は従来の製造方法とは半導体装置9上
下を逆にして、リンをドープしえ多結、晶シリコンから
なるゲート配線を酸化してゲート酸化膜とすれば解消さ
れるが、従来ゲート配線に自己整合して形成されたソー
ス及びドレイン領域管形成するのにフォトエツチング工
程を要する為に従来の方法よ、91回多く、アルず配線
形成までに5回のフォトエツチング工程を必要とし、製
造コスト増になる。FIG. 1 is a sectional view of a thin metal semiconductor device using polycrystalline silicon manufactured by a conventional manufacturing method. In the conventional manufacturing method, polycrystalline silicon, which is the base of the semiconductor device, is photo-etched onto a transparent insulating substrate 2 in order to minimize the number of photo-etching steps required to make a semiconductor device. Form an island shape by etching SK, and thermally oxidize the same length crystal silicon lIt to oxidize the gate M3.
form. Thereafter, a goo F wiring 4 is formed using polycrystalline silicon, and is self-aligned with the gate wiring 4 to form a source region 5 and a dosi region 6. In the conventional manufacturing method, four photo-etching steps are required to form the inter-wiring insulation 117, to form the contact hole 80 for the insulation expansion 7, and to form the aluminum ridge @9. However, it is not doped with phosphorus.
It is a well-known fact that a silicon oxide film formed by oxidizing polycrystalline silicon has poor insulation properties, so the thickness of the gate oxide film must be increased, which deteriorates the characteristics of the semiconductor device. The above-mentioned drawbacks can be overcome by turning the semiconductor device 9 upside down and doping the semiconductor device 9 with phosphorus and oxidizing the gate wiring made of polycrystalline silicon to form a gate oxide film. Since a photo-etching process is required to form the source and drain region tubes that are self-aligned with the wiring, it requires 5 photo-etching processes to form the aluminum wiring, which is 91 times more than the conventional method. Manufacturing costs will increase.
本発明は上記の欠点を除去するに半導体装置の基体とな
る多結晶シリコン膜のエツチングとQンタクト孔の形成
を同一フォトエツチング工程で行なう事に依ってフォト
エツチング工程の数を増加する事なく、ゲート配lIを
酸化してゲート酸化膜とする構造管可能にした薄膜半導
体装置・製造方法である。jll!2図以下に零以下の
′1IIiW11半導体装置の製造方法をMIi図で示
す。リンをドープし九多結晶シリコンをフォトエツチン
グしてゲート配線10ソース領域11及びドレイン領域
12f:形成した後ダート酸化膜13を形成し、ソース
領域及びドレイン領域及びゲート配線のアル2配縁との
コンタクト部分の酸化膜を除去すると第2図に示す形状
に戒る。選択酸化法によって平担化する拳も出来る。第
3因の工程では多結晶シリコン族14を形成し、フォト
エツチングする事なく配線間絶縁l1Iisを形成する
。第4図の工程ではコンタクト孔16の形成と多結晶シ
リコン1114のエツチングを同一のフォトエツチング
工程で行なう、コンタクト孔16と多結晶シリコン族を
除去する部分の絶縁層をエツチングした後、露出した多
結晶シリコン族をクレオングッズマでエツチングする。The present invention eliminates the above-mentioned drawbacks by etching the polycrystalline silicon film serving as the base of the semiconductor device and forming Q contact holes in the same photoetching process, thereby eliminating the need to increase the number of photoetching processes. This is a thin film semiconductor device and manufacturing method that enables a structure in which a gate interconnect II is oxidized to form a gate oxide film. jll! The method for manufacturing a '1IIiW11 semiconductor device of less than zero is shown in MIi diagrams in FIG. 2 and below. After doping the phosphorus and photoetching the polycrystalline silicon to form the gate wiring 10, the source region 11 and the drain region 12f, a dirt oxide film 13 is formed to connect the source region, the drain region and the gate wiring with the Al2 interconnection. When the oxide film at the contact portion is removed, the shape shown in FIG. 2 is obtained. A flattened fist can also be created using selective oxidation. In the step of the third factor, a polycrystalline silicon group 14 is formed, and inter-wiring insulation l1Iis is formed without photoetching. In the process shown in FIG. 4, the formation of the contact hole 16 and the etching of the polycrystalline silicon 1114 are performed in the same photoetching process. Etch the crystalline silicon group with Creon Goodsma.
リンをドープした多結晶シリコンは7レオングツズマに
対してドープしない、多結晶シリコンよ)エツチング速
度が小さく3ンタクトIIOリンをドーグした多結晶シ
リコンを上記のエツチングで損う事はない。Polycrystalline silicon doped with phosphorus has a low etching rate (polycrystalline silicon, which is not doped with phosphorus), and polycrystalline silicon doped with 3-tact IIO phosphorus is not damaged by the above etching.
多結晶シリコン膜の端部17#i第5図に示す411に
熱酸化もしくけ酸化膜のデポジシ璽ンで覆い、コンタク
ト孔の多結晶シリコンlIを露出する為、反応性イオン
エツチング等異方性エツチング法によ〕酸化膜を全面に
一率にエツチングする。ソース及びドレイン領域は熱処
理によ〉広がDM (1!I型半導体装筐が形成される
。しかる後アルン配!Ilsを形成すればフォトエツチ
ングエaは従来と同じ4回であシ、ゲート酸化IIは従
来の物を比軟して大巾に改善される為比較的薄く形成す
る事が出来、MOEI型半導体装置の特性は改善される
。The end portion 17#i of the polycrystalline silicon film 411 shown in FIG. [By etching method] The oxide film is uniformly etched over the entire surface. The source and drain regions are expanded by heat treatment (DM) (1! An I-type semiconductor device is formed. After that, if Arun wiring is formed, the photo-etching process is repeated four times as in the conventional method. Since oxide II is much softer than the conventional one and is greatly improved, it can be formed relatively thin, and the characteristics of the MOEI type semiconductor device are improved.
上記の様に本発明の製造方法に依って薄膜半導体装置は
工程数を増加する事なく特性を改善する事が出来る。As described above, by using the manufacturing method of the present invention, the characteristics of a thin film semiconductor device can be improved without increasing the number of manufacturing steps.
本発明の製造方法に依りて作られる半導体装置を液晶表
示パネルに使用する場合には走査線方向に走るゲート配
線とそれに直角に走るアル々配線間の容Jliを小さく
する為、少くともゲート配線とアルミ配線の交差部はゲ
ート配線上の酸化膜を除去し2てゲート配線と多結晶シ
リコンを密着させ、フローティング状態の多結晶シリコ
ンを残す事なぐ配線聞納5iiaを残す。When using a semiconductor device manufactured by the manufacturing method of the present invention in a liquid crystal display panel, at least the gate wiring is At the intersection of the gate wiring and the aluminum wiring, the oxide film on the gate wiring is removed, and the gate wiring and the polycrystalline silicon are brought into close contact with each other, leaving a wiring gap 5iia without leaving any floating polycrystalline silicon.
以上多結晶シリコンMを半導体基体とする場合について
述べてきたが、単結晶シリコンや他の半導体材料管用い
ても同様の事が可能である。Although the case where polycrystalline silicon M is used as the semiconductor substrate has been described above, the same thing can be done using single crystal silicon or other semiconductor material tubes.
本発明の製造方法による薄膜半導体装置Fi特性におい
て優れておシ、%に液晶表示装置のスイッチングトラン
ジスタアレイとしての利用が大いに期待出来る。Since the thin film semiconductor device manufactured by the manufacturing method of the present invention has excellent Fi characteristics, it can be highly expected to be used as a switching transistor array for a liquid crystal display device.
agi図は従来の製造方法によって作られた多結晶シリ
コンを用い−ks、III半導体装置の断面図である。
第2図〜fg5鍼紘本発vAo*m半導体装置の製造方
法を示す断面−である。
1.14・・多結晶シリコン
3.13・・ゲート酸化膜
4.10・・ダート配線
5 、11・・ソース領域
6.12・φドレイン領域
7.15・自記線間絶縁膜
8,16・・コンタクト孔
9.18・・アルミ配線
以 上
出願人 株式会社−訪精工舎
5図The agi figure is a cross-sectional view of a -ks, III semiconductor device using polycrystalline silicon manufactured by a conventional manufacturing method. FIG. 2 is a cross-sectional view showing a method for manufacturing a vAo*m semiconductor device produced by fg5 Acupuncture. 1.14... Polycrystalline silicon 3.13... Gate oxide film 4.10... Dirt wiring 5, 11... Source region 6.12. φ drain region 7.15. Self-registered line insulating film 8, 16.・Contact hole 9.18... Aluminum wiring or above Applicant: Hoseikosha Co., Ltd. Figure 5
Claims (1)
・エツチングと峡牛導体薄膜上の絶縁膜にコンタクト孔
を形成するフォトエツチングが同一フォトエツチング工
程で行なわれる事を特徴とする薄膜半導体装置の製造方
法。A method for manufacturing a thin film semiconductor device, characterized in that photo etching of a semiconductor thin film serving as a base of a MOB type transistor and photo etching for forming a contact hole in an insulating film on a conductive thin film are performed in the same photo etching process.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6569382A JPS58182273A (en) | 1982-04-20 | 1982-04-20 | Manufacture of thin film semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6569382A JPS58182273A (en) | 1982-04-20 | 1982-04-20 | Manufacture of thin film semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58182273A true JPS58182273A (en) | 1983-10-25 |
Family
ID=13294345
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6569382A Pending JPS58182273A (en) | 1982-04-20 | 1982-04-20 | Manufacture of thin film semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58182273A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100451381B1 (en) * | 1998-07-30 | 2005-06-01 | 엘지.필립스 엘시디 주식회사 | Thin film transistor and its manufacturing method |
-
1982
- 1982-04-20 JP JP6569382A patent/JPS58182273A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100451381B1 (en) * | 1998-07-30 | 2005-06-01 | 엘지.필립스 엘시디 주식회사 | Thin film transistor and its manufacturing method |
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