JPH0482222A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH0482222A
JPH0482222A JP19662590A JP19662590A JPH0482222A JP H0482222 A JPH0482222 A JP H0482222A JP 19662590 A JP19662590 A JP 19662590A JP 19662590 A JP19662590 A JP 19662590A JP H0482222 A JPH0482222 A JP H0482222A
Authority
JP
Japan
Prior art keywords
tungsten
film
hole
high concentration
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19662590A
Other languages
Japanese (ja)
Inventor
Yutaka Ito
豊 伊藤
Tsurukazu Yamazaki
山崎 弦一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP19662590A priority Critical patent/JPH0482222A/en
Publication of JPH0482222A publication Critical patent/JPH0482222A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent tungsten from coming out on account of temperature change at the time of tungsten growth and heat treatment after growth, by a method wherein protrusions which tungsten has in the horizontal direction are caught in recesses of insulator. CONSTITUTION:In an SiO2 film on a conducting film 3, a hole in which the surface of the conducting film 3 is exposed is formed by a photo mask method and anisotropic dry etching. The whole body is dipped in hydrofluoric acid diluted with water. The dissolving velocity into hydrofluoric acid, of the SiO2 film containing high concentration P is high as compared with the SiO2 film containing little P, so that the SiO2 film containing high concentration P is rapidly dissolved and, recesses are formed. Tungsten 4 of a pillar type is buried in the hole by CVD method. This tungsten 4 generates protrusions 5 in the direction horizontal to the substrate l, in the recesses of the SiO2 film part containing high concentration P in the hole.

Description

【発明の詳細な説明】 産業上の利用分野 本発明Cヨ  半導体装置及びその製造方法に関するも
のであも 従来の技術 従来の半導体装置における埋め込みタングステンによる
配線構造としてζよ 第5図に示すように導電性膜3上
に形成された絶縁膜2番へ 基板lに垂直方向に導電性
膜3表面が露出するように穴を形成した後、CVD法に
より穴に柱状タングステン54を埋め込んだものがあっ
た 発明が解決しようとする課題 しかし タングステンgsio2膜や5isNa膜等の
絶縁膜と密着性が悪い上!ミ タングステンを埋め込む
穴の部分の導電性膜表面にはごく薄くではあるが自然酸
化膜が形成されておりタングステンとの密着性を低下さ
せており、タングステン成長直後の温度変化や熱処理が
加わると応力によりタングステンが導電性膜との界面か
ら剥離して上に抜けてしまt、%  熱処理温度を高く
できないという課題がありk 本発明者は以上のような
従来のタングステンによる配線を有する半導体装置の欠
点に鑑み本発明を完成するに至ったものである。
[Detailed Description of the Invention] Industrial Application Fields of the Invention The present invention relates to semiconductor devices and methods of manufacturing the same, and also relates to conventional technology.As shown in FIG. To the second insulating film formed on the conductive film 3 There is a method in which a hole is formed in a direction perpendicular to the substrate 1 so that the surface of the conductive film 3 is exposed, and then columnar tungsten 54 is embedded in the hole by the CVD method. However, the problem that this invention attempts to solve is that it has poor adhesion to insulating films such as tungsten gsio2 film and 5isNa film! A very thin natural oxide film is formed on the surface of the conductive film in the hole where tungsten is to be buried, reducing the adhesion to the tungsten. As a result, tungsten peels off from the interface with the conductive film and escapes upward.There is a problem in that the heat treatment temperature cannot be increased. In view of the above, the present invention has been completed.

本発明の目的(よ 埋め込みタングステン配線に突起を
設けることにより、はがれを防止できる半導体装置及び
その製造方法を提供することを目的とすも 課題を解決するための手段 本発明の半導体装置としてζよ 絶縁物中に基板の主面
に対して垂直方向に埋め込まれ 最上部と最下部を除い
た部分に前記基板の主面に対して水平方向に突起を有し
 最下部において導電体に接したタングステンにより形
成される配線構造を有する。
The purpose of the present invention is to provide a semiconductor device that can prevent peeling by providing protrusions on embedded tungsten wiring, and a method for manufacturing the same. Tungsten is embedded in an insulator in a direction perpendicular to the main surface of the substrate, has protrusions in a direction horizontal to the main surface of the substrate except for the top and bottom, and is in contact with the conductor at the bottom. It has a wiring structure formed by.

また本発明の半導体装置の製造方法として1表導電体上
にP(リン)を高濃度に含有する5102膜を、Pをほ
とんど含有しない5102膜で挟んで形成する工程と、
フォトマスク法と異方性ドライエッチにより、前記Pを
高濃度に含有する5102膜および前記Pをほとんど含
有しない5102膜に前記導電体表面が露出するように
穴を形成する工程と、その後ふつ化水素酸や希釈したふ
り化水素酸に浸し 前記穴部において前記Pを高濃度に
含有するSiO2の部分にくぼみを形成する工程と、C
VD法を用いて前記穴をタングステンにより埋め込んで
配線を形成する工程とを備えたものであム 作用 本発明は前記した構成により、タングステンが水平方向
に有する突起が絶縁物のくぼみにひっかかることにより
、タングステン成長時の温度変化や熱処理によって、タ
ングステンが上方に抜けることを防止することができも 実施例 以下、図面に基づいて更に詳しく説明する。
Further, as a method for manufacturing a semiconductor device of the present invention, a step of forming a 5102 film containing a high concentration of P (phosphorous) on a first conductor is sandwiched between 5102 films containing almost no P;
A step of forming a hole in the 5102 film containing a high concentration of P and the 5102 film containing almost no P by a photomask method and anisotropic dry etching so that the surface of the conductor is exposed, and then forming a hole to expose the surface of the conductor. immersing in hydrogen acid or diluted hydrofluoric acid to form a depression in the SiO2 portion containing a high concentration of P in the hole;
and a step of filling the hole with tungsten using a VD method to form a wiring.The present invention has the above-described structure, so that the protrusion that the tungsten has in the horizontal direction is caught in the recess of the insulator. However, it is possible to prevent tungsten from escaping upward due to temperature changes and heat treatment during tungsten growth.

第1図は本発明にかかる半導体装置の配線部分の部分拡
大図であも 同図において、基板1には例えばシリコン
基板を、絶縁物2には例えばSiO2膜を、導電性膜3
には例えばモリブデン、アルミ、タングステン、タング
ステンシリサイド、ポリSi膜等を用いも 絶縁物2中
に1友 最下部を導電性膜3に接し水平方向に突起5を
有する柱状タングステン4が埋め込まれていも 第2図は柱状タングステン4の最下部が導電体として導
電性膜3の代わりに半導体基板6に接している場合であ
ム 第1図、第2図においては柱状タングステン4は2カ所
において水平方向に突起5を有しているカミこの突起数
は2に限らず最低1カ所有れば良(■しかし突起数が多
いほど柱状タングステン4が上方に抜けるのを防止する
効果は太き(l第1図のような構成の配線構造は例えば
第3図(a)〜(d)のようにして作成されも第3図(
a)では 絶縁膜2上に形成された配線材料の導電性膜
3上にPをほとんど含有しないSiO2膜31、Pを高
濃度に含有するSiO2膜32、Pをほとんど含有しな
いSiO2膜33、Pを高濃度に含有するSiO2膜3
4、Pをほとんど含有しない5102膜35の順に例え
ばCVD法を用いて堆積すa 各膜の膜厚は特に規定さ
れることはない力<、  10nmから11000n程
度が望ましt℃またPを高濃度に含有するSiO2膜3
2,34のP濃度としては10”cm−”以上が望まし
しも またPをほとんど含有しないSiO2膜31,3
3.35のP濃度としては10”cm−’以下が望まし
l、1゜次に第3図(b)では 導電性膜3上の5iC
12膜31〜35にフォトマスク法と異方性ドライエッ
チにより、導電性膜3の表面が露出するまでの穴36を
形成する。穴36の上部から見た形状ζ表正方形や長方
形が望ましくt その大きさは 形状が正方形の場合0
.2ミクロンからlOミクロン角程度が望まし賎 次&へ 第3図(c)でCよ ふっ化水素酸や水等で希
釈したふつ化水素酸に浸す。このときPを高濃度に含有
するSiO2膜32.341−LPをほとんど含有しな
いSiO2膜31,33.35に比べぶつ化水素酸に対
する溶解速度が1.5倍から10倍程度速いた取 穴3
6においてPを高濃度に含有する5iOp膜32.34
が速く溶解するためくぼみ37が形成される。SiO2
膜中のP濃度を選びまたぶつ化水素酸の濃度や希釈材を
選ぶことにより、ぶつ化水素酸に対する溶解速度を制御
することが可能でくぼみ37の深さをかなり大きな範囲
で変えることができも 次に第3図(d)でj;LCVD法により穴36の中に
柱状タングステン4を埋め込a 柱状タングステン4を
埋め込むときには 選択的に穴3の中だけに形成しても
良いし基板全面に形成しても良(−このようにして埋め
込まれた柱状タングステン4は穴36の中のPを高濃度
に含有するS i 02膜32.34の部分のくぼみ3
7において基板1に対して水平方向に突起5を生じも 
このようにして、水平方向に突起5を有した絶縁物に埋
め込まれた柱状タングステン配線構造が形成されるので
あも第4図に本発明を3次元回路素子に応用した場合の
素子の部分断面図の1例を゛示す。 1層目トランジス
タ41の配線は導電性膜3で構成され 2層目トランジ
スタ42の配線は導電性膜43で構成され導電性膜3と
導電性膜43は柱状タングステン4で結合されていも 発明の詳細 な説明したよう&へ 本発明によれば タングステンが
水平方向に有する突起が絶縁物のくぼみにひっかかるこ
とにより、タングステン成長時の温度変化やその後の熱
処理によって、タングステンが上方に抜けることを防止
することができ、特に3次元回路素子のようにタングス
テンを形成した後900℃前後高温熱処理が必要な半導
体素子においてはその実用的効果は太き(−
FIG. 1 is a partially enlarged view of a wiring part of a semiconductor device according to the present invention.
For example, molybdenum, aluminum, tungsten, tungsten silicide, poly-Si film, etc. may be used.A columnar tungsten 4 having a protrusion 5 in the horizontal direction and having a lowermost portion in contact with the conductive film 3 may be embedded in the insulator 2. FIG. 2 shows the case where the lowest part of the columnar tungsten 4 is in contact with the semiconductor substrate 6 as a conductor instead of the conductive film 3. In FIG. 1 and FIG. The number of protrusions 5 is not limited to two, but it is sufficient to have at least one protrusion. For example, the wiring structure with the configuration shown in Figure 1 can be created as shown in Figures 3 (a) to (d).
In a), on the conductive film 3 of the wiring material formed on the insulating film 2, an SiO2 film 31 containing almost no P, an SiO2 film 32 containing a high concentration of P, an SiO2 film 33 containing almost no P, SiO2 film 3 containing a high concentration of
4. The 5102 film 35 containing almost no P is deposited in this order using, for example, the CVD method.The film thickness of each film is not particularly defined, but is preferably about 10 nm to 11000 nm, and the thickness is preferably 10 nm to 11000 nm. SiO2 film 3 contained in the concentration
It is desirable that the P concentration in the SiO2 films 31, 3 containing almost no P is 10"cm-" or more.
The P concentration of 3.35 is preferably 10"cm-' or less l, 1°. Next, in FIG. 3(b), 5iC on the conductive film 3
Holes 36 are formed in the 12 films 31 to 35 by a photomask method and anisotropic dry etching until the surface of the conductive film 3 is exposed. The shape of the hole 36 as seen from the top ζ Table is preferably square or rectangular t Its size is 0 if the shape is square
.. The desired size is from 2 microns to 10 microns square.C in Figure 3 (c) Soak in hydrofluoric acid or hydrofluoric acid diluted with water. At this time, the dissolution rate for hydrobutic acid is about 1.5 to 10 times faster than the SiO2 film 32.341 containing a high concentration of P-LP and the SiO2 film 31, 33.35 containing almost no LP.
5iOp film containing high concentration of P in 6 32.34
The depressions 37 are formed because of the rapid dissolution of the liquid. SiO2
By selecting the P concentration in the film, as well as the concentration of hydrobutic acid and the diluent, it is possible to control the rate of dissolution in hydrobutic acid, and the depth of the depressions 37 can be varied over a fairly large range. Next, as shown in FIG. 3(d), the columnar tungsten 4 is embedded in the hole 36 by the LCVD method.a When the columnar tungsten 4 is embedded, it may be formed selectively only in the hole 3 or over the entire surface of the substrate. (-The columnar tungsten 4 buried in this way can be formed in the depression 3 in the portion of the Si 02 film 32 and 34 containing a high concentration of P in the hole 36.
7, a protrusion 5 may be formed horizontally with respect to the substrate 1.
In this way, a columnar tungsten wiring structure embedded in an insulator having horizontal protrusions 5 is formed. Fig. 4 shows a partial cross section of a three-dimensional circuit element when the present invention is applied to it. An example of the figure is shown below. The wiring of the first layer transistor 41 is made of a conductive film 3, and the wiring of the second layer transistor 42 is made of a conductive film 43, and the conductive film 3 and the conductive film 43 are connected by a columnar tungsten 4. As explained in detail, according to the present invention, the horizontal protrusions of tungsten are caught in the depressions of the insulator, thereby preventing tungsten from slipping upward due to temperature changes during tungsten growth or subsequent heat treatment. The practical effect is particularly great for semiconductor devices, such as three-dimensional circuit devices, which require high-temperature heat treatment at around 900°C after forming tungsten (-

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例に係る半導体装置の配線部分の
部分拡大断面図 第2図は本発明の実施例に係る半導体
装置の配線部分の部分拡大断面図第3図は本発明の実施
例に係る第1図に示す半導体装置を形成するための工程
断面図 第4図は本発明を3次元回路素子に応用した場
合の断面1第5図は従来の半導体装置の配線部分の部分
拡大断面図である。 1・・・基板、2・・・絶縁物 3・・・導電性wL 
4柱状タングステン、5・・・突起 31.33.35
−Pをほとんど含まないSiO2K  32.34・・
・Pを高濃度に含有する5iOelf!、37・・・く
ぼも代理人の氏名 弁理士 粟野重孝 はか1名前 1
 図 41主伏夕/クスヲン 第 2r!!J 第 図 〜 城 一プ 寸 rつ 第 図
FIG. 1 is a partially enlarged sectional view of a wiring portion of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a partially enlarged sectional view of a wiring portion of a semiconductor device according to an embodiment of the present invention. FIG. 3 is a partially enlarged sectional view of a wiring portion of a semiconductor device according to an embodiment of the present invention. 4 is a cross-sectional view of the process for forming the semiconductor device shown in FIG. 1 according to an example. FIG. 4 is a cross-section when the present invention is applied to a three-dimensional circuit element. FIG. FIG. 1...Substrate, 2...Insulator 3...Conductivity wL
4 columnar tungsten, 5... protrusions 31.33.35
-SiO2K containing almost no P 32.34...
・5iOelf containing a high concentration of P! , 37...Name of Kubomo's agent Patent attorney Shigetaka Awano Haka 1 name 1
Figure 41 Lord Fusyu/Kusuwon 2nd r! ! J Diagram ~ Joichipu Dimension Diagram

Claims (4)

【特許請求の範囲】[Claims] (1)絶縁物中に基板の主面に対して垂直方向に埋め込
まれ最上部と最下部を除いた部分に前記基板の主面に対
して水平方向に突起を有し、最下部において導電体に接
したタングステンにより形成される配線構造を有するこ
とを特徴とする半導体装置。
(1) It is embedded in an insulator in a direction perpendicular to the main surface of the substrate, and has protrusions in the horizontal direction with respect to the main surface of the substrate except for the top and bottom, and a conductor at the bottom. 1. A semiconductor device characterized by having a wiring structure formed of tungsten in contact with tungsten.
(2)請求項1記載の導電体が導電性膜あるいは半導体
基板であることを特徴とする半導体装置。
(2) A semiconductor device, wherein the conductor according to claim 1 is a conductive film or a semiconductor substrate.
(3)導電体上にP(リン)を高濃度に含有するSiO
_2膜を、Pをほとんど含有しないSiO_2膜で挟ん
で形成する工程と、フォトマスク法と異方性ドライエッ
チにより、前記Pを高濃度に含有するSiO_2膜およ
び前記Pをほとんど含有しないSiO_2膜に前記導電
体表面が露出するように穴を形成する工程と、その後ふ
っ化水素酸や希釈したふっ化水素酸に浸し前記穴部にお
いて前記Pを高濃度に含有するSiO_2の部分にくぼ
みを形成する工程と、CVD法を用いて前記穴をタング
ステンにより埋め込んで配線を形成する工程とを備えた
半導体装置の製造方法。
(3) SiO containing a high concentration of P (phosphorus) on the conductor
A process of sandwiching the _2 film between two SiO_2 films containing almost no P, and a photomask method and anisotropic dry etching are used to form the SiO_2 film containing a high concentration of P and the SiO_2 film containing almost no P. A step of forming a hole so that the surface of the conductor is exposed, and then immersing it in hydrofluoric acid or diluted hydrofluoric acid to form a depression in the portion of the SiO_2 containing a high concentration of P in the hole portion. A method for manufacturing a semiconductor device, comprising: a step of filling the hole with tungsten using a CVD method to form a wiring.
(4)請求項3記載の導電体が導電性膜あるいは半導体
基板であることを特徴とする半導体装置の製造方法。
(4) A method for manufacturing a semiconductor device, wherein the conductor according to claim 3 is a conductive film or a semiconductor substrate.
JP19662590A 1990-07-24 1990-07-24 Semiconductor device and manufacture thereof Pending JPH0482222A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19662590A JPH0482222A (en) 1990-07-24 1990-07-24 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19662590A JPH0482222A (en) 1990-07-24 1990-07-24 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0482222A true JPH0482222A (en) 1992-03-16

Family

ID=16360874

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19662590A Pending JPH0482222A (en) 1990-07-24 1990-07-24 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH0482222A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007059796A (en) * 2005-08-26 2007-03-08 Matsushita Electric Works Ltd Manufacturing method of pierced hole interconnect line
JP2012506144A (en) * 2008-10-15 2012-03-08 オー・アー・セー・マイクロテック・アクチボラゲット Method for making via wiring
JP2016006857A (en) * 2014-05-30 2016-01-14 株式会社半導体エネルギー研究所 Semiconductor device, manufacturing method of the same and electronic apparatus

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007059796A (en) * 2005-08-26 2007-03-08 Matsushita Electric Works Ltd Manufacturing method of pierced hole interconnect line
JP4581915B2 (en) * 2005-08-26 2010-11-17 パナソニック電工株式会社 Manufacturing method of through-hole wiring
JP2012506144A (en) * 2008-10-15 2012-03-08 オー・アー・セー・マイクロテック・アクチボラゲット Method for making via wiring
US8742588B2 (en) 2008-10-15 2014-06-03 ÅAC Microtec AB Method for making via interconnection
JP2016006857A (en) * 2014-05-30 2016-01-14 株式会社半導体エネルギー研究所 Semiconductor device, manufacturing method of the same and electronic apparatus
US10229906B2 (en) 2014-05-30 2019-03-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including insulating film having opening portion and conductive film in the opening portion

Similar Documents

Publication Publication Date Title
JPS58210634A (en) Preparation of semiconductor device
JPS6041231A (en) Method of producing integrated circuit structure using replica patterning
JPH01175260A (en) Manufacture of insulated-gate field-effect transistor
JPH0482222A (en) Semiconductor device and manufacture thereof
JPS59232437A (en) Manufacture of semiconductor device
JPH05849B2 (en)
JPH0447980B2 (en)
JPS59168640A (en) Manufacture of semiconductor device
JPH0447979B2 (en)
JPH02205339A (en) Manufacture of semiconductor device
JPS6242522A (en) Manufacture of semiconductor device
JP3111961B2 (en) Method for manufacturing semiconductor device
JPH0427703B2 (en)
JPH0555455A (en) Manufacture of semiconductor device
JPS6151940A (en) Wiring structure of semiconductor device
JPH04109654A (en) Semiconductor device and manufacture thereof
JPH0334322A (en) Manufacture of semiconductor device
JPH0797583B2 (en) Method for forming interlayer insulating film
JPS62222654A (en) Manufacture of semiconductor device
JPS63170922A (en) Wiring method
JPH0353519A (en) Manufacture of semiconductor device
JPS62112345A (en) Manufacture of semiconductor device
JPH04127425A (en) Manufacture of semiconductor integrated circuit
JPH04134858A (en) Manufacture of semiconductor memory device
JPS61147550A (en) Manufacture of semiconductor device