JPH0353519A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0353519A
JPH0353519A JP18941289A JP18941289A JPH0353519A JP H0353519 A JPH0353519 A JP H0353519A JP 18941289 A JP18941289 A JP 18941289A JP 18941289 A JP18941289 A JP 18941289A JP H0353519 A JPH0353519 A JP H0353519A
Authority
JP
Japan
Prior art keywords
polycrystalline silicon
contact hole
phosphorus
silicon film
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18941289A
Other languages
Japanese (ja)
Other versions
JP2817230B2 (en
Inventor
Nobuyasu Kitaoka
信恭 北岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18941289A priority Critical patent/JP2817230B2/en
Publication of JPH0353519A publication Critical patent/JPH0353519A/en
Application granted granted Critical
Publication of JP2817230B2 publication Critical patent/JP2817230B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To make it possible to fill up a contact hole with polycrystalline silicon in an excellent reproducible manner by a method wherein, after the contact hole has been filled up with a conductive polycrystalline silicon film and an undoped polycrystalline silicon film, phosphorus is doped on the non- doped polycrystalline silicon film excluding the inside of the contact hole, and then an etching treatment is conducted. CONSTITUTION:First, an N<+> diffusion layer 12 is at least selectively formed on a P-type semiconductor substrate 11. A silicon oxide film 13 is coated using an oxide film vapor growth method, and a contact hole is perforated. Then, a polycrystalline silicon film is coated, and phosphorus is added by thermal diffusion. Then, after the contact hole has been filled up by coating an undoped polycrystalline silicon film 15, phosphorus is implanted by conducting an ion implanting method under the condition wherein phosphorus is not added to the polycrystalline silicon located inside the contact hole. Then, the polycrystalline silicon films 14 and 15 in the contact hole are left, and the polycrystalline silicon films 17 and 18 on the other region are removed. Then, an Al wiring layer 16 is formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特にコンタクト
ホールの埋込み方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of burying a contact hole.

〔従来の技術〕[Conventional technology]

半導体装置を微細化する手段の一つとして、コンタクト
ホールを多結晶シリコンあるいは高融点金属を用いて埋
込み平坦化するという方法がある. 多結晶シリコンを用いた従来技術を第3図(a),(b
)を参照して説明する。
One of the methods for miniaturizing semiconductor devices is to bury and planarize contact holes using polycrystalline silicon or high-melting point metal. Conventional technology using polycrystalline silicon is shown in Figures 3(a) and (b).
).

第3図(a)に示すように、P型半導体基板1(シリコ
ン》にN+拡散層2を少なくとも選択的に形成する.気
相成長法によるシリコン酸化膜3を被着後、コンタクト
ホールを開ける.次に多結晶シリコンを被着し、熱拡散
によりリンを添加し導電性多結晶シリコンwA4を形或
する。次にノンドープ多結晶シリコン膜5を被着する。
As shown in FIG. 3(a), an N+ diffusion layer 2 is at least selectively formed on a P-type semiconductor substrate 1 (silicon). After a silicon oxide film 3 is deposited by vapor phase growth, a contact hole is opened. Next, polycrystalline silicon is deposited, and phosphorus is added by thermal diffusion to form conductive polycrystalline silicon wA4.Next, a non-doped polycrystalline silicon film 5 is deposited.

次に、第3図(b)に示すように、異方性ドライエッチ
ング法により、コンタクトホール内の多結晶シリコン膜
4.5は残し、そ他の領域の多結晶シリコンを除去する
.次にAJ2配線6を形成する。
Next, as shown in FIG. 3(b), by anisotropic dry etching, the polycrystalline silicon film 4.5 in the contact hole is left and the polycrystalline silicon in other regions is removed. Next, the AJ2 wiring 6 is formed.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のコンタクトホール埋込方法は異方性ドラ
イエッチング法により多結晶シリコン膜をエッチングす
るが、被着した多結晶シリコン膜の膜厚のばらつきや異
方性ドライエッチングのエッチング速度のばらつきによ
り半導体基板内の場所によってはオーバーエッチになる
ところがある.そのような処ではコンタクトホール内に
は埋込むべき多結晶シリコンが残らず、急峻な段差が生
じ、配線層を形或するとき、第4図に示すように、配線
の段切れが生じるという欠点がある。
In the conventional contact hole filling method described above, a polycrystalline silicon film is etched using an anisotropic dry etching method, but due to variations in the thickness of the deposited polycrystalline silicon film and variations in the etching rate of the anisotropic dry etching, Overetching may occur depending on the location within the semiconductor substrate. In such a place, there is no polycrystalline silicon to be filled in the contact hole, resulting in a steep step, and when forming the wiring layer, the disadvantage is that the wiring layer breaks as shown in Figure 4. There is.

本発明の目的は、多結晶シリコンでコンタクトホールを
再現性よく埋込むことのできる半導体装置の製造方法を
提供することにある. 〔課題を解決するための手段〕 本発明の半導体装置の製造方法は、半導体基板の一主面
上にコンタクトホールを有する絶縁膜を形成したのち、
第1の多結晶シリコン膜を前記コンタクトホールを埋込
まない膜厚で被着する工程と、前記第1の多結晶シリコ
ン膜にリンを添加する工程と、前記第1の多結晶シリコ
ン膜上に第2の多結晶シリコン膜を前記コンタクトホー
ルを埋込む膜厚で被着する工程と、前記コンタクトホー
ル内部を除き前記第2の多結晶シリコン膜にリンを添加
する工程と、コンタクトホール内部以外のリン添加され
た前記第1の多結晶シリコン膜とリン添加された前記第
2の多結晶シリコン膜とを除去する工程とを含むという
ものである。
An object of the present invention is to provide a method for manufacturing a semiconductor device that allows contact holes to be filled with polycrystalline silicon with good reproducibility. [Means for Solving the Problems] The method for manufacturing a semiconductor device of the present invention includes forming an insulating film having a contact hole on one main surface of a semiconductor substrate, and then
depositing a first polycrystalline silicon film to a thickness that does not fill the contact hole; adding phosphorus to the first polycrystalline silicon film; a step of depositing a second polycrystalline silicon film to a thickness that fills the contact hole; a step of adding phosphorus to the second polycrystalline silicon film except for the inside of the contact hole; The method includes a step of removing the first polycrystalline silicon film doped with phosphorus and the second polycrystalline silicon film doped with phosphorus.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)〜(C)は本発明の第1の実施例を説明す
るための主な工程順に示した半導体チップの断面図であ
る。
FIGS. 1A to 1C are cross-sectional views of a semiconductor chip shown in the order of main steps for explaining a first embodiment of the present invention.

まず、第1図(a)に示すように、P型半導体基板11
にN+拡散層12を少なくとも選択的に形成する.気相
酸化膜或長法によりシリコン酸化膜13を1.0μn被
着し、1.0μmX1.0μmの開口径のコンタクトホ
ールを開ける.次に多結晶シリコン膜を厚さ200nm
被着し、熱拡敗によりリンを添加する.N+拡散層12
と後工程で形成する配線層とを低抵抗に接続するためで
ある.このようにして形成された導電性多結晶シリコン
膜14は、前述のコンタクトホールと下地のN+拡散層
12の表面を覆うのみでコンタクトホールは埋込んでい
ない。
First, as shown in FIG. 1(a), a P-type semiconductor substrate 11
The N+ diffusion layer 12 is at least selectively formed. A silicon oxide film 13 of 1.0 .mu.m is deposited by a vapor phase oxide film lengthening method, and a contact hole with an opening diameter of 1.0 .mu.m x 1.0 .mu.m is made. Next, apply a polycrystalline silicon film to a thickness of 200 nm.
It adheres and phosphorus is added through thermal expansion. N+ diffusion layer 12
This is to provide a low-resistance connection between the wire and the wiring layer that will be formed in a later process. The conductive polycrystalline silicon film 14 thus formed only covers the aforementioned contact hole and the surface of the underlying N+ diffusion layer 12, but does not fill the contact hole.

次に、第1図(b)に示すように、ノンドーブ多結晶シ
リコン膜15を厚さ800nm被着してコンタクトホー
ルを埋込んだのち、イオン注入法により、リンがコンタ
クト内の多結晶シリコンには添加されない条件、この場
合は550keV,l X I O 16crs−2で
リンを注入する.17はリンドープ多結晶シリコン膜、
18は熱拡散によりリンが添加された領域(14〉にさ
らに、イオン注入でリンが添加された高濃度のリンドー
プ多結晶シリコン膜である。
Next, as shown in FIG. 1(b), a non-doped polycrystalline silicon film 15 is deposited to a thickness of 800 nm to fill the contact hole, and then ion implantation is performed to inject phosphorus into the polycrystalline silicon in the contact. In this case, phosphorus is injected at 550 keV and 16 crs-2. 17 is a phosphorus-doped polycrystalline silicon film;
Reference numeral 18 denotes a highly concentrated phosphorus-doped polycrystalline silicon film in which phosphorus is added by ion implantation to the region (14) to which phosphorus is added by thermal diffusion.

次に、第1図(c)に示すように、フッ酸と硝酸との混
合液を用いてコンタクトホール内の多結晶シリコン14
.15は残し、それ以外の領域の多結晶シリコン17.
18を除去する。次に、Affi配線層16を形成する
Next, as shown in FIG. 1(c), a mixture of hydrofluoric acid and nitric acid is used to remove the polycrystalline silicon 14 in the contact hole.
.. 15 is left and the other areas are polycrystalline silicon 17.
Remove 18. Next, an Affi wiring layer 16 is formed.

リン濃度の高い多結晶シリコンはリン濃度の低い多結晶
シリコンよりもフッ酸と硝酸との混合液に対しエッチン
グ速度が速いので、ノンドープ多結晶シリコンをコンタ
クトホール内に確実に残すことができ、多結晶シリコン
が埋込れたコンタクトホールを安定して製造できる。
Polycrystalline silicon with a high phosphorus concentration is etched faster in a mixture of hydrofluoric acid and nitric acid than polycrystalline silicon with a low phosphorus concentration, so non-doped polycrystalline silicon can be reliably left in the contact hole. Contact holes filled with crystalline silicon can be stably manufactured.

本発明の第2の実施例を第2図(a)〜(c)を参照し
て説明する。
A second embodiment of the present invention will be described with reference to FIGS. 2(a) to 2(c).

まず、第2図(a)に示すように、P型半導体基板21
にN+拡散層22を形或する。気相酸化膜或長法により
酸化シリコン膜23を1.0μm被着し、1.0μmX
1.0μmの開口径のコンタクトホールを開ける.次に
多結晶シリコンを200nm被着し、熱拡散によりリン
を添加する。
First, as shown in FIG. 2(a), a P-type semiconductor substrate 21
An N+ diffusion layer 22 is formed therein. A silicon oxide film 23 of 1.0 μm is deposited by a vapor phase oxide film lengthening method, and
Drill a contact hole with an opening diameter of 1.0 μm. Next, 200 nm of polycrystalline silicon is deposited, and phosphorus is added by thermal diffusion.

次にノンドープ多結晶シリコン膜25を800nm被着
する。ここまでは第1の実施例と同様である.次にイオ
ン注入法により300keV,I X 1 0 16c
m−2の条件でリンを注入する。27はリンが注入され
た多結晶シリコン膜、25はリンが添加されていない多
結晶シリコン膜である.次に、第2図(b)に示すよう
に、フッ酸と硝酸との混合液でリン添加された多結晶シ
リコン膜27を除去する。さらにイオン注入法により、
コンタクト内にはリンが添加されない条件で、この場合
は300keV,IXIO”Cal−2でリンを注入す
る。28は熱拡散によりリンが添加された領域にさらに
、イオン注入でリンが添加された高濃度のリンドープ多
結晶シリコン膜である.次に、第2図(C)に示すよう
に、フッ酸と硝酸との混合液を用いてコンタクトホール
内の多結晶シリコン14.15は残し、それ以外の領域
の多結晶シリコン27.28を除去する。次にAf配線
層26を形成する. リン濃度の高い多結晶シリコンはリン濃度の低い多結晶
シリコンよりもフッ酸と硝酸との混合液に対し、エッチ
ング速度が速いということを利用し、また、リン添加す
る工程とリン添加された多結晶シリコンを除去する工程
とを複数回くり返すことにより多結晶シリコンが埋込れ
たコンタクトホールをより安定して製造できる。
Next, a non-doped polycrystalline silicon film 25 of 800 nm is deposited. The process up to this point is the same as the first embodiment. Next, by ion implantation method, 300 keV, I
Phosphorus is injected under conditions of m-2. 27 is a polycrystalline silicon film doped with phosphorus, and 25 is a polycrystalline silicon film to which phosphorus is not added. Next, as shown in FIG. 2(b), the polycrystalline silicon film 27 doped with phosphorus is removed using a mixed solution of hydrofluoric acid and nitric acid. Furthermore, by ion implantation method,
In this case, phosphorus is implanted at 300 keV and IXIO"Cal-2 under the condition that phosphorus is not added into the contact. 28 is a region where phosphorus is added by thermal diffusion, and a high temperature region where phosphorus is added by ion implantation is added. Next, as shown in Figure 2 (C), a mixed solution of hydrofluoric acid and nitric acid is used to leave the polycrystalline silicon 14 and 15 in the contact hole, and to remove the remaining polycrystalline silicon. The polycrystalline silicon 27, 28 in the region is removed.Next, the Af wiring layer 26 is formed.Polycrystalline silicon with a high phosphorus concentration is more resistant to a mixed solution of hydrofluoric acid and nitric acid than polycrystalline silicon with a low phosphorus concentration. By taking advantage of the high etching speed and repeating the process of adding phosphorus and removing the phosphorus-added polycrystalline silicon multiple times, the contact hole filled with polycrystalline silicon can be made more stable. It can be manufactured by

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、コンタクトホールを導電
性多結晶シリコン膜とノンドーブ多結晶シリコン膜とで
埋込んだのち、コンタクトホール内を除き前述のノンド
ープ多結晶シリコン膜にリンをドーピングしたのちエッ
チングすることにより、リンが高濃度に添加された多結
晶シリコンは、リンが低濃度に添加された多結晶シリコ
ンあるいは不純物が添加されていない多結晶シリコンに
比較し、fヒ学薬品たとえば、フッ酸と硝酸との混合液
に対してエッチング速度が速いことを利用して、多結晶
シリコンが埋込れたコンタクトホールを有する半導体装
置を制御性よく製造できる効果がある.
As explained above, in the present invention, after a contact hole is filled with a conductive polycrystalline silicon film and a non-doped polycrystalline silicon film, the non-doped polycrystalline silicon film is doped with phosphorus except inside the contact hole, and then etched. By doing this, polycrystalline silicon doped with a high concentration of phosphorus is more susceptible to chemicals such as hydrofluoric acid than polycrystalline silicon doped with a low concentration of phosphorus or polycrystalline silicon with no impurities. Utilizing the high etching rate of a mixed solution of nitrate and nitric acid, semiconductor devices having contact holes filled with polycrystalline silicon can be manufactured with good controllability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(c)は本発明の第1の実施例を説明す
るための主な工程順に配置した半導体チップの断面図、
第2図(a)〜(C)は本発明の第2の実施例を説明す
るための主な工程順に配置した半導体チップの断面図、
第3図(a),(b)は従来の半導体装置の製造方法を
説明するための主な工程順に配置した半導体チップの断
面図、第4図は従来例の欠点を説明するための半導体チ
ップの断面図である. 1.11.21・・・P型半導体基板、2.12.22
・・・N+拡散層、3.13.23・・・シリコン酸化
膜、4,14.24・・・導電性多結晶シリコン膜、5
.15.25・・・ノンドープ多結晶シリコン膜、6,
16.26・・・Ajl配線、17,27,18,28
.29・・・リンドープ多結晶シリコン膜。
FIGS. 1(a) to 1(c) are cross-sectional views of semiconductor chips arranged in the order of main steps for explaining the first embodiment of the present invention;
FIGS. 2(a) to (C) are cross-sectional views of semiconductor chips arranged in the order of main steps for explaining a second embodiment of the present invention;
3(a) and 3(b) are cross-sectional views of semiconductor chips arranged in the order of main steps to explain the conventional manufacturing method of semiconductor devices, and FIG. 4 is a cross-sectional view of the semiconductor chip to explain the drawbacks of the conventional example. This is a cross-sectional view. 1.11.21...P-type semiconductor substrate, 2.12.22
... N+ diffusion layer, 3.13.23 ... silicon oxide film, 4, 14.24 ... conductive polycrystalline silicon film, 5
.. 15.25...Non-doped polycrystalline silicon film, 6,
16.26...Ajl wiring, 17, 27, 18, 28
.. 29...Phosphorus-doped polycrystalline silicon film.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板の一主面上にコンタクトホールを有する絶縁
膜を形成したのち、第1の多結晶シリコン膜を前記コン
タクトホールを埋込まない膜厚で被着する工程と、前記
第1の多結晶シリコン膜にリンを添加する工程と、前記
第1の多結晶シリコン膜上に第2の多結晶シリコン膜を
前記コンタクトホールを埋込む膜厚で被着する工程と、
前記コンタクトホール内部を除き前記第2の多結晶シリ
コン膜にリンを添加する工程と、コンタクトホール内部
以外のリン添加された前記第1の多結晶シリコン膜とリ
ン添加された前記第2の多結晶シリコン膜とを除去する
工程とを含むことを特徴とする半導体装置の製造方法。
forming an insulating film having a contact hole on one main surface of the semiconductor substrate, and then depositing a first polycrystalline silicon film to a thickness that does not fill the contact hole; a step of adding phosphorus to the film; a step of depositing a second polycrystalline silicon film on the first polycrystalline silicon film to a thickness that fills the contact hole;
a step of adding phosphorus to the second polycrystalline silicon film except inside the contact hole; and the first polycrystalline silicon film doped with phosphorus and the second polycrystalline silicon film doped with phosphorus outside the inside of the contact hole. 1. A method for manufacturing a semiconductor device, the method comprising: removing a silicon film.
JP18941289A 1989-07-21 1989-07-21 Method for manufacturing semiconductor device Expired - Fee Related JP2817230B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18941289A JP2817230B2 (en) 1989-07-21 1989-07-21 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18941289A JP2817230B2 (en) 1989-07-21 1989-07-21 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0353519A true JPH0353519A (en) 1991-03-07
JP2817230B2 JP2817230B2 (en) 1998-10-30

Family

ID=16240837

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18941289A Expired - Fee Related JP2817230B2 (en) 1989-07-21 1989-07-21 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2817230B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030001642A (en) * 2001-06-25 2003-01-08 주식회사 하이닉스반도체 Method for forming the contact plug of semiconductor device
US9254993B2 (en) 2007-11-14 2016-02-09 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V. Method for connecting a precious metal surface to a polymer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030001642A (en) * 2001-06-25 2003-01-08 주식회사 하이닉스반도체 Method for forming the contact plug of semiconductor device
US9254993B2 (en) 2007-11-14 2016-02-09 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V. Method for connecting a precious metal surface to a polymer

Also Published As

Publication number Publication date
JP2817230B2 (en) 1998-10-30

Similar Documents

Publication Publication Date Title
JPS58210634A (en) Preparation of semiconductor device
US5453395A (en) Isolation technology using liquid phase deposition
US4334348A (en) Retro-etch process for forming gate electrodes of MOS integrated circuits
US4318759A (en) Retro-etch process for integrated circuits
JPH0353519A (en) Manufacture of semiconductor device
JPS6362107B2 (en)
JP2874234B2 (en) Method for manufacturing semiconductor device
JPS5923544A (en) Manufacture of semiconductor device
JP2517751B2 (en) Method for manufacturing semiconductor device
KR0179555B1 (en) Isolation method of semiconductor device
JPH11214512A (en) Manufacture of semiconductor device
JPS58200554A (en) Manufacture of semiconductor device
KR0150672B1 (en) Forming method for capacitor of semiconductor memory device
JP2543192B2 (en) Semiconductor device and manufacturing method thereof
JP2982282B2 (en) Semiconductor device and manufacturing method thereof
JPH0482222A (en) Semiconductor device and manufacture thereof
JP2985218B2 (en) Semiconductor device and manufacturing method thereof
JPS63170922A (en) Wiring method
JPH0620989A (en) Contact hole formation
JPS5837991B2 (en) Manufacturing method of semiconductor device
JPH021922A (en) Manufacture of semiconductor device
JPS586135A (en) Manufacture of semiconductor device
JPH01158752A (en) Wiring forming method
JPS63181356A (en) Manufacture of semiconductor device
JPH0221657A (en) Manufacture of semiconductor storage device

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees