JP2517751B2 - Method for manufacturing semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which element isolation is performed using a groove.

2. Description of the Related Art In recent years, element isolation methods for embedding an insulator in a groove have been researched and developed. However, when the aspect ratio of the groove (depth of groove / width of groove) becomes larger than 1/2, when an insulator is embedded in the groove, a slit is generated and the insulator can be embedded evenly in the groove. could not. Therefore, the following method has been used to eliminate the slit.

FIG. 3 is a process diagram of element isolation in which an insulator is embedded in a conventional groove used to eliminate a slit. An oxide film 2 of about 50 nm and a semiconductor film 3 of about 150 nm are formed on the semiconductor substrate 1. Next, the groove 4 is formed in the element isolation region of the semiconductor substrate 1.
(Aspect ratio is 1/2 or more) is formed (see FIG. 3a). CV of the first insulating film 5 by a film thickness of about the depth of the groove 4
Deposit using method D. At this time, the weak portion 7 of the first insulator 5 and the cavity 8 are formed. Next, in order to flatten the surface of the semiconductor substrate 1, the first flattening material 6 is applied.
(See FIG. 3b). The first insulating film 5 and the first planarizing material 6 are etched at the same etching rate, deeper than the total film thickness of the oxide film 2 and the semiconductor film 3, and to a degree not exceeding 1/2 of the minimum groove width a. It is necessary to dig x ₁ from the surface. That is, as shown in FIG. 3c, it is necessary that about 200 nm <x ₁ <a / 2. Then, the depression 9 is formed. In order to remove the depression 9, the second insulating film 10 is formed with a film thickness of ₁ x CVD.
It is deposited using a method. Next, in order to make the surface of the semiconductor substrate 1 flat, a second flattening material 11 is applied (see FIG. 3d). The second insulating film 10 and the second planarizing material 11 are dug at the same etching rate until the height becomes the same as that of the oxide film 2 (see FIG. 3e). When the semiconductor film 3 and the oxide film 2 are removed, the first insulating film 5 and the second insulating film 5 are formed at the same height as the semiconductor substrate 1.
The insulating film 10 of FIG.
reference). Below, the dug amount x _{1 of} the first insulating film 5 is x ₁ > a /
The case of 2 and x ₁ <(total film thickness of oxide film 2 and semiconductor film 3) will be described.

First, x ₁ > a / 2 will be described with reference to FIG. First
Of the insulating film 5 and the first planarizing material 7 at the same etching rate from the surface of the semiconductor substrate 1 (total film thickness of the oxide film 2 and the semiconductor film 3) <x ₁ <a / 2, where x ₂ > a Fig. 4c shows the case of digging down by / 2. At this time, the depression 9 is formed. A second insulating film 10 is formed to remove the depression 9.
deposited using only the CVD method of the membrane Atsubun x _2. At this time, x ₂ > a
Because of / 2, the weak portion 12 of the second insulating film 10 and the cavity 13 are formed. Next, in order to flatten the surface of the semiconductor substrate 1, a second
The flattening material 11 is applied (see FIG. 4d). The second insulating film 10 and the second planarizing material 11 are dug at the same speed until the height becomes the same as that of the oxide film 2. At this time, a hollow 14 is formed by the cavity 13. (See Figure 4e). When the semiconductor film 3 and the oxide film 2 are removed, the trench 4 can be filled with the first insulating film 5 and the second insulating film 10, but it cannot be made flat due to the recess 14 (see FIG. 4f).

Next, x ₁ <(total film thickness of oxide film 2 and semiconductor film 3) will be described with reference to FIG. When the first insulating film 5 and the first planarizing material 7 are dug by the same etching rate from the surface of the semiconductor substrate 1 (total film thickness of the oxide film 2 and the semiconductor film 3) <x ₁ <a / 2, x ₃ FIG. 5c shows a case where the depth is dug only by <(total film thickness of oxide film 2 and semiconductor film 3). At this time, the weak portion 7 of the first insulating film 5 and the cavity 8 remain in the groove 4 as they are. Next, the second insulating film 10 is deposited using only CVD method film Atsubun of x _3. In order to flatten the surface of the semiconductor substrate 1, the second flattening material 11 is applied (see FIG. 5d).
The second insulating film 10 and the second planarizing material 11 are dug at the same etching rate until the height becomes the same as the oxide film 2. At this time, the depression 15 is formed (see FIG. 5e). When the semiconductor film 3 and the oxide film 2 are removed, the trench 4 can be filled with the first insulating film 5 and the second insulating film 10, but the recess 15 is formed.
Cannot be flattened due to the existence of (see FIG. 5f).

However, according to such a configuration, there is a problem that it is difficult to bury the first insulating film and the second insulating film at the same height as the semiconductor substrate evenly in the groove.

The problems described above occur due to the following reasons: (1) Since the total thickness of the first and second insulating films deposited on the semiconductor substrate is large, the film thickness variation during deposition is large and the etching variation is large. (2) Since the etching end points of the first insulating film and the first planarizing material must be (total film thickness of the oxide film 2 and the semiconductor film 3) <x ₁ <a / 2, the etching control is performed. Is difficult. The minimum groove width a
Becomes smaller, making this etching more difficult to control.

The present invention has been tried in view of the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device in which an insulating film or the like is formed in a groove at the same height as a semiconductor substrate and can be buried flat. To do.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a step of forming a groove in an element isolation region of a semiconductor substrate, and a step of forming the groove so that the first filling materials do not associate with each other inside the groove. Depositing one embedding material on the semiconductor substrate;
After the step of depositing the first filling material, a step of filling a fluid substance in the groove in which the first filling material is deposited, and a step of filling the fluid substance in the groove, and The step of etching the first filling material to leave the first filling material on the bottom and side surfaces of the groove, and the step of leaving the first filling material on the bottom and side surfaces of the groove, After the step of removing the fluid substance remaining inside and the step of removing the fluid substance, a second filling material is deposited in the groove left on the bottom surface and the side surface of the first filling material. Forming a cavity surrounded by the first filling material and the second filling material in the groove,
The method has a step of forming a planarizing material on the second filling material, and a step of etching the second filling material and the planarizing material, and filling the first and second filling materials in the groove. It is characterized by that.

Action The present invention makes it easy to dig down the first burying material because the thickness of the first burying film is reduced by the above configuration. In addition, although the aspect ratio of the groove is increased, a cavity is not formed inside the groove so that no slit is generated, and the first and second filling materials are formed in the groove at the same height as the semiconductor substrate.
Can be embedded flat.

Example 1 Example 1 FIG. 1 is a cross-sectional view showing a process of element isolation using a groove in a first example of the present invention. The first embodiment will be described below with reference to FIG.

About 50 nm thermal oxide film 2 on p-type silicon substrate 1 and about
A 150 nm poly-Si film 3 is formed as a surface protection film. Next, a groove 4 having a constant groove depth of 1000 nm and a minimum groove width of 600 nm is formed in the element isolation region of the silicon substrate 1 (see FIG. 1a). A first insulating film 20 having a thickness of 250 nm is deposited by the CVD method (see FIG. 1b). Next, the first insulating film 20 is subjected to anisotropic etching of 400 nm so that the side surface of the groove of the silicon substrate 1 is not exposed (see FIG. 1c). Next, the second insulating film
The same CVD oxide film as that of the first insulating film 20 is deposited as 21 to 1000 nm. At this time, the cavity 22 is formed by the first and second insulating films 20 and 21. After that, a resist film is applied as the flattening material 6 so that the surface of the silicon substrate 1 becomes flat (FIG. 1 d).
reference). The second insulating film 21 and the planarizing material 6 are etched at the same etching rate so as to have the same height as the surface of the silicon substrate 1, that is, about 1200 nm. Finally, when the poly-Si film 3 and the thermal oxide film 2 which are the surface protection films are removed, a cavity 22 is formed in the groove 4, and the groove 4 is flattened by the first insulating film 20 and the second insulating film 21. It becomes embedded (see FIG. 1e).

The use of this embodiment makes it easier to dig down the first insulating film 20 because the first buried film 20 is thinner than in the conventional example. Further, although the aspect ratio of the groove 4 becomes large, a slit is not generated due to the formation of a cavity inside the groove.
The insulating film can be embedded in the groove evenly. The defective rate due to disconnection or short circuit of the wiring formed in the subsequent wiring process was reduced.

In addition, since the side surface of the groove 4 of the silicon substrate 1 is not exposed when the first insulating film 20 is etched in the present embodiment, contamination and damage due to the etching or the like can be prevented.

Embodiment 2 FIG. 2 is a sectional view showing a process of element isolation using a groove in the second embodiment of the present invention. The second embodiment will be described below with reference to FIG.

Since the steps up to forming the groove 4 in the element isolation region are the same as those in the first embodiment, they are omitted. A 250 nm-thick first insulating film 20 is deposited by the CVD method, and a resist film, such as a fluid material 23, is applied so as to remain in the groove 4 by 300 nm (see FIG. 2B). Next, the first insulating film 20 is anisotropically etched to a thickness of 400 nm so that the groove side surface of the silicon substrate 1 is not exposed. After that, the remaining resist film 23 is removed (see FIG. 2c). Next, the same CVD oxide film as the first insulating film 20 is deposited as the second insulating film 21 by 750 nm. Hollow at this time
22 is formed by the first and second insulating films 20 and 21. After that, a resist film is applied as the planarizing material 6 so that the surface of the silicon substrate 1 becomes flat (see FIG. 2D). The flattening material 6 is etched by the second insulating film 22 at the same etching rate so as to be at the same height as the surface of the silicon substrate 1, that is, 950 nm, and finally the poly-Si film 3 which is the surface protection film and the thermal oxidation are formed. When the membrane 2 is removed, it has a cavity 22 in the groove 4,
The insulating film 20 and the second insulating film 21 are used to flatly fill the groove 4 (see FIG. 2e).

The present embodiment has the following effects in addition to the effects of the first embodiment. That is, after depositing the first insulating film 20, in the groove 4,
Since the fluid material 23 is formed on the first insulating film, the bottom of the groove 4 is not etched when the first insulating film is etched. Therefore, it is possible to reduce contamination and damage without directly exposing the bottom of the groove 4 to plasma or etching species.

Although the first and second insulating films are used as the filling material in the first and second embodiments of the present invention, polysilicon or the like may be used instead of the insulating film. Further, the present invention is not limited to the formation of the element isolation region, and after forming the groove, an insulating layer is formed on the surface thereof, and thereafter, a conductive polysilicon or the like is embedded to form a charge storage region (so-called trench capacitor). ) Etc. can also be used.

EFFECTS OF THE INVENTION As is clear from the above description, according to the present invention, since the thickness of the first burying film is reduced by the above-described configuration, it is easy to dig down the first burying material. Therefore, control of etching became easy. Further, although the aspect ratio of the groove is increased, a slit is not generated because a cavity is formed in the middle part of the groove, and the first and second filling materials are flatly embedded in the groove so as to have the same height as the semiconductor substrate. be able to.

[Brief description of drawings]

FIG. 1 is a sectional view showing a process of element isolation using a groove in the first embodiment of the present invention, and FIG. 2 is a sectional view showing a process of element isolation using a groove in the second embodiment of the present invention. FIGS. 3 to 5 are cross-sectional views showing a conventional process for element isolation using a groove. 1 ... p-type silicon substrate, 2 ... thermosetting film, 3 ... poly
Si, 4 ... Groove, 6 ... Flattening material, 20 ... First insulating film, 21 ... Second insulating film, 22 ... Cavity.

Claims (2)

(57) [Claims] 1. A step of forming a groove in an element isolation region of a semiconductor substrate, and a step of depositing the first filling material on the semiconductor substrate to such an extent that the first filling material does not associate with each other inside the groove. After the step of depositing the first filling material, a step of filling a fluid substance in the groove in which the first filling material is deposited, and a step of filling the fluid substance in the groove, and The step of etching the first filling material to leave the first filling material on the bottom and side surfaces of the groove, and the step of leaving the first filling material on the bottom and side surfaces of the groove, After the step of removing the fluid substance remaining inside, and the step of removing the fluid substance, the first embedding material is secondly formed in the groove left on the bottom surface and the side surface.
Depositing a filling material to form a cavity surrounded by the first filling material and the second filling material in the groove, and forming a planarizing material on the second filling material. And a step of etching the second filling material and the planarizing material, and filling the inside of the groove with the first and second filling materials. 2. The step of leaving the first burying material on the bottom surface and the side surface of the groove, the end of the etching of the first burying material is a place where the side surface of the groove is not exposed. A method of manufacturing a semiconductor device according to claim 1.