JPS58143548A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To bury an insulating film flatly by a method wherein a steep groove is formed into an element isolation region, a first insulating film is deposited onto the whole surface, the first insulating film is etched so as to leave the side wall of the groove, and the second insulating film and a surface flattened film are deposited and etched. CONSTITUTION:The groove 22, which has a steep side wall close to an approximately rectangle and narrow groove width, is formed to a silicon substrate 21. A CVDSiO2 film 23 is deposited onto the whole surface as the first insulating film. When the CVDSiO2 film 23 of the surface is etched partially, the central section of the groove 22 is etched quickly because the etching rate of a gross porosity 24 section is fast, and the CVDSiO2 film 23 is left only in the side wall of the groove 22. A gross porosity is not formed and the groove 22 can be buried by depositing a CVDSiO2 film 25 onto the whole surface again as the second insulating film. When a resist film 26 is applied onto the surface of the CVDSiO2 film 25 and etched until the surface of the silicon substrate of an element forming region is exposed, a field region is buried with the oxide film approximately flatly.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a semiconductor device in which an insulating film is embedded in a field region in order to electrically isolate each element on a semiconductor substrate. The present invention relates to a method for manufacturing device O.

[Technical background of the invention]

Semiconductor devices using silicon as a semiconductor, especially MO8
In semiconductor devices of No. 11, a thick oxide film is formed in a so-called field region between one element in order to reduce the insulation defect t&<L due to a parasitic channel and the parasitic capacitance.

Conventionally, as a device isolation method using such an oxide film, a part of the silicon substrate in the field area is processed, chindled to form a groove, and then the field oxide film is flattened using CVD technology. There is a way to get into it. With this device isolation method, after device isolation, the substrate surface is buried and flat, and the dimensions of the separation area are determined by the precisely formed groove dimensions, making it possible to produce highly integrated integrated circuits. This is a very effective device isolation technology.

Conventional method #! This will be briefly explained using Figure 1. Figure 1 (1
), prepare a Pfi (100) silicon substrate 11f with a specific resistance of 5-500-1:5I8i degrees, and
For example, 0.6μmI in the 11m area! The groove 12 is formed with a depth of Next, as shown in (b), an insulating film 1st thicker than the depth of @JJ is uniformly deposited on the surface of the substrate by, for example, the CVD method. Next, as shown in ( ), a surface flattening film 14t capable of flattening the surface is formed. Flattening @1
4, for example, a coating film of a polymer material or a plasma CV
There is silicon nitride lI based on D. after that(
As shown in d), the planarization l114 and the insulating film 13t
When etching is performed from the surface under approximately the same etching conditions to expose the surface of the substrate 11 above the element formation region, the groove 12 in the element isolation region is filled flat with the insulating film IJ. After that, desired elements are formed on the exposed substrate.

[Problems with background technology]

In the above conventional method, if the width of the trench serving as the element isolation region is less than twice the depth, the insulating film 13 may be
D5i02 film [When deposited, K
The CVD5102 film forms cavities 1j (portions where 810, is rough and #) is hollow) in the grooves.
Therefore, after this, the surface of the CVD810j film is flattened by resist spreading, or the surface of the CVD810j film is further coated with KCVD8102.
As a cavity when the membrane is deposited! ! IIJ), there were problems such as cycra and cracking caused by thermal expansion of the air inside, which significantly reduced the reliability of the device.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device with high reliability by flatly embedding an insulating film in a field region without generating the above-mentioned cavities.

[Summary of the invention]

In the present invention, after forming a steep trench in an element isolation region, a first insulating film is deposited on the entire surface and etched so as to remain on the side walls of the trench to make the trench wall substantially an inclined surface. After that, a second insulating film is deposited, followed by a surface planarizing film [deposited], and the planarizing film and the second insulating film are etched under conditions where the etching rate for both is approximately equal to the trench t-@ of the element isolation region.
The first and second insulating films are buried.

〔Effect of the invention〕

According to the present invention, it is possible to prevent the formation of cavities when depositing the second insulating film as an isolation insulating film on the trench sidewalls (virtually sloped surfaces), thereby preventing wire breakage and cracks. This can be prevented and the reliability of the device can be improved.

[Embodiments of the invention]

An embodiment of the present invention will be described with reference to FIG.

As shown in trench (1), a P-type (IOO) silicon substrate 21 with a resistivity of about 5 to 5001 is prepared, and after directly or thermally oxidizing the surface of the substrate 21, patterning is performed on the resist to form a mask and a silicon substrate 11t. - Machining and etching are performed by anisotropic drying and etching to form a narrow groove 2z having a nearly rectangular steep side wall. after that,
As shown in (b), a CVD 0□ film 23 is deposited over the entire surface as a first insulating film. At this time, East 24 occurs as shown. Next, when a part of the CVD5i02 film 23 on the surface is etched/etched with an ammonium fluoride water bath solution or vertical hydrofluoric acid, the etching speed of the cavity 24 is fast, so #$2
The center part of 2 is etched first, and groove 1 is etched as shown in (C).
1C) CVD-810 and jlJJ remain only on the side wall. As shown in (a), the CVD5 io□ film Jlt-etching can be performed using anisotropic dry etching instead of the tinde solution, and CVDSiO2 can be spread on the side wall of the groove 23. By again depositing the CVD 810□ film 25t on the entire surface as the second insulating film, it is possible to embed the insulation film 22 without generating p-holes. this is,
CVD810. has already been applied to the groove side walls at the M+J stage. The membrane 24 is
This is because the resist film 26t- Coating, resist film 26 and CVD1ii
If anisotropic dry etching and etching are performed under conditions such that the etching rate is approximately equal to that of the 102 film 25, and etching is performed until the surface of the silicon substrate in the element formation region is exposed, (
As shown in f), the field region is filled with an oxide film almost flatly. After that, the element forming area is filled with ordinary MO8.
What about the O8 type conductor device manufacturing process? -) Form a 91-oxide film, source and drain diffusion layers to make a transistor.

According to this embodiment, it is possible to fill trenches in the isolation region with a thickness less than twice the field oxide film thickness, which was impossible to fill with an oxide film due to the generation of cavities in the conventional method. Also, polycrystalline 81 wiring on the field area or metal wiring! It is possible to prevent IIT edges, prevent cracks and cracks, and improve the (i-axis properties) of the element.

The CVD8102 used in the above example has a length of 4JL with other insulating films, such as T&20□ and 81N, but in that case,
The etching solution of ammonium chloride or buffered hydrofluoric acid or the anisotropic dry etching technique used in the above embodiments is one that etches these insulations. Also, semiconductors other than silicon, such as GaAs, GaP,
Naturally, the method of the present invention can also be applied when using a semiconductor substrate such as InSb or an epitaxially grown layer. Further, the first insulating film and the second insulating film do not have to be the same film; for example, the WN2 insulating film may be used as a plasma CVDsto□ film or a low pressure CVD5i02 film.

[Brief explanation of drawings]

@1 Figures (,) to (4) are process cross-sectional views explaining the conventional method of embedding an oxide film in the field region, and Figure 2 is a cross-sectional view showing how cavities occur in the trenched insulating film. figure(&)
-(f) are process cross-sectional views illustrating an oxide film embedding method according to an embodiment of the present invention. 21... Silicon substrate, 22... Groove, 23... C
VD-8102 film (first CI insulating film), 24... East,
25...CVD810. Membrane (@2C) insulation film), J
i −・−L/ ) x ) film (1 surface flattening film). Applicant's agent Patent attorney Takehiko Suzue Figure 2 1'3 Figure 3 (d) (e) (a) Figure 3

Claims (2)

[Claims] (1) A step of selectively etching the element isolation region of the semiconductor substrate to form a trench with steep sidewalls, and then a step of uniformly depositing #11 insulating material over the entire surface of the substrate; a step of etching and stretching the insulating film so as to leave it on the side wall of the trench, a step of depositing the second insulating film over the entire surface again, and a step of depositing a flattening film tube for flattening the surface; a step of etching and etching the 1!24D insulating film and the planarizing film over the entire surface under conditions that the etching rates for both are substantially equal to filling trenches in the element isolation region with the first and second insulating films; and element formation. A method of manufacturing a semiconductor device, comprising: a step of forming an element on a surface of a substrate in a region; (2) 1st xvttg2o insulation ji[tI'1C
2. The method of manufacturing a semiconductor device according to claim 1, wherein the planarization film is made of vDSi02111 and is of a resist type.