JPS58177584A - Control system for associative buffer memory - Google Patents
Control system for associative buffer memoryInfo
- Publication number
- JPS58177584A JPS58177584A JP57059250A JP5925082A JPS58177584A JP S58177584 A JPS58177584 A JP S58177584A JP 57059250 A JP57059250 A JP 57059250A JP 5925082 A JP5925082 A JP 5925082A JP S58177584 A JPS58177584 A JP S58177584A
- Authority
- JP
- Japan
- Prior art keywords
- data
- stack
- memory
- frequency
- access
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Executing Machine-Instructions (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
【発明の詳細な説明】
(4)発aO技衝分野
本発−は情報処理速度を高速化−し九連想パシファメ毫
す制御方式に関す・
mtit留の背景
遜卑メ4□は記憶場所を記憶デーSO内容によりて識別
するメ儲す″e番〕、伺えばスタックと錨環装置O関に
パシファメ%蓼として設け、島履遮度の向上に利用する
など各種の利用方法の研究がおこなわれている。[Detailed description of the invention] (4) Departure from the field of aO technology This invention relates to a control method that increases the speed of information processing and performs nine-association pacifame. A method for identifying the memory data SO contents (e number) is installed as a pacifame % at the stack and anchor ring device O, and research is being conducted on various ways to use it, such as using it to improve the shielding degree of the island. It is.
C)従来技術と間慧点
スタックと処理装置との間に連想バクファメモリを設け
たシステムにおいては、連想バッファメモリへのデータ
の書込みに、従来、 LR[T(leastrecen
tly us@d )法が用いられていた。C) Prior art and advantages In a system in which an associative buffer memory is provided between the stack and the processing device, writing data to the associative buffer memory is conventionally performed using LR[T(least
tly us@d ) method was used.
LRU法は処理装置がスタックをアクセスして得たデー
タの蝋も新しいものを古いものに優先して書込む方式で
あるが、スタックのように順次にアクセスするメモリに
おいては、処理速度を向上するうえで連想バクフTメモ
リの効果が十分に発揮されていなかっ九〇
(2) 発明の目的
本発明は、スタックと処理装置との間に連想バッファメ
モリを設は九システムにおいて、既述従来例よりも処理
速度を向上し得る連想バッファメモリ制御方式を提供す
ることを目的とする。The LRU method is a method in which the processing unit writes the data obtained by accessing the stack, giving priority to the newest data over the oldest data, but it improves processing speed in memory that is accessed sequentially like the stack. However, the effect of the associative buffer T memory is not fully demonstrated. Another object of the present invention is to provide an associative buffer memory control method that can improve processing speed.
(ト)発明の#I#:
本発明の連想バクファメモリ制紳方式は、スタνりを順
次にアクセスし検索して得られるグーIを用いて情報の
処理をおこなう装置において、データと該データの検索
Kl!したスタックのアクセス回数とによってエントリ
を構成する連想バッフ7メモリを備え、該連想バッファ
メモリへのデータの書込を前記アクセス回数によって制
御することによって処理速度の向上を図ったものである
。(g) #I# of the invention: The associative backup memory control method of the present invention is applicable to a device that processes information using a group I obtained by sequentially accessing and searching a list of data. Search Kl! The system is provided with an associative buffer 7 memory in which an entry is configured according to the number of accesses of the stack, and the processing speed is improved by controlling writing of data to the associative buffer memory according to the number of accesses.
副 発明O実施例
次に本発明の要旨を図面に示す実施例によって具体的に
説明する。Sub-Invention O Examples Next, the gist of the present invention will be specifically explained using examples shown in the drawings.
図は本発明の一実施例を示し、lは読取データの内容に
対応する連想アドレスを発生する読取アドレス発生部、
2は連想アドレ入に対応するデータを記憶するデータメ
篭り部、3は新たにスタックをアクセスして得られたデ
ータの内容に対応する連想アドレスを発生する書込アド
レス発生部、4はデータメモリ部2に記憶するデータの
検索に要したスタックアクセス回数をそのデータに対応
して記憶するアクセス回数メモリ部、5はデータメモリ
部2に記憶されるデータのうち書込アトレータについて
アクセス回数メモリ部4に記憶されるスタック7213
回数が最少であるデータを検出しスタックアクセス回数
とともに出力する検出部、6は新たにスタックをアクセ
スして得られたデータのスタックアクセス@数と検出部
5が検出したデータのスタックアクセス回数とを比較し
、検出部5が検出したデータのスタックアクセス回数が
少ない場合にはそのデータ及びそのスタックアクセス回
数を十れぞれメモリs2及びアクセス回叡メモリs4か
ら消去し、新たにスタックをアクセスして得られたデー
タ及びそのスタックアクセス回数をそれぞれ書込むよう
に制御する制御部でわる。The figure shows an embodiment of the present invention, l is a read address generation unit that generates an associative address corresponding to the content of read data;
2 is a data storage section that stores data corresponding to input of an associative address; 3 is a write address generation section that generates an associative address corresponding to the contents of data newly obtained by accessing the stack; 4 is a data memory section Reference numeral 2 refers to an access number memory section that stores the number of stack accesses required for retrieving data to be stored in correspondence with the data; 5 refers to an access number memory section 4 for the write aterator among the data stored in the data memory section 2; Stored stack 7213
A detection unit 6 detects the data with the minimum number of times and outputs it together with the number of stack accesses, and a detection unit 6 detects the number of stack accesses of data obtained by newly accessing the stack and the number of stack accesses of the data detected by the detection unit 5. By comparison, if the number of stack accesses of the data detected by the detection unit 5 is small, the data and the number of stack accesses thereof are respectively erased from the memory s2 and the access circuit memory s4, and the stack is newly accessed. The control unit controls the writing of the obtained data and the number of accesses to the stack.
以上のようにして、データとその検索に要し九スタック
アクセス回数とによってエントリを構成する連ぎバッフ
ァメモリが得られ、常にスタックアクセス回数の多いデ
ータを紀葎−することができる0
IG)発明の詳細
な説明したように本発明によればスタックアクセス回数
の多いデータを連想バッファメモリに記憶し、スタック
アクセス回数の少ないデー#i;iスタックに記憶させ
るようKすることができるので、デーー〇アクセスに要
する時間を全体として短縮することができ、処理速度を
向上することができる。As described above, a continuous buffer memory is obtained in which an entry is formed by data and the number of stack accesses required to retrieve the data, and it is possible to always retrieve data that is accessed more often than the stack.0 IG) Invention As described in detail, according to the present invention, it is possible to store data that has been accessed many times on the stack in the associative buffer memory, and to store data on the stack that has been accessed less often on the i stack. The overall time required for access can be shortened, and processing speed can be improved.
図は本発明の一実施例を示し、2はデータメモリ部、4
はアクセス回数メモリ部、6ri制御部であゐ。The figure shows an embodiment of the present invention, in which 2 is a data memory section, 4 is a data memory section;
are the access count memory section and the 6ri control section.
Claims (1)
用いて情報のl&環をおこなう装置において、デー−と
諌デーlの検索に簑し九スタックOアクセスiI数とに
よってエントリを構成する連層バッフアメ毫すを備え、
皺連馨パF77メモリヘOデーIO書込を前記アクセス
回数によって制御することを特徴とす為連想バッファメ
モリ制御方式・In a device that performs information l&ring using data I obtained by accessing and searching a stacked stratification, a sequence that constitutes an entry by the data and the number of stacks accessed iI obtained by searching the data I is used. Equipped with a layer of buffer candy,
The associative buffer memory control method is characterized in that O-day/IO writing to the F77 memory is controlled by the number of accesses.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57059250A JPS58177584A (en) | 1982-04-09 | 1982-04-09 | Control system for associative buffer memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57059250A JPS58177584A (en) | 1982-04-09 | 1982-04-09 | Control system for associative buffer memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58177584A true JPS58177584A (en) | 1983-10-18 |
Family
ID=13107942
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57059250A Pending JPS58177584A (en) | 1982-04-09 | 1982-04-09 | Control system for associative buffer memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58177584A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5570998A (en) * | 1994-10-21 | 1996-11-05 | Unisia Jecs Corporation | Impeller structure of closed type centrifugal pump |
-
1982
- 1982-04-09 JP JP57059250A patent/JPS58177584A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5570998A (en) * | 1994-10-21 | 1996-11-05 | Unisia Jecs Corporation | Impeller structure of closed type centrifugal pump |
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