JPS6345655A - Control system for cache memory - Google Patents

Abstract

PURPOSE:To reduce the influence of an access given to a main memory and simultaneously to economically constitute a cache memory of a comparatively large capacity, by forming the cache memory with an exclusive cache memory and the area of the main memory and using them properly according to the type of data stored. CONSTITUTION:The fixed area of a main memory 30 is defined as a cache area (c) and this area (c) and an exclusive cache memory 8' form a cache memory. When this cache memory is used, a disk cache controller 12 decides to use the area (c) or the memory 8' based on the type of the data decided by a prescribed method and to receive an access. Both the area (c) and the memory 8' are controlled in the same way as a conventional cache memory. For instance, the memory 8' is used with such a type of data having high access frequency and both the memory 8' and the area (c) are used with other data respectively.

Description

[Detailed Description of the Invention] [Summary] Disk cache memory (hereinafter referred to as cache memory) that aims to speed up access by retaining and reusing blocks of data in a disk storage device, etc.
This is a control method for economically configuring the system. The cache memory consists of a dedicated cache memory and an area provided in the main storage device, and the two-headed area is used depending on the type of data to be stored. This method reduces the impact on access to the main memory by the central processing unit, etc.
A relatively large capacity cache memory can be constructed economically.

[Industrial application field]

The present invention relates to a control method for a cache memory installed in a data processing system.

Generally, from the perspective of the user, a high-speed, large-capacity storage device is ideal for a storage device used in a data processing system.

In order to approximate this economically, we created a pyramid-like hierarchy with high-speed, small-capacity storage devices at the top and low-speed, large-capacity storage devices at the bottom. ), and in this case, the upper-level high-speed, small-capacity buffer memory is called a cache memory.

[Conventional technology]

FIG. 3 is a block diagram showing an example of the configuration of a data processing system.

In Figure 3, the data processing system includes a central processing unit (hereinafter referred to as CPU) that controls and monitors the processing operations of the system.
)1 and the control buffer area (hereinafter referred to as CB) which forms the work area of cpυ1.
(a), a main storage area for data handled by the system (hereinafter referred to as MS) (b), and a disk cache that controls data read/write processing operations for the cache memory 8. The external storage device 15 includes a control device 3 and a disk control device 9 connected to the disk cache control device 3 through a channel 11 to control disk devices flOa to 10n and the processing operations of these disk devices.

As is well known, the channel 11 is a device that instructs CPU data transfer and other commands to lower-level devices (disk control device 9 and disk devices 10a to 'Ion) and controls data transfer.

-i, the data to be processed under the instructions from the CPUI is
The data is read from the disk device 10a = 1On to the main storage device 2 via the disk control device 9 and the channel 11 and processed in response to instructions from the CPUI.

However, reading frequently handled data from the disk devices 10a to Ion to the main storage device 2 every time takes a long time to process, so it is written to the cache memory 8, which can be accessed at high speed, and stored in the disk cache. By processing in the memory control device 3, the processing time of the data processing system is shortened.

The disk cache memory control device 3 includes a control section 4 that controls processing operations for reading/writing data to and from the cache memory 8, and a main storage device and the cache memory 8 for reading/writing data under the control of the control section 4. 2, a transfer mechanism 5 that performs transfer between the cache memory 8 and the disk devices 10a to Ion;
and LRU (LeastR) which stores management information of data stored in cache memory 8 as a table.
recently used) table 6 and a directory riff.

The cache memory 8 and its control function may be located in the disk controller 9, but as shown in FIG.
By placing the cache memory 8 under PU10, the cache memory 8 can be shared by many external storage devices.

The cache memory 8 is connected to the disk device 10 as described above.
Since the purpose is to speed up the apparent access time to the disk devices 10a to Ion, it is necessary that the access time to the disk devices 10a to LOn is sufficiently faster. Consists of random access memory (RAM).

The cache memory 8 has a storage area of, for example, 4 to 1.
It is divided into blocks of about 6 kilobytes.

The control unit 4 of the disk cache control device 3 is a CPU
When a command is received from the command, the address of the data on the disk drives W10a to Ion specified by the command is used.
The directory riff is searched to identify whether a block containing the data exists in the cache memory 8.

The directoriff is a table consisting of terms corresponding to each block obtained by dividing the cache memory 8, for example, and when a copy of a block of data of the disk devices 10a to 10n is stored in the block, the validity of the corresponding term is For example, by turning on the display bit, it is displayed that there is valid data, and the following column shows the disk device 1 of the block.
It is assumed that addresses on 0a to Ion are stored.

When it is determined that the specified data is in the cache memory 8 by searching the directory riff, the control unit 4 uses the address of the data in the cache memory 8 determined from the contents of the searched directory riff and the command from the CPU 1. The specified address of the area on MS(b) of the main storage device 2 is passed to the transfer mechanism 5, and the specified data is transferred from the cache memory 8 to the main storage device 2.

When it is determined that the specified data is not present in the cache memory 8 through the directory search, the control unit 4 stores the block containing the specified data in the disk devices 10a to 10I.
A command is issued to the channel 11 via the transfer mechanism 5 in order to transfer from the on to the cache memory 8.

In addition, the transfer mechanism 5 selects an empty block on the cache memory 8 along with the address of the specified area on the main storage device 2 as described above, and 1. Notify the address.

As is well known, the channel 11 is connected to the disk devices 10a to 10a through the disk controller 59 and the disk controller 9.
The command is relayed to one of the disk devices 10a to 10n.
When data is transferred from the transfer mechanism 5, it is passed to the transfer mechanism 5.

The transfer mechanism 5 stores this data in a designated free block of the cache memory 8, and also transfers the designated data therein to a designated area of the main storage device 2.

The control unit 4 searches for free blocks on the cache memory 8 by scanning the OFF term of the valid bit on the directory riff, and if there is an OFF term, processes the corresponding block as free. do.

If the directory riff is scanned and it is determined that there is no free space, the oldest accessed block is selected using the LRU table 6, the data in that block in the cache memory 8 is stopped, and this block is used for the current processing. This is an empty block used to store data inside.

The LRU table 6 is composed of entries corresponding to each block of the cache memory 8, and forms a chain in which entries of blocks that have been accessed are connected in the order of access occurrence by pointers held in the entries.

Each time the control unit 4 processes access to a certain block, it reconnects the term of that block to the end of the chain,
When selecting a block, select the block at the beginning of the chain.

For the above control, each item holds a pointer in the backward direction in addition to the pointer in the forward direction of the chain, and the table is also attached with pointers pointing to the beginning and end items of the chain.

When a free block is allocated to a new data block in the above manner, the control unit 4 writes the address of that block on the disk devices 10a to Ion to the relevant section of the directory lift and turns on the valid bit. .

[Problem that the invention seeks to solve]

In order to fully obtain the effect of shortening access time by the disk cache as described above, the cache memory 8 needs to have a somewhat large capacity.

However, if an independent relatively large-capacity memory is provided as the cache memory 8, the system becomes expensive and problems arise in terms of implementation.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the invention in detail.

A dedicated cache memory 8' that defines the cache memory 8 explained in FIG. 3 as a dedicated cache memory,
By providing a cache area (c) in the main storage device 30 and a table for managing each of the cache area (c) in the main storage device 30 and the dedicated cache memory 8' in the disk cache control device 12, , is a configuration means for solving the above-mentioned problems.

[Effect]

A certain area of the main storage device 30 is allocated as a cache area (c), and this cache area [0] and the dedicated cache memory 8'' are used as cache memories.

When using the cache memory, the disk cache control device 12 determines whether to use the cache area (c1 or
It is determined and processed whether to use the dedicated cache memory 8°, and each is controlled in the same way as the conventional cache memory 8.

In this method, for example, the dedicated cache memory 8' is used for frequently accessed data types, and the dedicated cache memory 8' and cache area (c1
By controlling the use of
By using the area of the main storage device, it is possible to realize a large capacity cache memory at relatively low cost.

〔Example〕

FIG. 2 is a block diagram illustrating the invention in detail. Note that the same reference numerals indicate the same objects throughout the figures.

In this embodiment, as shown in FIG.
and a dedicated cache memory 8'.

The cache area (c) is on the main storage device 30, for example, C.
Similar to the CB(a>?+1 area), the M S (
It is assumed that it is provided in an address area with a lower number than b).

The control section 24 in the disk cache control device 12 starts processing in response to a command from the CPUI in the same manner as the control section 4, and searches the directory 27 to find out which cache memory contains the corresponding block of data.

The directory 27 is a table having the same structure as the directory ref, except that it has entries corresponding to each block of the dedicated cache memory 8' and the cache area fc).

When the specified data is identified as being in either cache memory by searching the directory 27, the control unit 24 controls the transfer mechanism 25 in the same manner as the control unit 4, and stores the specified data in the dedicated cache memory 8° or Cache area (
c) The designated data is transferred to the designated area of the main storage device 30.

When transferring data from the cache area (e), the data is read from the cache area (c) to the transfer mechanism 25 in each predetermined access unit in the same way as normal transfer on the main storage device 30. , and the process of writing it to a designated area of the main storage device 30 is repeatedly executed.

When it is determined by searching the directory 27 that the designated data is not in the cache memory, the control unit 24 identifies whether or not the data is data that is used only by the dedicated cache memory 8'' based on, for example, the designated data address. The control table for this purpose is, for example, a list of addresses of blocks of data that should use the dedicated cache memory 8'', is created in advance as initial setting data, and is loaded into the memory in the control unit 24 at the time of initial setting of the system. shall be taken as a thing.

This list should list the addresses of frequently used data blocks.

As a result of the above, the block containing the specified data is stored in the dedicated cache memory 8' if the data uses the dedicated cache memory 8', or in any cache memory determined as described below in the case of other data. In order to transfer from the disk devices 10a to Ion, the transfer mechanism 25
A command is issued to the channel 11 via the .

Also, as in the past, the transfer mechanism 25 is notified of the address of the specified area on the main storage device 30 as described above, as well as the selected empty block on the cache memory.

Similarly to the above, the channel 11 is connected to the disk devices 10a to 1.
0n data transfer is started and the transfer data is transferred to the transfer mechanism 25.
pass it on to

The transfer mechanism 25 stores this data in a designated empty block of the designated dedicated cache memory 8'' or cache area (c1), and also transfers the designated data therein to a designated area of the main storage device 30.

The control unit 24 scans the corresponding portion on the directory 27 to search for a free block on the dedicated cache memory 8'' or the cache area (c1).

When the directory 27 is scanned and it is determined that there is no free space, the LRU table 20a is used for data that uses the dedicated cache memory 8, and the LRU table 20b is used for other types of data. Determine the accessed block and use that block as a free block.

The LRU table 20a holds the usage status of the dedicated cache memory 8', and the LRU table 20b holds the usage status of the dedicated cache memory 8' and the cache area (c) together, using a chain having the same configuration as described for the LRU table 6. Configure it as follows.

〔Effect of the invention〕

According to the present invention as described above, there is an effect that a large capacity cache memory can be realized at low cost without extremely interfering with access from the CPU to the main storage device.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, and FIG. 3 is a block diagram explaining a conventional example. In the figure, 1 is the CPU, 2 and 30 are the main storage devices, and 3
．． 12 is a disk cache control device, 4.24 is a control unit, 5.25 is a transfer mechanism, 6, 20a,
20b is the LRU table, 7.27 is the directory,
8 is a cache memory, 8'' is a dedicated cache memory, 9 is a disk controller, 11 is a channel, 10a to I
on is a disk device, FIG. 1 is a detailed block diagram of the present invention. FIG. 2 is a block diagram of the present invention. FIG. 3 is a block diagram of a conventional example.

Claims (1)

[Claims] A central processing unit (1), a main storage device (30), and, upon receiving a command from the central processing unit (1), data in an external storage device (15) specified by the command. In a data processing system comprising a disk cache control device (12) that stores a copy of a block contained in a cache memory and transfers data of the stored block to a specified area of the main storage device, the cache memory is controlled by a disk cache control device. Device(
12) and a predetermined area (cache area (c)) of the main storage device (30).
the block in either the dedicated cache memory (8') or a predetermined area (cache area (c)) of the main storage device, determined according to a predetermined type of data specified in the command; A cache memory control method characterized by being configured to store.