JPS58172268U

JPS58172268U - clamp device

Info

Publication number: JPS58172268U
Application number: JP6986582U
Authority: JP
Inventors: 黒柳　邦弘
Original assignee: ソニー株式会社
Priority date: 1982-05-13
Filing date: 1982-05-13
Publication date: 1983-11-17

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図はクランプ装置の従来例を示すブロック図である
。第２図は上記従来例の動作を示すタイムチャートであ
る。第３図は本考案に係るクランプ装置の一実施例を示
すブロック図である。第４図は上記実施例の動作を示す
タイムチャートである。１１・・・・・・信号入力端子、１２・・・・・・クラ
ンプパルス形成回路、１４・・・・・・サンプリング回
路、１５・・・・・・ノイズ除去回路、１６・・・・・
・逆加算回路、１８・・・・・・クランプ回路、２０・
・・・・・信号出力端子。補正昭５７．８．３１ −　　　実用新案登録請求の範囲を次のように補正する
。０実用新案登録請求の範囲ンプリング回路からのサンプリング出力についてノイズ
除去を行なうノイズ除去回路と、このノイ、　ズ除去回
路からの出力信号、と上記入力信号とを逆極性で加算す
る逆加算回路と、この逆加算回路からの加算出力信号に
ついてクランプ処理を行なうクランプ回路とから成るク
ランプ装置。FIG. 1 is a block diagram showing a conventional example of a clamp device. FIG. 2 is a time chart showing the operation of the conventional example. FIG. 3 is a block diagram showing an embodiment of the clamping device according to the present invention. FIG. 4 is a time chart showing the operation of the above embodiment. 11... Signal input terminal, 12... Clamp pulse forming circuit, 14... Sampling circuit, 15... Noise removal circuit, 16...
・Inverse adder circuit, 18...Clamp circuit, 20・
...Signal output terminal. Amendment August 31, 1980 - The scope of claims for utility model registration is amended as follows. 0 Utility Model Registration Claims A noise removal circuit that removes noise from the sampling output from the sampling circuit; an inverse addition circuit that adds the output signal from the noise removal circuit and the input signal with opposite polarity; A clamp device comprising a clamp circuit that performs clamp processing on the addition output signal from the inverse addition circuit.

Claims

[Scope of utility model registration request]

A sampling circuit that samples the clamped portion of the input signal, a noise removal circuit that removes noise from the sampling output from this sampling circuit, and an inverse circuit that adds the output borrowed from this noise removal circuit and the above input signal with opposite polarity. A clamp device consisting of an adder circuit and a clamp circuit that performs clamp processing on the addition output signal from the inverse adder circuit.