JPS58101574U - Video signal processing circuit - Google Patents
Video signal processing circuitInfo
- Publication number
- JPS58101574U JPS58101574U JP19340081U JP19340081U JPS58101574U JP S58101574 U JPS58101574 U JP S58101574U JP 19340081 U JP19340081 U JP 19340081U JP 19340081 U JP19340081 U JP 19340081U JP S58101574 U JPS58101574 U JP S58101574U
- Authority
- JP
- Japan
- Prior art keywords
- video signal
- circuit
- signal processing
- processing circuit
- clamp circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Television Signal Processing For Recording (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来回路の一例を示す系統図、第２図はこの考
案の＝実施例わ示す系統図、第３図はこの考案の他の実
施例を示す系統図である。
３は振幅変調器、５．１４はクランプ回路、６は信号切
換用スイッチ回路、７は遅延回路、８は復調器、９は擬
似垂直同期信号挿入用スイッチ回路である。FIG. 1 is a system diagram showing an example of a conventional circuit, FIG. 2 is a system diagram showing an embodiment of this invention, and FIG. 3 is a system diagram showing another embodiment of this invention. 3 is an amplitude modulator, 5.14 is a clamp circuit, 6 is a signal switching switch circuit, 7 is a delay circuit, 8 is a demodulator, and 9 is a pseudo vertical synchronization signal insertion switch circuit.
Claims (1)
プ回路と、この第１のクランプ回路の出力を所定量遅延
させる遅延回路と、この遅延回路の出力を上記基準電位
に保持する第２のクランプ回路と、このクランプ回路の
出力と上記第１のクランプ回路の出力とを選択す−るス
イッチ回路とを具備して成る映像信号の処理回路。a first clamp circuit that holds the input video signal at a predetermined reference potential; a delay circuit that delays the output of the first clamp circuit by a predetermined amount; and a second clamp circuit that holds the output of the delay circuit at the reference potential. A video signal processing circuit comprising a clamp circuit and a switch circuit for selecting between the output of the clamp circuit and the output of the first clamp circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19340081U JPS58101574U (en) | 1981-12-28 | 1981-12-28 | Video signal processing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19340081U JPS58101574U (en) | 1981-12-28 | 1981-12-28 | Video signal processing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58101574U true JPS58101574U (en) | 1983-07-11 |
Family
ID=30106755
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19340081U Pending JPS58101574U (en) | 1981-12-28 | 1981-12-28 | Video signal processing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58101574U (en) |
-
1981
- 1981-12-28 JP JP19340081U patent/JPS58101574U/en active Pending
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