JPS60127030U - digital filter system - Google Patents
digital filter systemInfo
- Publication number
- JPS60127030U JPS60127030U JP1363984U JP1363984U JPS60127030U JP S60127030 U JPS60127030 U JP S60127030U JP 1363984 U JP1363984 U JP 1363984U JP 1363984 U JP1363984 U JP 1363984U JP S60127030 U JPS60127030 U JP S60127030U
- Authority
- JP
- Japan
- Prior art keywords
- frequency control
- digital filter
- low
- filter
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Feedback Control In General (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来例のフロック図、第2図は本考案の一実施
例のフロック図、第3図は要部の動作説明図である。FIG. 1 is a block diagram of a conventional example, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of the main parts.
Claims (1)
域制御テジタルフィルタ、およびそれ以外の周波数を制
御する高域制御デジタルフィルタを具備するものにおい
て、低域制御回路および高域制御回路を並列に設け、高
域制御回路はその高域’+U御テジタルフィルタの前段
にデジタルバイパスフィルタを設け、低域制御回路はそ
の低域制御テシタルフィルタの前段にデジタルローパス
フィルタを設けると共に、上記低域制御デジタルフィル
タの前後に間引き処理回路および補間処理回路を具備し
、両制御回路は加算回路で加算されて出力するようにし
たことを特徴とするデジタルフィルタシステム。In devices equipped with a low-frequency control digital filter that controls frequencies sufficiently lower than the sample frequency and a high-frequency control digital filter that controls other frequencies, the low-frequency control circuit and high-frequency control circuit are installed in parallel. , the high-frequency control circuit is provided with a digital bypass filter before the high-frequency '+U control digital filter, and the low-frequency control circuit is provided with a digital low-pass filter before the low-frequency control digital filter. 1. A digital filter system comprising a decimation processing circuit and an interpolation processing circuit before and after a filter, and the two control circuits are added together by an adder circuit and output.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984013639U JPH083065Y2 (en) | 1984-02-03 | 1984-02-03 | Digital filter system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984013639U JPH083065Y2 (en) | 1984-02-03 | 1984-02-03 | Digital filter system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60127030U true JPS60127030U (en) | 1985-08-27 |
JPH083065Y2 JPH083065Y2 (en) | 1996-01-29 |
Family
ID=30497831
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1984013639U Expired - Lifetime JPH083065Y2 (en) | 1984-02-03 | 1984-02-03 | Digital filter system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH083065Y2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58111511A (en) * | 1981-12-25 | 1983-07-02 | Sony Corp | Correcting circuit for analog information signal |
-
1984
- 1984-02-03 JP JP1984013639U patent/JPH083065Y2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58111511A (en) * | 1981-12-25 | 1983-07-02 | Sony Corp | Correcting circuit for analog information signal |
Also Published As
Publication number | Publication date |
---|---|
JPH083065Y2 (en) | 1996-01-29 |
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