JPS58111511A - Correcting circuit for analog information signal - Google Patents

Abstract

PURPOSE:To attain the flexible and easy design, and ease of maintenance and inspection, by tone-controlling audio signal with a bit slice type microprocessor for digital processing of the audio signals. CONSTITUTION:The audio signal S1 is supplied to an A/D converter 2 from an input terminal 1, and converted into a digital signal S2 and applied to the bit slice microprocessor 3 and response control signals S8, S9 at low and high frequencies are applied to the processor 3 from control circuits 8 and 9. The processor 3 tone-controls the signal S2 in response to the signals S8, S9 to pick up a signal S'3, which is applied to a D/A converter 5 and a tone-controlled analog signal S5 is outputted from an output terminal 6.

Description

DETAILED DESCRIPTION OF THE INVENTION Tone control circuits are generally constructed from a combination of capacitors and resistors. Therefore, in such a tone control circuit, for example, striped 5rIIAA
When an audio signal having a high frequency component 8T and a low frequency component 8B is supplied as shown in Fig. At the same time as the level of area component 8B increases,
A phase shift of -1, that is, a phase distortion occurs.

The present invention provides a circuit for a tone controller that takes into account the phase V of each signal component, and particularly aims to simplify its configuration.

An example of this will be explained below. In addition, in the following example, as shown in Figure 6, the low range is QHz [±
Adjustable over a range of 10dB, high range 25kHz
This is the case where z is set to 5 so that it can be adjusted over a range of ±10 dB.

In FIG. 1, an analog audio signal Sl is supplied to an A/1) converter (2) through an input terminal (1), sampled at a frequency of, for example, 50 kHz, and converted into, for example, a 16-bit digital signal 82. This signal 82 is transmitted to the bit slice type microprocessor 4.
31 K is supplied and the control circuit +81, t9
A control signal S8 for controlling the low frequency response of the audio signal S1 and a control signal S9 for controlling the high frequency response of the audio signal S1 are supplied from the audio signal S1 to the processor (3). Then, in the microprocessor (3), a signal 5 is generated for the signal S2.
Tone control processing corresponding to 8sSilK is performed to generate signal S3, and this signal 4#8s is output to D/A.
Converter (51) and tone-controlled audio Note 8. K-converted.

This signal BS is output from terminal (6) K31.

In this case, the processor 33 is configured as a primary processor 33 to perform tone control processing.

That is, this processor (3) includes a four-pass filter (400) and a delay circuit (SO
O), a bypass filter (600), and a circuit (700) for converting their outputs to II&ll.
It is said that Then, in Puto Senna (3) k, C
D is mu LU, C1a) 116 x 16 hy)
Nol [aK, (to) ha ROM is shown, and this ROM @ contains data 81 to B2S such as shown in #l31IIK.
em1*"l"TN is written. In addition, the address module of the ROM@ in which these data B1-Be1tm1e T1 to T3 are written is B1 for simplicity.
” Addresses B2m*mu1#T1-T3.

Further, - indicates ILAM&, and this RAM (incorporated) works as a delay circuit, and one of its addresses corresponds to one delay circuit. In other words, if data at a certain address in RAM- is transferred to another address for a predetermined period τlik, the data will be contiguous for a period τ. Note that this delay period τ is the reciprocal of the sampling frequency in the MU/D converter (2), that is, 20 μsec. Also, the address of RAM C (51 is bl-″-
b12. Hatake 1~an @ '1-''-14, and the data at this address is also bl 5-bl2 # al ~ II
Let Q + tl to t4.

These circuits 01J-- are connected to the data bus (to) K
Further, when the buffer registers (to) and (b) are connected to the data bus coxs, the digital signal 82 from the A/D converter (2) is supplied to the register, and the digital signal S3 is taken out from the register. D/
A converter (5) K is supplied. In addition, an input port (to) and an input port are connected to the data bus, and the input port (aa) and cm#/cw control circuit (81, +91 f) are connected to the data bus.
Control signals &...8 are supplied.

Furthermore, 441) is a microphone party program controller (
(Sequencer) The % ring indicates a microphone program memory, - indicates a pipeline register, and the memory is composed of a ROM K, in which, for example, a 7m chart program indicated by the second jlK is written. Then, this program is loaded into the register by the contents 4 and each instruction is executed.

At this time, the next address control signal NAC is supplied from the register to the controller, and the program is pipelined. moreover.

A status signal 8T8 is also supplied to Suntroz@υ. Note that G14 indicates a Kutsk generator, and in this generator, a μtuk pulse is formed at a frequency of, for example, 4 MHz, that is, 80 times the sampling rate of 59 kHz in the A/D 5 amplifier (2) K, and this is applied to each part. Supplied.

In addition, the flowchart shown in llI21 is for realizing the equivalent struggle shown in Figure 4 using the processor (1) K & r, and the program written in the memory is set by the register UK by the control cost. As a result, gisIsυ~4 is controlled and executed.

That is, in the second gl, the step (103) is the step of initializing the step (102"l is processor + 13): 1 Inverter (2), (5J and processor (3) are asynchronously coupled. Therefore, the purpose of solving this is to check whether the signal s2 of the register (to) K1 sample is set or not.
,.

If it is set, this certainty g is continued until the signal S2 is read out from the register (to) and the next step (104) K is performed, or if it is not set, it is set. Therefore, the processing after step (104) is as follows:
This will be performed K1 times for each sample of No. 41 S2.

Further, step (104) is a step for realizing the low-pass filter (400) in FIG. 4. For example, when i = x l, K is U1 = 82 V1 = U1*Bt-b1*B2-b2*Bs =・
(1) C2”Vt + bt * B4 +b2
・・・・・・・・・・・・(it) b2 = bl
・・・・・・・・・・・・(II)
J xw Vl・・・・・・・・・
......(1v), but addition and subtraction in (1) and (II) are performed in ALU (lυ), and 1 multiplication is performed using multiplication at path -. is R.A.
The data bI at the btll location of M0# is transferred to the vb1 address, and the equation (1v) shows the data JV1va-c is transferred to the J address of RAMo4.

Then, five such sensitive layers are performed for i w 1 to 6, and finally, No. 1 Lo is deposited.

86, step (105) is the delay m1 in FIG.
This is a step to realize ll (50G).

Data aiv of address 11 in RAM (goods) next address x a, 1+,
m-1>IC, and the signal Mo' is obtained. Then, in step 5 above, this step (105
) (Steps of Abirin (104) to (108)')
is performed only once for each sample of the signal 82, so in this step (105) the signal 82 is maintained for a period of 50j seconds, which is the reciprocal of the number of sampling cycles, and is taken out as a signal. become.

Further, step (106) is a final step for realizing the no-pass filter (600) in FIG. 4, and this process is performed for i=1 to 3, and the digital signal Ho is taken out.

Then, step (107) is the synthesis circuit (7) of FIG.
00) to form a digital signal S3 from the signals LO*NO*HO formed in steps [104] to (106), and step (10g
), the signal 83 is supplied to the D/A converter (5) via the register (b). The process then jumps to step [103] and waits for human input to sample the next signal S2.

Therefore, this processor (3) is equivalent &CI! It is shown in Figure 4.

That is, the I-pass filter (400) is a second-order II
It consists of 6 stages of R-type filters connected in cascade.

Its frequency characteristics are low-pass characteristics as shown by the solid line in FIG. 7 (the loss in the upper band is 60 dB or more).

Further, the group delay time characteristic becomes flat in the pass band 5, as indicated by the dotted line in FIG. Therefore, the output signal Lo
is the digital signal of the low frequency component of signal 4#S1.

Since this signal LQKg Goshin 4#88 is multiplied, the level when the multiplied signal L=L1)*8B is converted to analog is the signal 8. It changes as shown in No. 81111 correspondingly.

sb, the bypass filter (6OO) is configured in a fourth-order FIR type with symmetrical coefficients, and its frequency characteristic is
It has a high-pass characteristic shown by IK (loss of li stop band is 89
dB or more). Therefore, its output signal I40 is.

This is a digital signal of the high frequency component of the compensation circuit 81.

Then, since this signal) 16KIl1M is multiplied by the signal S-, the level of the multiplied signal H=HOI8 when it is converted to analog changes to 5 as shown in Figure 9, corresponding to signal 89. .

The jP% delay circuit (500) has signals L, MQ,
This is to prevent a difference in delay time (phase) from occurring in the analog signal when H is converted to analog, and the level at the 81st and 1011th is 4.
The level at which No. m was converted to analog is used as the standard.

Then, these signals L, MO, and H are added to form a signal S3, which is converted to an analog signal s5, so that this signal S5 has a frequency characteristic as shown in Fig. 6. That is, when the signal from the control signal 88K is converted to analog, the level changes rapidly as shown in 8a2, and this signal is added to the signal with a flat characteristic, so that the signal 8.
The low-frequency components contained in K change as shown in Figure 6.

Furthermore, when the signal H is converted into an analog signal by the control signal 89, the level changes as shown in FIG. The high frequency component percentage changes as shown in Figure 6. Therefore, the signal S! I has a frequency characteristic that changes from the control signal 8g and S@K as shown in the 6th #AK.

In this way, according to the present invention, it is possible to perform tone control of the audio signal, but in this case, according to the present invention, the signal MoK with a flat characteristic and the signal H of the high frequency component can be added to 1%. At this time, the group delay time characteristic of the filter (400) that outputs the low-frequency component signal Lt-ME is flat in the passband as shown by the broken line in the seventh panel. , the high-frequency component signal Hvtlj output filter (600) is configured in an FIR type with symmetrical coefficients, so that the delay time characteristic is constant in its pass band. Therefore, since there is no phase shift in the analog H signal, the phase difference between the low-frequency component, mid-frequency component, and high-frequency component contained in the output signal of the terminal (6) also increases. Misalignment, ie.

No phase distortion occurs.

Also, according to this example, the audio signal Slv
When tone control is performed by the digital processing 11, it is performed using a bit-slice-type one setter (3)k, so it is superior in terms of processing, design, maintenance, etc. In other words, it is superior in terms of processing, design, maintenance, etc. If so, it can be realized by configuring the wired IC like the equivalent circuit in the 4th diagram, but in that case, the I'C
Even if it were to be implemented, the number of ICs would be extremely large, the size would be large, and it would be extremely expensive.5 In addition, if different tone control characteristics are required depending on the market or user requirements, development during the design process will be required. Flexibility and ease #1 is rarely available. In addition, maintenance of iI position.

Problems also arise with respect to inspection and repair.

However, according to this Wiik, the microprocessor (
3) Since the digital tone control circuit is configured as a tube, the configuration is simple, as shown in Figure 1.
Costs can be reduced and a small WIIC can be achieved.

In addition, if different tone controls are required depending on the market or user requirements, all you need to do is change the data in the ROM and the program in the memory, increasing the flexibility and ease of design and development. . Furthermore, equipment maintenance, inspection, and repair will also be handled by J6IC.

In the above description, the tone control of the audio signal is performed, but the delay time (phase) can also be controlled. Furthermore, in the case of a high-frequency signal such as a video signal, the digital signal may be divided into multiple channels, and each channel may be processed by a processor before being synthesized.

[Brief explanation of drawings]

Illustrated is a systematic diagram of this example, and Figures 2 to 10 are diagrams for explaining it. Ll) )! The A/D converter % (3) is a bit slice type 1x4 processor, and (5) is a D/M converter. A5 G i'-14 Arrow Figure 8 Figure 10 [Interval JIl foot number [
AHx) - M Danjiki' Tribute 1 Summer j -

Claims (1)

[Claims] A digital signal that has been subjected to M/D conversion from an analog information signal is supplied to a bit-slice-type microprocessor, and the microprocessor processes the digital signal into a predetermined program by performing calculations, delay, etc.
-L, an analog information signal correction circuit which is used to correct the analog signal when this process is D/A converted;