JPS58171549U - Latch circuit for microcomputer - Google Patents
Latch circuit for microcomputerInfo
- Publication number
- JPS58171549U JPS58171549U JP6853082U JP6853082U JPS58171549U JP S58171549 U JPS58171549 U JP S58171549U JP 6853082 U JP6853082 U JP 6853082U JP 6853082 U JP6853082 U JP 6853082U JP S58171549 U JPS58171549 U JP S58171549U
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- mode
- level
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Input From Keyboards Or The Like (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は先行技術の電気回路図、第２図は第１図に示さ
れた先行技術の動作を説明するための波形図、第３図は
本考案の二実施例の電気回路図、第４図は第３図に示さ
れた実施例の動作を説明するための波形図である。
１・・・比較回路、２・・・一方入力端子、３・・・他
方入力端子、４・・・出力端子、１・・・マイクロコン
ピユー ゛り、ＳＷ・・・スイッチング素子、Ｒ１−
Ｒ６・・・抵抗、Ｉｌｏ・・・入出力ポート。FIG. 1 is an electrical circuit diagram of the prior art, FIG. 2 is a waveform diagram for explaining the operation of the prior art shown in FIG. 1, and FIG. 3 is an electrical circuit diagram of two embodiments of the present invention. FIG. 4 is a waveform diagram for explaining the operation of the embodiment shown in FIG. 3. 1... Comparison circuit, 2... One input terminal, 3... Other input terminal, 4... Output terminal, 1... Microcomputer, SW... Switching element, R1-
R6...resistance, Ilo...input/output port.
Claims (1)
って入出力ポートに予め定めたレベルを有する信号を導
出して、入出力ポートを出力モードとし、またはその入
出力ポートを信号受信のために高入力インピーダンスと
して入力モードとすることができるマイクロコンピュー
タと、２つの入力端子と、前記入出力端子に接続された
出力端子と゛を有する比較回路と、 子イツチング動作し、比較回路の一方の入力端子に接続
されてその入力端子のレベルを変えるスイッチング素子
と、 比較回路の他方の入力端子と出力端子とに接続され、入
出力ポートにおける出力モードまたは入力モードの変化
によって前記他方入力端子のレベルを変える基準電圧発
生回路とを含み、この基準電圧発生回路は、入出力ポー
トが入力モードであるときスイッチング素子のスイッチ
ング態様の変化に応じて比較回路の出力端子のレベルが
変化し、入出力ポートが出力モードでありかつスイッチ
ング素子が予め定める一方のスイッチング態様であると
き比較回路の出力端子が予め定めたレベルになるように
他方入力端子のレベルを一強制することを特徴とするマ
イクロコンピュータ用うツを回路。
□[Claims for Utility Model Registration] A system having an input/output port, which derives a signal having a predetermined level to the input/output port according to a prestored program to set the input/output port to an output mode, or a microcomputer that can be in input mode as a high input impedance for signal reception; a comparator circuit having two input terminals and an output terminal connected to the input/output terminal; a switching element connected to one input terminal of the circuit to change the level of that input terminal; and a switching element connected to the other input terminal and output terminal of the comparator circuit to change the level of the other input terminal by changing the output mode or input mode at the input/output port. a reference voltage generation circuit that changes the level of the input terminal, and this reference voltage generation circuit changes the level of the output terminal of the comparison circuit in accordance with a change in the switching mode of the switching element when the input/output port is in the input mode. , characterized in that when the input/output port is in the output mode and the switching element is in one predetermined switching mode, the level of the other input terminal is forced to one level so that the output terminal of the comparison circuit becomes a predetermined level. Circuits for microcomputers.
□
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6853082U JPS58171549U (en) | 1982-05-10 | 1982-05-10 | Latch circuit for microcomputer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6853082U JPS58171549U (en) | 1982-05-10 | 1982-05-10 | Latch circuit for microcomputer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58171549U true JPS58171549U (en) | 1983-11-16 |
Family
ID=30078305
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6853082U Pending JPS58171549U (en) | 1982-05-10 | 1982-05-10 | Latch circuit for microcomputer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58171549U (en) |
-
1982
- 1982-05-10 JP JP6853082U patent/JPS58171549U/en active Pending
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