JPS601046U - gate circuit - Google Patents
gate circuitInfo
- Publication number
- JPS601046U JPS601046U JP9321383U JP9321383U JPS601046U JP S601046 U JPS601046 U JP S601046U JP 9321383 U JP9321383 U JP 9321383U JP 9321383 U JP9321383 U JP 9321383U JP S601046 U JPS601046 U JP S601046U
- Authority
- JP
- Japan
- Prior art keywords
- gate circuit
- comparator
- input terminal
- inverting input
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Logic Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図、第２図は従来のアンドゲート回路を示す電気回
路図、第３図は本考案の実施例を示す電気回路図、第４
図、第５図は本考案の他の実施例を示す電気回路図であ
る。
７．８・・・・・・第１、第２抵抗、９・・・・・・比
較器、１０・・・・・・第３抵抗、１１．１２・・・・
・・入力抵抗。Figures 1 and 2 are electric circuit diagrams showing a conventional AND gate circuit, Figure 3 is an electric circuit diagram showing an embodiment of the present invention, and Figure 4 is an electric circuit diagram showing a conventional AND gate circuit.
FIG. 5 is an electrical circuit diagram showing another embodiment of the present invention. 7.8...First and second resistors, 9...Comparator, 10...Third resistor, 11.12...
...Input resistance.
Claims (1)
転入力端子から入力する比較器と、この比較器の非反転
入力端子と接地間に接続される第３抵抗と、この比較器
の非反転入力端子に接続される少なくとも２つ以上の入
力抵抗とを備え、この入力抵抗を介してＨもしくはＬの
論理レベル電圧を入力した後、比較器よりＨもしくはＬ
の論理レベルを出力させたことを特徴とするゲート回路
。A first and second resistor that generates a reference voltage, a comparator that inputs this reference voltage from an inverting input terminal, a third resistor that is connected between the non-inverting input terminal of this comparator and ground, and It is equipped with at least two input resistors connected to a non-inverting input terminal, and after inputting an H or L logic level voltage through the input resistors, a comparator outputs a high or low voltage.
A gate circuit characterized in that it outputs a logic level of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9321383U JPS601046U (en) | 1983-06-16 | 1983-06-16 | gate circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9321383U JPS601046U (en) | 1983-06-16 | 1983-06-16 | gate circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS601046U true JPS601046U (en) | 1985-01-07 |
Family
ID=30223905
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9321383U Pending JPS601046U (en) | 1983-06-16 | 1983-06-16 | gate circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS601046U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49118357A (en) * | 1973-03-14 | 1974-11-12 | ||
| JPS5016836B2 (en) * | 1971-11-08 | 1975-06-16 |
-
1983
- 1983-06-16 JP JP9321383U patent/JPS601046U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5016836B2 (en) * | 1971-11-08 | 1975-06-16 | ||
| JPS49118357A (en) * | 1973-03-14 | 1974-11-12 |
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