JPS59119620U - ideal diode circuit - Google Patents
ideal diode circuitInfo
- Publication number
- JPS59119620U JPS59119620U JP1213283U JP1213283U JPS59119620U JP S59119620 U JPS59119620 U JP S59119620U JP 1213283 U JP1213283 U JP 1213283U JP 1213283 U JP1213283 U JP 1213283U JP S59119620 U JPS59119620 U JP S59119620U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- diode
- operational amplifier
- input terminal
- amplifier circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の説明に供する線図、第２図は従来の理
想ダイオード回路の例を示す結線図、第３図は本考案理
想ダイオード回路の一実施例を示す結線図、第４図、第
５図及び第６図は第３図の等価回路を示す結線図である
。
１は入力端子、１０は出力端子、１１は演算増幅回路、
１２．１５及び１６は夫々抵抗器、１３ ′及び１４は
夫々ダイオードである。Fig. 1 is a diagram for explaining the present invention, Fig. 2 is a wiring diagram showing an example of a conventional ideal diode circuit, Fig. 3 is a wiring diagram showing an embodiment of the ideal diode circuit of the invention, and Fig. 4. , FIG. 5, and FIG. 6 are wiring diagrams showing the equivalent circuit of FIG. 3. 1 is an input terminal, 10 is an output terminal, 11 is an operational amplifier circuit,
12, 15 and 16 are resistors, respectively, and 13' and 14 are diodes, respectively.
Claims (1)
演算増幅回路の反転入力端子を第１の抵□ 抗器を介
して接地し、前記演算増幅回路の出力端子を第１のダイ
オードのカソード及び第２のダイオードのアノードに夫
々接続し、該第１のダイオードのアノードを前記演算増
幅回路の反転入力端子に接続すると共に前記第２のダイ
オードのカソードを第２の抵抗器を介して前記演算増幅
回路の反転入力端子に接続し、前記第２のダイオード及
び前記第２の抵抗器の接続点を第３の抵抗器を介して接
地し、前記第２及び第３の抵抗器の接続点より出力端子
を導出すると共に前記第３の抵抗器の抵抗値を第２の抵
抗器の抵抗値より小とする様にしたことを特徴とする理
想ダイオード回路。An input terminal is connected to a non-inverting input terminal of an operational amplifier circuit, an inverting input terminal of the operational amplifier circuit is grounded via a first resistor, and an output terminal of the operational amplifier circuit is connected to a first diode. the anode of the first diode is connected to the inverting input terminal of the operational amplifier circuit, and the cathode of the second diode is connected to the anode of the second diode through the second resistor. connected to an inverting input terminal of an operational amplifier circuit, a connection point between the second diode and the second resistor is grounded via a third resistor, and a connection point between the second and third resistors; An ideal diode circuit, characterized in that an output terminal is derived from the third resistor and the resistance value of the third resistor is smaller than the resistance value of the second resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1213283U JPS59119620U (en) | 1983-01-31 | 1983-01-31 | ideal diode circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1213283U JPS59119620U (en) | 1983-01-31 | 1983-01-31 | ideal diode circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59119620U true JPS59119620U (en) | 1984-08-13 |
Family
ID=30143537
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1213283U Pending JPS59119620U (en) | 1983-01-31 | 1983-01-31 | ideal diode circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59119620U (en) |
-
1983
- 1983-01-31 JP JP1213283U patent/JPS59119620U/en active Pending
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