JPS583640U - Chattering prevention circuit - Google Patents
Chattering prevention circuitInfo
- Publication number
- JPS583640U JPS583640U JP9682481U JP9682481U JPS583640U JP S583640 U JPS583640 U JP S583640U JP 9682481 U JP9682481 U JP 9682481U JP 9682481 U JP9682481 U JP 9682481U JP S583640 U JPS583640 U JP S583640U
- Authority
- JP
- Japan
- Prior art keywords
- prevention circuit
- flip
- flop
- chattering prevention
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のチャタリング防止回路の回路図、第２図
は本案の実施例に係る回路図である。
ＳＷｌ・５ｅｎｓｅスイツチ、Ｆｌ・・・・・−ＲＳＳ
フリップフロラフＳ・・四セット端子、Ｒ・曲リセット
端子、Ｑ。
互・・・・・・出力端子、Ｒ□□およびＲ□２・・間第
１都よび第２の抵抗。 ・FIG. 1 is a circuit diagram of a conventional chattering prevention circuit, and FIG. 2 is a circuit diagram according to an embodiment of the present invention. SWl/5ense switch, Fl...-RSS
Flip Flow Rough S...4 set terminals, R/song reset terminal, Q. Mutual...Output terminal, R□□ and R□2... between the first and second resistors.・
Claims (1)
セット端子のいずれか一方を選択的に接地してロジック
・ローとする吉共に、前記端子の他方を電圧供給回路網
から供給される電圧によりロジック・ハイとし、前記Ｒ
Ｓフリップフロップの一対の出力端子からそれぞれ制御
電圧を取出すようにしてなる前記スイッチのチャタリン
グ防止回路であって、 前記ＲＳフリップフロップの前記セット端子と同じロジ
ック関係にある前記出力端子の一方とを第１の抵抗を介
して接続し、前記リセット端子と 、 ゛同じロジッ
ク関係にある前記出方端子の他方を第２の抵抗を介して
接続して前記電圧供給回路網を形成したことを特徴とす
るチャタリング防止回路。[Claims for Utility Model Registration] A switch may selectively ground either the set terminal or the reset terminal of the RS flip-flop to make it logic low, and the other terminal may be grounded to logic low. Logic high due to the voltage applied to R
The chattering prevention circuit for the switch is configured to take out control voltages from a pair of output terminals of the S flip-flop, and the chattering prevention circuit is configured to output a control voltage from a pair of output terminals of the S flip-flop, the chattering prevention circuit being configured to output a control voltage from a pair of output terminals of the RS flip-flop, and one of the output terminals having the same logic relationship as the set terminal of the RS flip-flop. The reset terminal and the other output terminal having the same logic relationship are connected via a second resistor to form the voltage supply circuit network. Chattering prevention circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9682481U JPS583640U (en) | 1981-06-30 | 1981-06-30 | Chattering prevention circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9682481U JPS583640U (en) | 1981-06-30 | 1981-06-30 | Chattering prevention circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS583640U true JPS583640U (en) | 1983-01-11 |
Family
ID=29891653
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9682481U Pending JPS583640U (en) | 1981-06-30 | 1981-06-30 | Chattering prevention circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS583640U (en) |
-
1981
- 1981-06-30 JP JP9682481U patent/JPS583640U/en active Pending
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