JPS58170050A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58170050A JPS58170050A JP5312782A JP5312782A JPS58170050A JP S58170050 A JPS58170050 A JP S58170050A JP 5312782 A JP5312782 A JP 5312782A JP 5312782 A JP5312782 A JP 5312782A JP S58170050 A JPS58170050 A JP S58170050A
- Authority
- JP
- Japan
- Prior art keywords
- film
- region
- sbd
- forming
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims description 29
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- 238000005530 etching Methods 0.000 abstract description 9
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 238000001312 dry etching Methods 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 230000004888 barrier function Effects 0.000 abstract 2
- 238000000059 patterning Methods 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 150000004767 nitrides Chemical class 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000007514 turning Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241001523761 Digitipes Species 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- ZADPBFCGQRWHPN-UHFFFAOYSA-N boronic acid Chemical compound OBO ZADPBFCGQRWHPN-UHFFFAOYSA-N 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
- H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
- H01L27/0755—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0761—Vertical bipolar transistor in combination with diodes only
- H01L27/0766—Vertical bipolar transistor in combination with diodes only with Schottky diodes only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（１） 発明、の技術分野 、
本発明は半導体装置の製造方法、詳しくは厚いフィール
ド酸化膜を形成する際にマスクとして使用され良書化シ
・リコン膜をノリー二ンダで一部残し、当該膜を除去し
た領域にトランジスタを、また当該膜が残され九領域に
はＶ ｗ ｙ・トキパリャダイオードを形成する方法に
関する・
（２） 技術の分野
厚い酸化膜で囲まれた領域にトランジスタを形成した構
造において、当該領域にショッすキノ譬リヤダイオード
（・８３Ｄ）・とトランジスタを形成することが行なわ
れる。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device, and more specifically, a method for manufacturing a semiconductor device using a silicon film that is used as a mask when forming a thick field oxide film. (2) Technical Field Regarding the method of forming a transistor in the region where the film is removed and a V w y -tokyparya diode in the region where the film is left. (2) Technical field In a structure in which a transistor is formed in a region in which a transistor is formed, a transistor is formed in the region in which a photovoltaic rear diode (83D) and a transistor are formed.
第１図はかかる半導体装置を製造する工程における幽骸
装置の要部が断面で示される。同図を参照すると、先ず
その（ａ） Ｋ示されるように、ｐｍシリコン基板ＩＫ
は、全知の技術で、３〔＃■〕の厚さのＮ”ｆｆ１Ｊｌ
込層２．１〜１．５ ［Ｊｍ］の厚さのＮ型エピタキシ
ャル層３．１−１．５〔メ臘〕の厚さのフィールド酸化
膜４が、前記酸化膜形成時に能動素子形成領域をマスク
する九めに用いられ良書、化シリコン（Ｓｌ、Ｎ４）膜
５（以下窒化膜と−う）と共に示されている。なお窒化
膜４の下には１０００（１）種変の二酸化シリコン（８
１０，）膜６（熱酸化膜）が形成されている。FIG. 1 shows, in cross section, the essential parts of a ghost device in the process of manufacturing such a semiconductor device. Referring to the figure, first, as shown in (a) K, the pm silicon substrate IK
is an omniscient technique, and N”ff1Jl with a thickness of 3 [#■]
N-type epitaxial layer 3.1 to 1.5 [Jm] thick field oxide film 4 is formed in the active element formation region when the oxide film is formed. It is shown together with a silicon oxide (Sl, N4) film 5 (hereinafter referred to as a nitride film), which is used as a mask for masking. Note that under the nitride film 4, 1000 (1) type silicon dioxide (8
10,) A film 6 (thermal oxide film) is formed.
次に、全面にレゾスト膜（図示せず）を塗布し、それを
・譬ターニングして、例えばほう素（ｌ＋）をイオン注
入法で、加速エネルギー６０（Ｋ＠Ｖ）、ドーズ量５
Ｘ １０” （ＣＩＩＭ−２）でイオン注入して、深さ
約０．３ ［ｎｍ）のペース領域７を形成する〔同図（
ｂ）。Next, a resist film (not shown) is applied to the entire surface, and it is turned, and then, for example, boron (l+) is ion-implanted at an acceleration energy of 60 (K@V) and a dose of 5.
A pace region 7 with a depth of about 0.3 [nm] is formed by ion implantation with X 10'' (CIIM-2) [see the same figure (
b).
なお同図（ｂ）以下においてＮ＋型埋込層２は省略しで
ある。〕 “
次Ｋ例えば化学気相成長法（ｃｖｎ法）で５ｔＯ２膜８
を約３０００（ス〕の膜厚に成長させる。Note that the N+ type buried layer 2 is omitted from FIG. ] "Next K, for example, by chemical vapor deposition method (CVN method), 5tO2 film 8
is grown to a film thickness of approximately 3000 mm.
次いで、ＳＢＤ ｓ ペース、エミッタ電極９，１０゜
１１の窓開けのため、レジスト膜Ｒを形成し、それｆ
１４ターニングし、公知のエツチングによって前記した
窓開きを同図（ｄ）に示す如く′になす、なお第１図（
ｄ） 、 （・）、（ｆ）においては説明を容易にする
九め工程を模式的に示す。Next, a resist film R is formed to open windows for the SBD s paste and emitter electrodes 9, 10° 11, and
14 turns, and the above-mentioned window opening is made into '' as shown in FIG. 1(d) by known etching.
d), (・), and (f) schematically show the rounding process to facilitate explanation.
９をマスクする如＜ ’々ターニンクシ、ペース、エミ
ッタ電番窓１０．１１の領域の８１０２膜１２を工１
、チングすると、同図（ｇ）に′□示す構Ｉ得ら
れる。9. Machining the 8102 film 12 in the area of the turn comb, pace, and emitter number window 10.11 by masking 9.
, the structure shown in FIG. 2(g) is obtained.
引続き、全面に多結晶シリコン層（ポリシリコン層・・
・１示せず）を成長させ、不純物（燐−Ｐ）拡散により
エミッタ領域１４を形成し、ぼりシリコン層を除去し、
８ＢＤ電極窓９の領域の８に０２ＩＩをコントロールエ
ツチングで除去し、例えばアル建ニウム（ムｔ）配線層
を形成する。なお上記の工程において、エミ、り電極廖
は拡散寝ともなるので、自己整合法により高集積化集積
回路（ＩＣ）の形成が可能となる。ま７’？、８ＢＤ窓
９の領域に８１０２膜を残す理由は、ぼりシリコン層除
去のエツチングの際当該エツチングのストッ／＃とする
ためである。Subsequently, a polycrystalline silicon layer (polysilicon layer...
・1) is grown, an emitter region 14 is formed by diffusion of impurities (phosphorus-P), and the silicon layer is removed.
02II is removed by controlled etching in the region 8 of the 8BD electrode window 9 to form, for example, an aluminum (mut) wiring layer. In the above process, since the emitter and electrode holes also serve as diffusion holes, it is possible to form highly integrated integrated circuits (ICs) by the self-alignment method. Ma7'? The reason why the 8102 film is left in the region of the 8BD window 9 is to serve as a stopper for the etching during etching to remove the raised silicon layer.
（３） 従来技術と問題点 ゛上記従来技
術においては、第１図（ｄ）から（ｆ） ｔでを参照し
て説明し喪工程が必要である。その理由について説明す
ると、ＩＣの集積度を高めるＫついて、レジストの／４
ターン巾をＩ Ｃｐｍ） １１度に形成する必要がある
。ネがテ（プ型のレジストにおいては、露光しない部分
のレジストを残すので、露光に際してマスクに覆われ九
部分（残す部分）に光が回りこんで／譬ターン巾が乱れ
、更には埃、＊の後に残る部分が膨潤して／４ターン巾
を細くする。(3) Prior art and problems ゛The above prior art requires a mourning process, which will be explained with reference to FIGS. 1(d) to 1(f)t. To explain the reason, for K, which increases the degree of integration of IC, the resist
It is necessary to form a turn width of I Cpm) 11 degrees. In the case of a tape type resist, parts of the resist that are not exposed to light are left behind, so during exposure, the light is covered by a mask and the light goes around to the parts (the parts to be left), which disturbs the pattern width and also causes dust, etc. The part that remains after swells and reduces the width by 4 turns.
かくして、微細・やターンの形成には露光しない部分が
残るヂジティプ型レジスト（デジレジスト）が用いられ
るようになった。前記した電極窓まで第１図（ｇ）に・
示す構造を得るには、第２図に模式的に示される工程を
とシたい、つま夛５ｉｏ２膜８′（前記した５ｉｎ２膜
６と５１０２膜８とが一体化したもの）の上に第１のレ
ジスト膜Ｒ１を塗布し、それを電極窓形成のためツタタ
ーニングし、８１０．Ｉ［８’のエツチングが図示の如
く半ば遂行したところでとの工、チングを中止し、第２
のレジスト膜Ｒ２を全面に塗布し、それを８ＢＤ窓９の
みをマスクする如く）臂ターニングし、ペース、エミッ
タ電極窓１０．１１の領域の残存５ｔＯ２膜をエツチン
グすれば、第１図（ｇ）に示す構造が得られる。しかし
、微細ノ豐ターンに適したデジレジストでレゾスト膜で
Ｒ１ｔＲ２を作ること、すなわちデジレジストの二重マ
スク化はできないので、第１図（ｄ）〜（ｆ） Ｋ示し
た工程が必要となるのである。このことは、半導体ＩＣ
の製造における工程数の増加、すなわち製造歩留りの低
下の間鵜を生ずる。As a result, digitip type resists (digiresists), which leave unexposed areas, have come to be used to form fine patterns and turns. As shown in Figure 1 (g) up to the electrode window mentioned above.
In order to obtain the structure shown in FIG. 2, it is necessary to carry out the steps schematically shown in FIG. A resist film R1 of 810. When the etching of I[8' is halfway completed as shown in the figure, the etching is stopped and the second etching is completed.
If a resist film R2 is applied to the entire surface, it is turned (so as to mask only the 8BD window 9), and the remaining 5tO2 film in the area of the paste and emitter electrode windows 10 and 11 is etched, as shown in FIG. 1(g). The structure shown is obtained. However, it is not possible to make R1tR2 with a resist film using a digirest suitable for fine pattern turns, that is, it is not possible to double mask the digirist, so the steps shown in Fig. 1 (d) to (f) K are required. It is. This means that semiconductor IC
This results in an increase in the number of steps in the manufacturing process, which leads to a decrease in manufacturing yield.
（４） 発明の目的
本発明は上記従来の問題点に鑑み、例えば８１１Ｄとト
ランジスタの結合した半導体装置の製造において、゛ホ
トリソダラフィエｌｉにおいて゛すべてｓｔ−、ｐレジ
スト−を用い九ドライエ、チング方式となし、従来要求
され九工程数を減少し九半導体装置の製造方法・を提供
するＫある。 □ 。(4) Purpose of the Invention In view of the above-mentioned problems of the prior art, the present invention is aimed at, for example, in manufacturing a semiconductor device in which an 811D and a transistor are combined. The present invention provides a method for manufacturing a semiconductor device by reducing the number of steps conventionally required. □.
（５）発明の構成
そしてこの目的は本発明によれば、半導体基板に設けた
厚い酸化膜で囲まれた領域にシ１．トキパリャダイオー
ドと他の能動素子とを形成する方法において、前記酸化
膜形成にマスクとして用いた窒化シリコン膜を一部残し
て除去し、窒化シリコン膜の除去された領域には前記他
の能動素子をまた会化シリ□コン膜の残存せしめられた
領域にはシ、ットキパリャダイオードを形成することｔ
％徴゛とする半導体装置の製造方法を提供することによ
〕達成される。(5) Structure and object of the invention According to the present invention, a 1. In a method for forming a tokipalya diode and other active elements, the silicon nitride film used as a mask for forming the oxide film is removed, leaving a part of the silicon nitride film, and the other active element is formed in the area where the silicon nitride film is removed. The element is also formed in the remaining region of the silicon film to form a separate diode.
This is achieved by providing a method for manufacturing a semiconductor device that has the following characteristics:
（６）発明の実施例 ゛以下本発
明実施例を図面によりて詳述する。(6) Embodiments of the invention ゛Examples of the present invention will be described in detail below with reference to the drawings.
第３図に本発明の方法を実施する工程における半導体装
置の要部が断面で示され、同図において既に図示された
ものと同じ部分は同じ符号を付して示す。FIG. 3 shows a cross section of the main parts of a semiconductor device in the process of carrying out the method of the present invention, and the same parts as those already illustrated in the figure are designated by the same reference numerals.
同図（ａ）には、Ｐ型シリコン基板ＩＫ公知の技術で３
〔μｍ〕の厚さのＮ＋型埋込層２．１〜１．５〔１１ｍ
〕の厚さのＮ型エピタキシャル層３．１〜１．５〔μｍ
〕の厚さのフィールド酸化膜４が形成された構造が、フ
ィールド酸化膜の形成のときマスクとして用いられた窒
化シリコン（８１，Ｎ４）膜５（窒化膜）と共に示され
、窒化膜５の下には熱酸化で形成した１０００［χ〕の
厚さの８１０２ＩＩ６がある。Figure (a) shows a P-type silicon substrate IK using a known technique.
N+ type buried layer with a thickness of [μm] 2.1 to 1.5 [11 m]
) with a thickness of 3.1 to 1.5 [μm
A structure in which a field oxide film 4 with a thickness of There is 8102II6 with a thickness of 1000 [χ] formed by thermal oxidation.
次に同図伽）に示されるように、シ、ットキパリャダイ
オード（ＳＢＤ ）を形成する領域にのみ窒化膜５′が
残るよう窒化膜５を・母ターニングする。なおｌｉ’Ｆ
Ｉ図（ｂ）以下において埋込層２は省略する。Next, as shown in FIG. 3), the nitride film 5 is turned so that the nitride film 5' remains only in the region where a switch diode (SBD) is to be formed. Naoli'F
The buried layer 2 is omitted from FIG. 1(b) onwards.
窒化８！１５′をマスクとして、はう素（Ｂ＋）をイ第
２□い工、より、加速、え４．二、。〔え、７３１．′
一ズ１ｉ５ｘｌｏ Ｃｃｍ ）でイオン注入して、
深さ０．３〔μｍ〕のベース領域７を修成する〔同図（
６）〕。Using nitride 8!15' as a mask, add boronic acid (B+) to the second layer, accelerate the process, and accelerate the process.4. two,. [Eh, 731. ′
Ion implantation was carried out at 1i5xlo Ccm).
Repair the base region 7 to a depth of 0.3 [μm] [same figure (
6)].
次いで同図偵）に示される如く、全面に二酸化シリコン
（８１０２）層８を３０００（Ｘ）の厚さに化学気相成
長法（ｃｖｎ法）で形成する。Next, as shown in the same figure, a silicon dioxide (8102) layer 8 is formed on the entire surface to a thickness of 3000 (X) by chemical vapor deposition (CVN method).
次いで、全面に／ゾレジスト層を塗布形成し、公知の／
ダターニングおよびドライエ、チング工程によってベー
ス領域７表面の８１０．８１１６及び８にベース電極窓
１０、巾が１〜２ （＃ｍ）のエミ、り電極窓１１及び
８ＢＤ （電極）形成用廖を形成する。この工程におい
て、残存窒化膜５′は、８ＢＤ（電極）形成領域をマス
クする０以上管での工程は、窒化膜５′を残す点を除く
と、従来技術における工程と同じである。Next, a /zoresist layer is applied and formed on the entire surface, and a known /solesist layer is formed.
A base electrode window 10, a width of 1 to 2 (#m), an emitter electrode window 11 and a groove for forming 8BD (electrode) are formed at 810.8116 and 8 on the surface of the base region 7 by data turning, drying and etching processes. do. In this step, the remaining nitride film 5' masks the 8BD (electrode) forming region, and the step with 0 or more tubes is the same as the step in the prior art except that the nitride film 5' remains.
次に、同図（ｆ）に示される如く、ＣＶＤ法でぼりシリ
コン層ｔｓｔ−ｓｏｏ［Ｘ）の厚さに成長する。Next, as shown in FIG. 3(f), a silicon layer is grown to a thickness of tst-soo[X] using the CVD method.
次に、全面に燐シリケートガラス（Ｐ２Ｏ）層管形成し
、それがエミッタ電極窓１１のみを橿う如くに残余部分
を除去し、１１５０（Ｃ）で３０〔秒〕熱処理してＰ２
Ｏ層にｊ″含）れる燐（Ｐ）成分を拡散させてエミッタ
領域１４を形成した験弗駿系の液を用いてＰ２Ｏを洗い
流す。Next, a layer of phosphorus silicate glass (P2O) is formed on the entire surface, the remaining part is removed so that it covers only the emitter electrode window 11, and heat treated at 1150 (C) for 30 [seconds] to form a P2O layer.
The P2O is washed away using an experimental liquid in which the emitter region 14 is formed by diffusing the phosphorus (P) component contained in the O layer.
次に、同図へ）に示されるように、全図にデジレジスト
膜（図示せず）を形成し、公知め技術でそれをノーター
ニングし、ドライエツチングで４リシリコン層と窒化膜
５′を除去し、ＳＢＤ電極窓９を形成する。９化膜５′
の・譬ターンの図に見て右端部分＃−１Ｓ１０２膜６上
に残る。Next, as shown in the same figure), a digi-resist film (not shown) is formed on the entire figure, it is not-turned using a known technique, and the silicon layer and nitride film 5' are removed by dry etching. Then, the SBD electrode window 9 is formed. 9 film 5'
The right end portion #-1 remains on the S102 film 6 as seen in the illustration of the parable turn.
次に、デジレジスト膜（図示せず）を全面に形ｈ（し’
、−’、それを８ＢＤ領域のみさらされる如くにノータ
ーニングシ、コントロールエツチン／テ８ＢＤＩＩｍに
残存していた５ｉｎ２膜６を除去する〔同図０）〕。Next, apply a digi-resist film (not shown) to the entire surface.
, -', the 5in2 film 6 remaining on the control film/te 8BDIIm is removed without turning so that only the 8BD region is exposed [FIG. 0)].
次に、全面に約１〔μｍ〕の厚さのアルミニウム配＃層
１５を形成する〔同図（ｊ）〕。以後の工程は公知の技
術により所望の半導体装置を完成する。Next, an aluminum wiring layer 15 with a thickness of about 1 [μm] is formed on the entire surface [FIG. 6(j)]. In the subsequent steps, a desired semiconductor device is completed using known techniques.
（７）発明の効果
以上、詳細に説明し九ように、本発明の方法によるとき
は、微細ノ臂ターンの形成に適したデジレノストのみを
用い、従来の工程よシも少ない数の工程で、絶縁膜に囲
まれ要領域内にＳＢＤとトランゾスタが形成されるので
、当該デバイスの製造歩留９の向上と、ＩＣの高集積化
に効果的である。(7) Effects of the Invention As explained in detail above, when using the method of the present invention, only Digirenost suitable for forming fine arm turns is used, and the number of steps is smaller than that of the conventional process. Since the SBD and the transistor are formed within the required area surrounded by the insulating film, it is effective for improving the manufacturing yield 9 of the device and increasing the integration density of the IC.
第１図は従来の半導体装置の製造工程におけるその要部
の断面図、１１ｇ２図はレジスト膜の二重マスク化を説
明する九めの断面図、第３図は本発明の方法を実施する
工程における半導体装置の要部の断面図である。
ｌ・・・Ｐ型シリコン基板、２・・・Ｎ”ｆｆ１ｊｌ込
層、３・・・？ｌｌエピタキシャル層、４・・・酸化シ
リコン膜、５・・・窒化シリコン膜、６・・・熱酸化膜
、７・・・ベース領域、８・・・酸化シリコン膜、９・
・・８ＢＤ１１＠ｇ、 １０・・・ペース電極窓、１１
・・・エミッタ電極窓、１２・・・酸化シリコン膜、１
３・・・Ｉリシリコン７１１．１４・・・ニオ、夕領域
、１５・・・ムを配ａｍ。
１１１図
第１図
第２図
１Ｉ３図
第３図Fig. 1 is a cross-sectional view of the main parts in a conventional semiconductor device manufacturing process, Fig. 11g2 is a ninth cross-sectional view illustrating double masking of the resist film, and Fig. 3 is a step of implementing the method of the present invention. FIG. 1...P-type silicon substrate, 2...N"ff1jl layer, 3...?ll epitaxial layer, 4...silicon oxide film, 5...silicon nitride film, 6...thermal oxidation Film, 7... Base region, 8... Silicon oxide film, 9.
...8BD11@g, 10...Pace electrode window, 11
...Emitter electrode window, 12...Silicon oxide film, 1
3...I silicon 711.14...Nio, evening area, 15...Am distributed. 111Figure 1Figure 2Figure 1I3Figure 3
Claims (1)
し、かかる素子領域にシ、ツ、トキノ臂リヤダイオード
と他の能動素子とを形成する方法にして、前記絶縁膜形
成用マスクとして用い良書化シリコン膜を選択的に除去
し、該窃化シリコン膜の除、去された領域には前記他の
能動素子を、また該窒化シリコン膜の残存せしめられ九
領域にシロットキパリャダイオードを形成する工程を有
することを特徴とする半導体装置の製造方法。A method is provided in which an insulating film is selectively provided on a semiconductor substrate to define an element region, and a rear diode and other active elements are formed in the element region, and the mask for forming the insulating film is formed. The silicon nitride film is then selectively removed using the silicon nitride film, and the other active elements are placed in the removed area, and the silicon nitride film is removed in the remaining nine areas. A method for manufacturing a semiconductor device, comprising a step of forming a diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5312782A JPS58170050A (en) | 1982-03-31 | 1982-03-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5312782A JPS58170050A (en) | 1982-03-31 | 1982-03-31 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58170050A true JPS58170050A (en) | 1983-10-06 |
Family
ID=12934137
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5312782A Pending JPS58170050A (en) | 1982-03-31 | 1982-03-31 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58170050A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0717844U (en) * | 1993-09-10 | 1995-03-31 | 桐生機械株式会社 | Manhole cover locking device |
-
1982
- 1982-03-31 JP JP5312782A patent/JPS58170050A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0717844U (en) * | 1993-09-10 | 1995-03-31 | 桐生機械株式会社 | Manhole cover locking device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0415938A (en) | Formation of contact hole | |
| JPH035058B2 (en) | ||
| US5395782A (en) | Process for fabricating a semiconductor integrated circuit | |
| JPS58170050A (en) | Manufacture of semiconductor device | |
| JPH04107831A (en) | Manufacture of semiconductor device | |
| JPS5846846B2 (en) | hand tai souchi no seizou houhou | |
| JPS58194345A (en) | Semiconductor device | |
| JPS6220711B2 (en) | ||
| JPS63313866A (en) | Manufacture of semiconductor device | |
| KR100256259B1 (en) | Method of preparing common gate in semiconductor device | |
| JPS6211514B2 (en) | ||
| JPH0410662A (en) | Manufacture of semiconductor device | |
| KR100277875B1 (en) | Capacitor Manufacturing Method | |
| JPS6038874B2 (en) | Method for manufacturing insulator gate field effect transistor | |
| JPS63288069A (en) | Manufacture of mos type semiconductor element | |
| JPH0139221B2 (en) | ||
| JPH01165159A (en) | Manufacture of complementary mos semiconductor device | |
| JPS6049677A (en) | Manufacture of field-effect transistor | |
| JPH038338A (en) | Manufacture of multilayer wiring structure | |
| JPH03211836A (en) | Manufacture of semiconductor device | |
| JPS6161546B2 (en) | ||
| JPH06120243A (en) | Manufacture of semiconductor device | |
| JPH01280352A (en) | Manufacture of semiconductor device | |
| JPH02114537A (en) | Manufacture of semiconductor integrated circuit device | |
| JPH0445523A (en) | Manufacture of semiconductor device |