JPS58169260A - Display for stored data - Google Patents

Abstract

PURPOSE:To display stored data without relaying of a program and to simplify the constitution of a display, by displaying the stored data on an optional address of an RAM at an optional time regardless of the operation of a processor. CONSTITUTION:In an address setter 1, a monitor address is set and an address on a processor address bus 8 and the address set in the setter 1 are switched by an address switching circuit 2 and stored in a storage device 3. To this device 3, a latch circuit 4 is connected through an RAM data bus ID and to the circuit 4, a display 5 is connected; and a data output buffer 6 and a data input buffer 7 connected to a processor data bus D are connected to the bus ID. To the stored data read enable terminal OE and write enable terminal WE of the devide 3, logical circuits for inputting their selection signals are connected. Then, the circuit 4, buffers 6 and 7, etc., are used to display the data on an optional address of the device 3 on the display 5 at an optional time regardless of the operation of the processor.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory element (Randim Accesssie) capable of reading and writing data in a computer system using a microcombi, etc. as a processing unit.
It is related to a storage data display device for displaying storage data at an arbitrary address of a memory (hereinafter abbreviated as ILAM). Or, for the purpose of monitoring variable data, you may want to display and recognize data stored at an arbitrary address in the attached RAM. This program is called a monitor program stored in the program section. However, there have been methods such as comparing the RAM address data output from the processing device with the monitor address data of the address setter, and when they match, storing and displaying the data on the processing device data bus. According to the conventional method, it is necessary to temporarily suspend the execution of the program of the processing device that is supposed to be executed, or to
When there is no data read or write request from the processing device to M, data at a predetermined address is stored 9
The present invention aims to solve the above-mentioned problems, and allows the display of any address in the RAM regardless of the operation of the processing device. This invention realizes a stored data display device that can display stored data at any time.The present invention will be explained in detail below based on the drawings of one embodiment. In the block diagram showing one embodiment of the device, 1 is an address setter for setting data of a monitor address M, 2 is an address switching circuit, and is connected to a processing device (such as a microcombi, etc.).
When the logic state of the storage device selection signal C8 inputted from the storage device selection signal C8 (not shown) is “0”, the monitor address M set by the address setter 1 is set to the storage device selection signal C8.
When the logic state of 8 is "1", the address data N on the processing device address bus 8 input from the processing device together with the storage device selection signal C8 is transferred to each RAM address line A.
Output to.

3 is a storage device consisting of a commonly used RAM;
The logic state of the storage device enable terminal CB is "1" and the logic state of the storage data read enable terminal OR is "I".
J, the address data specified by the address data output to the RAM address line is RA
M data bus IDK read, storage device enable terminal C
When the logic state of B is "1" and the logic state of the data write enable terminal WE is "1", the data on the RAM data bus ID is transferred to the address specified by the address data output to the RAM address line. It is designed to be written. In the zero device, the logic state of the storage device enable terminal CE is always "1". 4 is a data latch circuit, and when the logic state of the storage device selection signal CB is "0", the RAM is The data on the data bus ID is output to the display data line ND, and when the logic state of the storage device selection signal C8 becomes "1", the data on the R, AM data bus ID at that time is stored, and then the storage device selection signal C8 is stored.
The configuration is such that the logic state of 8 can be maintained until it becomes "0".

Reference numeral 5 denotes a display made of a semiconductor element or the like for displaying the data stored in the storage device 3 which is outputted to the display data line ND; A data output buffer 7 is a data buffer for inputting the data of the processing unit data bus D to the RAM data bus ID, OGI is an OR circuit with a negative input terminal, and GL and AG2 are AND circuits. In the device, a data read request signal RD is sent from the processing device of the microcombi and -Tanato to the storage device 3.
When neither the data write request signal WR nor the data write request signal WR are issued, the logic state of the storage device selection signal C8 is "0". At this time, the address switching circuit 2
The monitor address M set by is output to the RAM address line.

On the other hand, since the logic state of the output of the AND circuit G1 becomes rOJ, the output from the data output buffer 6 to the processing device data bus D is prohibited, and the logic state of the output of the AND circuit G2 also becomes rOJ. Therefore, writing of data ' into the storage device 3 and inputting data from the data manual buffer 7 to the RAM data bus ID are prohibited.

At the same time, the logic state of the output of the OR circuit OGI with a negative input terminal, that is, the data read enable terminal OE of the storage device 3 becomes "L", so that the monitor address M output to the RAM address line A is specified. The stored data at the address of the storage device 3 is transferred to the RAM data bus ID.
At this time, the data latch circuit 4 outputs the stored data of the storage device 3, which is read to the RAM data bus ID, as it is to the display data line ND. The storage data at the address specified by the monitor address M set by the address setting device 1 is displayed on the display 5 without being affected by the data 1. Next, data 1 is sent from the processing device to the storage device 3. A period in which there is a read request of 1 will be explained. At this time, the logical states of the storage device selection signal C8 and the data read request signal RD are both "1".

The operation by which the processing device reads stored data from the storage device 3 is as follows.The 0 address switching circuit 2 outputs the address data N on the processing device address bus 8 to the RAM address line A in response to the storage device selection signal C8. The logical state of the output of the AND circuit AGI becomes rlJ, and the output of the OR circuit OGI with a negative input terminal, that is, the data read enable terminal of the storage device 3 is ON! The logical state of is "1"
Therefore, the data stored in the storage device 3 specified by the address data N on the processing device address spring 8 output to the RAM address line is read out to the RAM data bus ID, and is transferred to the processing device data bus D through the data output buffer 6. Output to.

At this time, the data latch circuit 4 stores and holds the storage data of the storage device 3 that was read out to the RAM data bus ID immediately before the processing device requests the storage device 3 to continue data. On day 1, the data stored in the storage device 3 designated by the monitor address M set by the address setter 1 remains displayed.

In addition, we will explain the period during which a data write request is made from the processing device to the storage device 3. At this time, the logical states of the storage device selection signal C8 and the data write request signal WR are both "1". The operation in which the processing device writes data to the storage device 36ζ is as follows.The address switching circuit 2 outputs the address data N on the processing device address bus 8 to the fifth RAM address line ζ in response to the storage device selection signal C8. . Since the logic state of the output of the AND circuit AG2, that is, the data write enable terminal WB of the storage device 3 becomes "1", the write data on the processor data bus D is inputted to the RAM data bus ID through the data manual buffer 7. , RAM address line AE is stored at the address of the storage device 3 specified by the address data N on the processor address bus 8. At this time, the data latch circuit 4 is transferred from the processing device to the storage device 3.
The monitor address M set by the address setter 1 is displayed on the display 5 in order to store and hold the data stored in the storage device 3 that was read to the RAM data bus ID immediately before a data write request was made to the RAM data bus ID. The data stored in the specified storage device 3 remains displayed. As explained in detail above, according to the present invention, data can be transferred from the processing device to the storage device without interrupting the execution of the program of the processing device. Even if there is no request to display or write data, it is possible to display the stored data at any address in the storage device set by the address setting device at any time, regardless of the operation of the processing device. In addition, in the normal case, the RAM address line is connected to the processor address bus, the storage device enable terminal CB is connected to the storage device selection signal, and the data read enable terminal OB is connected to the data read request signal. RD, the data write enable terminal wg is connected to the data write request signal WRJ, and the RAM data bus is connected to the processing device data bus D, so it is not necessary to build this device in the storage device in advance. It is also possible to connect this device in place of the original storage device and display the stored data whenever necessary.

[Brief explanation of drawings]

The figure is a block diagram showing one embodiment of the stored data display device according to the present invention.O1... Address setter, 2... Address switching circuit, 3... Storage device, 4...
・Data latch circuit, 5...Display device, 6...
...Data output buffer 7.7...Data manual buffer, 8...Processing device address bus, M.
---Monitor address, N...Address data, M...RAM address line, ID...
...RAM data bus, ND...Display data line, D...Processing device data bus, RD...
...Data read request signal, WR...Data write request signal Patent applicant Representative of Toyo Denki Seizo Co., Ltd. Atsushi Doi Procedural amendment (voluntary) April 2g, 1980 Commissioner of the Japan Patent Office Tono 1 , Indication of the case Patent Application No. 51300 λ of 1988 Invention Memory Data Display Device 3, Person making the amendment Relationship with the case Patent applicant Postal code 104 2-7-2-4 Yaesu, Chuo-ku, Tokyo; Drawings subject to correction

Claims (1)

[Scope of Claims] An address setting device for setting a monitor address, and an address setting device for setting a monitor address when there is no request for displaying or writing data to RAM E from a processing device such as a microcombi, etc. When there is a request from the processing device to display or write the monitor address data to the RAM, k is an address switching circuit that inputs the address and response data on the processing device address bus to the RAM address line, respectively. and RA from the processing device.
When there is no data read or write request for M, the data read on the M data bus is output to the display data line as display data. When there is a request from the processing unit to display or write data to RAM K, the data that was read out on the RAM data bus immediately before is stored and held until the request is no longer made and the data is displayed. A data latch circuit that outputs data to the data line, a display device that displays data on the display data line, and a RAM from the processing device.
When there is a request to expose data to the processing unit, there is a data output buffer for outputting the data on the ILAM data bus to the processing device data bus, and when there is a request to write data from the processing device to the RAM. Building II! A storage data display device 0 characterized in that it includes a data buffer for inputting data on a data bus to a RAM data bus.