JPS5816559A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5816559A JPS5816559A JP56113712A JP11371281A JPS5816559A JP S5816559 A JPS5816559 A JP S5816559A JP 56113712 A JP56113712 A JP 56113712A JP 11371281 A JP11371281 A JP 11371281A JP S5816559 A JPS5816559 A JP S5816559A
- Authority
- JP
- Japan
- Prior art keywords
- type
- layer
- diffusion
- epitaxial
- impurity concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 10
- 238000009792 diffusion process Methods 0.000 abstract description 12
- 238000002955 isolation Methods 0.000 abstract description 9
- 238000005468 ion implantation Methods 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 3
- 238000002513 implantation Methods 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- RNNBHZYEKNHLKT-UHFFFAOYSA-N isopropylmethylpyrazolyl dimethylcarbamate Chemical compound CC(C)N1N=C(C)C=C1OC(=O)N(C)C RNNBHZYEKNHLKT-UHFFFAOYSA-N 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/8605—Resistors with PN junctions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は半導体装置の製法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.
半導体集積回路装置（以下ＩＯ）を形成する場合におい
て、第１図に示すようＫ例えば高抵抗のＰ−型別半導体
基板１上に一部でＮ＋型塩込層２を介しズ比較的低不純
物濃置ドープＮ−型Ｓｔ半導体層３をエピタキシャル成
長させ、このＮ″″ｓ１″８１層３らＰ−基板に接続す
るＰ＋型アインレーション４（分離層）で囲んだ部分を
素子領域として、ＮＰＮトランジスタ等をつ（りこむが
、このＮＰＮ）ランジスタのＰ中型ベース拡散と同時に
抵抗領域５を形成することが知られている。When forming a semiconductor integrated circuit device (hereinafter referred to as IO), as shown in FIG. A heavily doped N-type St semiconductor layer 3 is epitaxially grown, and a portion surrounded by a P+-type inlation 4 (separation layer) connected to the P- substrate from this N''s1''81 layer 3 is used as an element region to form an NPN transistor. It is known to form the resistance region 5 at the same time as the P medium base diffusion of the NPN transistor.
ところで、高耐圧のＩＯの場合、Ｎ−８１層３の不純物
濃度を小さくとってあり、一方、抵抗となるＰ＋島領域
の端子ＶＣ＠続したＡｊ配置１６をＮ−８ｉ層表面に絶
縁膜（８ｉ０．）７を介して延在させたり、低電位のＡ
ｊ配■がＰ＋抵抗５とアイソレージ冒ン４とめ間を通過
するためＫＰ＋抵抗領域５とＰ＋アイソレージ曹ノン４
の間ＶＣ寄生ＭＯ８＆Ｃよる反転層を生じ、抵抗のリー
クとなる問題があった。このような寄生ＭＯ８対策とし
て、（１）Ｐ中抵抗領域とＰ＋アイツレ−・シ曹ンの間
のＮ−８１′層表面に工電ツタ拡散による高湿［Ｎ中領
域８をナヤネルストッパとして設ける方法、（２）表面
に高電位のＡＪ膜をオーバラップさせる方法が従来より
採られている。しかしく１）Ｋよればチャネルストッパ
の幅ｄ、、ｄ、’に応じて抵抗をアイソレージ曹ンから
引き離すために抵抗のレイアウト（ある偽は寸法！Ｄが
変り、パターンの高密度化が困難となり、又（２）によ
ればＡＩ膜をオーバラップさせることで配線レイアウト
が複雑化する等の欠点があった。By the way, in the case of a high breakdown voltage IO, the impurity concentration of the N-81 layer 3 is kept low, and on the other hand, an insulating film ( 8i0.) Extending through 7 or lower potential A
Since j distribution passes between P+ resistance 5 and isolation range 4, KP+ resistance area 5 and P+ isolation range 4
During this period, an inversion layer was formed due to the VC parasitic MO8&C, which caused a problem of resistance leakage. As a countermeasure against such parasitic MO8, (1) high humidity caused by the diffusion of industrial ivy on the surface of the N-81' layer between the P medium resistance region and the P+ high resistance region [using the N medium region 8 as a Nayanel stopper]; (2) A method of overlapping a high potential AJ film on the surface has been conventionally adopted. However, 1) According to K, in order to separate the resistor from the isolation circuit according to the width d,,d,' of the channel stopper, the layout of the resistor (some false dimensions! D changes, making it difficult to increase the density of the pattern. Also, according to (2), there were drawbacks such as overlapping the AI films, which made the wiring layout complicated.
本発明は上記した欠点を取り除くためＫなされたも゛の
であり、高密度化を損うことなく、を生ＭＯ８を防止し
た高耐圧ＩＯの提供にある。The present invention has been made to eliminate the above-mentioned drawbacks, and its purpose is to provide a high voltage IO that prevents the generation of MO8 without impairing high density.
第２図は本発明の原理的構造を示す半導体装置の断面図
である。本発明によれば、抵抗のＰ＋抵抗領域５を形成
するエピタキシャル８ｉ層３′において表面よりＮ型不
純物、例えばリンをイオン打込みにより導入し、拡散さ
せｓｉ層の比抵抗を下げることすなわち、他のアイツレ
−、トされたエピタキシャル層（図示せず）よりも高濃
度にすることによってエピタキシャル層表面に反転層を
生じにくくエミッタ拡散によるチャネルストッパ等を用
いることなくを生ＭＯ８の生じるのを防止するものであ
る。このような本発明によれば、Ｎ十エミッタ拡散によ
るチャネルストッパの＃１ｄｔ−ｄ＊の和だけ抵抗領域
の抵抗の寸法ｉｔを従来の場合の！、よりも太き（する
ことができ、特に高抵抗を形成する場合に有利である。FIG. 2 is a sectional view of a semiconductor device showing the basic structure of the present invention. According to the present invention, an N-type impurity, for example, phosphorus, is introduced from the surface of the epitaxial 8i layer 3' forming the P+ resistance region 5 of the resistor by ion implantation, and is diffused to lower the resistivity of the Si layer. It is possible to prevent the formation of raw MO8 without using a channel stopper or the like by emitter diffusion by making the concentration higher than that of the epitaxial layer (not shown) that has been etched. It is. According to the present invention, the resistance dimension it of the resistance region is reduced from the conventional case by the sum of #1dt-d* of the channel stopper due to N+ emitter diffusion! , which is advantageous especially when forming a high resistance.
又、本発明によれば、高電位のＡ！膜をオーバーラツプ
させる場合忙比べて構造的にも簡単になる。Further, according to the present invention, high potential A! If the membranes are overlapped, the structure will be simpler than if the membranes were overlapped.
第３図はＩＯにおいてＰ＋抵抗領域による抵抗を形成す
る場合の拡散レイアウトパターンの例を示すもので、５
がＰ＋抵抗領域、９がそのコンタクト穴を示している。Figure 3 shows an example of a diffusion layout pattern when forming a resistance using a P+ resistance region in an IO.
indicates the P+ resistance region, and 9 indicates its contact hole.
Ｎ型エピタキシャル層４′の不純物濃度は、通常３Ω−
ｃｍ〜５Ω−ｃｍのエピタキシャル層においてリンネ線
動をｌＸｌ０”〜５Ｘ １０ ” ａｔｏｍｓ／ｄ糧度
が適当である。一般に抵抗の耐圧ＢＹ、は
ＢＶ、２ＢＶＣ１，）ＢＹｃｌｏ
であり、エピタキシャル層を少し高濃度にしてもＢｖｃ
、。以下になることはなく、回路的に耐圧としてはＢｖ
ｏ。を用いるので十分保証される。The impurity concentration of the N-type epitaxial layer 4' is usually 3Ω-
In an epitaxial layer of cm to 5 Ω-cm, a Rinne linear motion of 1X10'' to 5X10'' atoms/d is suitable. In general, the withstand voltage BY of a resistor is BV,2BVC1,)BYclo, and even if the epitaxial layer is made a little highly doped, Bvc
,. It will never go below Bv, and the circuit withstand voltage is Bv.
o. is used, so it is fully guaranteed.
第４図（ａ）〜（ｄ）は本発明をＩＪ ニア−Ｉ”１回
路を含む高耐圧ＩＯのプロセスに適用した場合の実施例
を各工程ごとに図示したものである。FIGS. 4(a) to 4(d) illustrate each step of an embodiment in which the present invention is applied to a high breakdown voltage IO process including one IJ near-I" circuit.
（ａｌ 通常の高耐圧ＩＯのプロセス忙従って、高抵
抗Ｐ−型８ｉ基板１上に部分的Ｎ中拡散によりＮ十埋込
層２を形成し、この上に低不純物濃度のＮ−型８ｉ層３
をエビタキシャＡＩ成長させる。この後、８４層の表面
酸化膜７をマスクにＢ（ボロン）を深いイオン打込みま
たは拡散によりＰ型アイソレージ曹ン（素子分離領域）
４を形成する。(al) Due to the usual high-voltage IO process, an N0 buried layer 2 is formed on a high-resistance P-type 8i substrate 1 by partial N diffusion, and on top of this an N-type 8i layer with a low impurity concentration. 3
Let Ebitakisha AI grow. After this, using the 84-layer surface oxide film 7 as a mask, B (boron) is deeply ion-implanted or diffused to form P-type isolation carbon (element isolation region).
form 4.
−図にお−て、■はリニア（高耐圧リニア）部、■は抵
抗部、■はＩ”Ｌ部をそれぞれ形成すべき領域とする。- In the figure, ◯ indicates a region where a linear (high breakdown voltage linear) portion, ◯ indicates a resistance portion, and ◯ indicates an area where an I''L portion is to be formed.
、（ｂ） リニア部Ｉの表面に酸化膜等によるマスク
１０を形成し、抵抗部■、ＩＬＬ部■のＮ８ｉ層［Ｐ（
リン）をイオン打込みする。なお、リニア部Ｉにおいて
コレクタ取出し部（ＯＮ）＆Ｃは同時［１３ンをイオン
打込みを行なう。, (b) A mask 10 made of an oxide film or the like is formed on the surface of the linear part I, and the N8i layer [P(
ion implantation of phosphorus). In addition, in the linear part I, the collector extraction part (ON) &C perform ion implantation at the same time.
（Ｃ） ｌ リゴア部！・のベース１１．抵抗部■の領
域５゜β１Ｌ部のインジェクタ１２． インバータのベ
ース１３のＰ＋拡散のためのＢ（ボロン）デポジシ。(C) l Rigoa Club! Base of 11. Injector 12 in the area 5°β1L of the resistor section ■. B (boron) deposit for P+ diffusion in the base 13 of the inverter.
ン（又はイオン打込み）を行なう。このとき同時にアイ
ソレージ冒ンの表面部’１４にもボロンをオーバラップ
するように導入する。(or ion implantation). At this time, boron is also introduced into the surface part '14 of the isolation layer so as to overlap.
（ｄｌ リニア部Ｉのエミッタ１５． コレクタ取出
し部１６： β１Ｌ部のマルチコレクタ１７． エミ
ッタリング１８のＮ＋拡散のためのＰ（リン）又はＡｓ
（、ヒ素）の高濃度デポジン璽ヌ拡散を行なう。(dl Emitter 15 of linear part I. Collector extraction part 16: Multi-collector 17 of β1L part. P (phosphorus) or As for N+ diffusion of emitter ring 18
(, arsenic) is diffused into a high concentration deposit.
第５図は上記工程終了後の各素子領域１． Ｗｅ Ｉ
ＩＩにおける拡散パターンのレイアウトを示す平面図で
ある。FIG. 5 shows each element region 1. after the above process is completed. We I
FIG. 3 is a plan view showing the layout of the diffusion pattern in II.
この後、図示畜れないが、表面酸化膜上にＰＳＧ（リン
・シリケート・ガラス）等をデポジットし、コンタクト
ホトエッチによる各半導体領域に窓開し、ＡＪ蒸着、ア
ニール、ホトエッチの各工程を経て電極、配線を完成す
る。なお、第５図において抵抗領域５に対する配線は例
えば点線で図示したようにアイソレージＩｌ′７１・４
上に延び木ことばいうまでもない。After this, as shown in the figure, PSG (phosphorus silicate glass) or the like is deposited on the surface oxide film, a window is opened in each semiconductor region by contact photoetching, and the steps of AJ vapor deposition, annealing, and photoetching are performed. Complete the electrodes and wiring. In FIG. 5, the wiring for the resistance region 5 is, for example, an isolation wire Il'71/4 as shown by a dotted line.
Needless to say, it grows upwards.
以上実施例で述べたように、■！Ｌ高耐圧プロセスでは
、通常Ｉ”Ｌ部のＮ″″″エピタキシヤル層上！１！ク
エルイオン打込みを行なってβ１（ＮＰＮ型インバーメ
トランジスタの電流増幅率）値を調整することが行われ
ているので、このＮ型ウェルイオン打込みと抵抗部のＮ
−エピタキシャル層の比抵抗を下げ″′ＣＮ一層表面の
反転をなりシ薔生ＭＯ８発生を防止する目的でのＮ型不
純物イオン打込みとを同じ工程で行なうことができ、特
にエミッタ拡散等による沓生ＭＯ８対策が不要となり、
抵抗レイアウトの高密度化が実現できる。As mentioned above in the examples, ■! In the L high voltage process, it is usually on the N″″″ epitaxial layer of the I″L part! 1! Quell ion implantation is performed to adjust the β1 (current amplification factor of an NPN type inverter transistor) value, so this N type well ion implantation and N
- N-type impurity ion implantation for the purpose of lowering the specific resistance of the epitaxial layer, causing inversion of the surface of the CN layer, and preventing the generation of MO8 can be performed in the same process. MO8 countermeasures are no longer necessary,
High density resistor layout can be achieved.
第１図は従来型の半導体抵抗率子の例を示す断面図であ
る。第２図は本発明の原理的構成を示す半導体装置の断
面図、第３因は本発明の一実施例を示す半導体＠１１の
正面断面斜面図、第４図（ａｌ〜（ｄｉはＩＲＬ高耐圧
ＩＯに本発明を適用した場合のプロセスにおける１糧断
面図、第５図は第４図１ｄｌに対応する拡散パターンの
平面図である。
ｌ・・・Ｐ−型Ｓｉ基板、２・・・Ｎ＋型埋込層、３・
・・Ｎ−型８ｉ エピタキシャル層、４・・・Ｐ型アイ
ソレージ冒ン、５・・・Ｐ＋型島領域（抵抗）、６・・
・ＡＩ配線、７・・・酸化膜、８・・・Ｎ＋型チャネル
ストッパ、９・・・コンタクト孔、１０・・・酸化膜マ
スク、１１・・・リニア部のベース、１２・・・インジ
ェクタ、１３・・・インバータのベース、１４・・・ア
イソレーン１フ表面部、１５・・・エミッタ、１６・・
・コレクタ取出し部、１７・・・マルチコレクタ、１８
・・・エミッタリング。FIG. 1 is a cross-sectional view showing an example of a conventional semiconductor resistor. FIG. 2 is a cross-sectional view of a semiconductor device showing the basic configuration of the present invention, the third factor is a front cross-sectional oblique view of a semiconductor @11 showing an embodiment of the present invention, and FIG. FIG. 5 is a cross-sectional view of a process in which the present invention is applied to a withstand voltage IO, and FIG. 5 is a plan view of a diffusion pattern corresponding to 1dl in FIG. 4. l...P-type Si substrate, 2... N+ type buried layer, 3.
...N- type 8i epitaxial layer, 4...P type isolation layer, 5...P+ type island region (resistance), 6...
・AI wiring, 7... Oxide film, 8... N+ type channel stopper, 9... Contact hole, 10... Oxide film mask, 11... Base of linear part, 12... Injector, 13...Base of inverter, 14...Isolane 1 surface part, 15...Emitter, 16...
・Collector extraction part, 17...Multi collector, 18
...Emitter ring.
Claims (1)
のうち少くなくとも一つのエピタキシャル層内にそのエ
ピタキシャル層と逆導電型の半導体抵抗領域を形成する
にあたって、半導体抵抗領域を形成すべきエピタキシャ
ル層内を他のエピタキシャル層よりも高不純物濃ｌｌ！
にしておくことを特徴とする半導体装置の製法。1. When forming a semiconductor resistance region of a conductivity type opposite to that of at least one epitaxial layer among a plurality of fissolated semiconductor epitaxial layers, the inside of the epitaxial layer in which the semiconductor resistance region is to be formed is Higher impurity concentration than epitaxial layer!
A method for manufacturing a semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56113712A JPS5816559A (en) | 1981-07-22 | 1981-07-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56113712A JPS5816559A (en) | 1981-07-22 | 1981-07-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5816559A true JPS5816559A (en) | 1983-01-31 |
Family
ID=14619239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56113712A Pending JPS5816559A (en) | 1981-07-22 | 1981-07-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5816559A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5466963A (en) * | 1994-01-13 | 1995-11-14 | Harris Corporation | Trench resistor architecture |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5017992A (en) * | 1973-06-19 | 1975-02-25 | ||
| JPS515976A (en) * | 1974-07-04 | 1976-01-19 | Tokyo Shibaura Electric Co | SHUSEKI KAIROSOSHI |
-
1981
- 1981-07-22 JP JP56113712A patent/JPS5816559A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5017992A (en) * | 1973-06-19 | 1975-02-25 | ||
| JPS515976A (en) * | 1974-07-04 | 1976-01-19 | Tokyo Shibaura Electric Co | SHUSEKI KAIROSOSHI |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5466963A (en) * | 1994-01-13 | 1995-11-14 | Harris Corporation | Trench resistor architecture |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6080267A (en) | Semiconductor ic device and manufacture thereof | |
| US5323057A (en) | Lateral bipolar transistor with insulating trenches | |
| US4199378A (en) | Method of manufacturing a semiconductor device and semiconductor device manufactured while using such a method | |
| GB2156583A (en) | Process for producing semiconductor device | |
| KR910006672B1 (en) | Semiconductor integrated circuit device and its manufacturing method | |
| JPH0557741B2 (en) | ||
| JPS63200568A (en) | Bipolar transistor employing cmos technology and manufacture of the same | |
| JPS5880851A (en) | Semiconductor device and method of producing same | |
| JPH02246264A (en) | Semiconductor device and manufacture thereof | |
| JP3099917B2 (en) | Field effect transistor | |
| US4197147A (en) | Method of manufacturing an integrated circuit including an analog circuit and an I2 L circuit utilizing staged diffusion techniques | |
| JPS5816559A (en) | Manufacture of semiconductor device | |
| JPS62229880A (en) | Semiconductor device and manufacture thereof | |
| KR100774114B1 (en) | Semiconductor device for integrated injection logic cell and process for fabricating the same | |
| EP0367293B1 (en) | Methods of fabricating semiconductor devices having a bipolar transistor | |
| JPH06168953A (en) | Bipolar transistor | |
| JPS6159775A (en) | Semiconductor device | |
| JP3082800B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2602490B2 (en) | Method for manufacturing semiconductor device | |
| JPH0621077A (en) | Semiconductor device and manufacture thereof | |
| JPH01187868A (en) | Semiconductor device | |
| JPS61139057A (en) | Manufacture of semiconductor integrated circuit device | |
| JPH0574790A (en) | Semiconductor device and manufacture thereof | |
| JPS58108765A (en) | Manufacture of semiconductor device | |
| JPH02278736A (en) | Semiconductor device |