JPS5816294Y2 - frequency control circuit - Google Patents

Description

[Detailed Description of the Invention] The interval, that is, the frequency, of the horizontal synchronization signal of a reproduced video signal obtained by a recording/reproducing device may be disturbed due to dropout or skew.

Therefore, for example, when trying to obtain a clock pulse whose frequency corresponds to the frequency of the reproduced horizontal synchronizing signal and whose phase is synchronized with the reproduced burst signal in a device that corrects the time error of the reproduced video signal, the reproduced horizontal synchronizing signal It is not desirable to use the horizontal synchronization signal in the reproduced video signal as a signal.

In view of this point, the present invention has been developed to easily create a synchronization signal that is completely free from dropout effects from the original synchronization signal and in which the effects of skew are minimized. .

Hereinafter, a specific example of the present invention will be explained with reference to the drawings.

In FIG. 1, 1 is a variable frequency oscillator whose oscillation center frequency is, for example, 6 times the subcarrier frequency, that is, about 21.481 VIHz, and 2 and 3 are oscillation pulses S of this variable frequency oscillator 1.

These are first and second counters that divide X455 P (FIG. 2A) by -11-1 to form a horizontal frequency pulse.

For example, 12-bit counters are used as counters 2 and 3, and their initial load value is "2731J".
and the output S of the first counter 2.

H (B in the same figure) becomes "0" in an interval corresponding to one cycle of the oscillation pulse SCP whose value becomes "2731".

4 is a terminal to which the I/'i reproduced video signal is supplied, 5 is a horizontal synchronizing signal separation circuit for extracting the horizontal synchronizing signal SH (FIG. 2C) from this reproduced video signal, and 6 is this horizontal synchronizing signal sHO.
In a monostable multivibrator triggered by the leading edge, the time to maintain the metastable state of the monostable multivibrator 6 is, for example, 400 nSee.0 γ is a phase comparison circuit, and the falling edge of the output SCH of the first counter 2 and the output SDR of monostable multivibrator 6
(D in FIG. 2) is compared in phase, and the oscillation frequency of the variable frequency oscillator 1 is controlled by the comparison output.

8 is a window pulse forming circuit in which the counter 2 changes to l'-4 depending on the state of the first counter 2 and the oscillation pulse SCP.
The output Sw (FIG. 2E) becomes "1" in the division of 15 force counts taking the value from 080j to r4.094jt, and a window pulse is obtained.

Reference numeral 9 denotes a signal forming circuit that forms a signal in which the horizontal synchronizing signal SH is synchronized with the oscillation pulse SCP.In other words, from this signal forming circuit 9, two of the oscillating pulses SCP, counted from the leading edge of the horizontal synchronizing signal sHO, are output from the signal forming circuit 9. Signal Sy that becomes “1” in the interval between the 3rd pulse and the 3rd pulse (Fig. 2 G)
is obtained.

Reference numeral 10 denotes a detection circuit for detecting whether or not the interval between the horizontal synchronizing signals shH is within a certain range.It is composed of NAND circuits 11 and 12 and an inverter 13, and the output signal Sw of the circuit 8 and the output signal Sy of the circuit 9 are connected to the NAND circuit. The polarity inverted output Sw of the output Sw from the inverter 13 is supplied to the circuit 11 (FIG. 2F)
and signal Sy are supplied to the NAND circuit 12.

14 is a signal forming circuit that forms a hold signal for the first counter 2, which is composed of a monostable multivibrator 15 and a JK flip 70 tube circuit 16, and is made monostable by the rise of the output SOK of the NAND circuit 11 of the detection circuit 10. When the multivibrator 15 is triggered, the time for which the monostable multivibrator 15 maintains the metastable state is approximately 15 cycles of the oscillation pulse SCP, and the JK flip-flop circuit 16 has the input signal of the metastable multivibrator 15 as the J input. The output sM is the output S of the circuit 8 as the T input.
w is supplied with the output signal Sy of the circuit 9 as the R input, respectively.

17 is another counter, for example, a 2-bit counter, whose value is reset to "1" by the fall of the output SNG of the NAND circuit 12 of the detection circuit 10, and the output SA
becomes “O”, and from this, the NAND circuit 1 of the detection circuit 10
When the output SOK of 1 becomes “0” three times in a row, the output SA
becomes "1".

18 is a NAND circuit, and the output SA of counter 17 is "1"
At this time, a signal sR with the polarity of the signal Sy inverted is taken out.

19 is a retrigger type monostable multivibrator, the second
It is triggered by the output Sc of the counter 3,
Corresponding to the fact that the frequency of the output Sc is set to the horizontal frequency, the time period during which the quasi-stable state should be maintained is, for example, 100 of the horizontal period, that is, approximately 32 μsec.

The state of the reproduced horizontal synchronizing signal sH and the first counter 2 is the second
In the states shown in Figures C and A, when the signal Sy exists within the interval of "1" of the output Sw, that is, in the white part of the window pulse, one output of the detection circuit 10 is 5OK (H in the figure).
becomes “0” in the section of signal Sy, and the other output SNG
(Same artist) becomes 1 in the past of ``1''.

In addition, in the circuit 14, the output SM (J in the figure) of the monostable multivibrator 15 falls when the output SOK rises, and JK at the rise of the output Sw.
Since the J input of the flip-flop circuit 16 is "0", the output sJ (K in the figure) of the circuit 16 is 11 of varOJ.

Therefore, at this time, the monostable multi-high frame rate is not forcibly reset, the counter 2 is neither forced to load nor forced to hold, and in the phase comparator circuit 1, the counter 2 The falling edge of the output SCH and the falling edge of the output SDR of the monostable multivibrator 6, which is delayed by 400 nsec from the front line of the horizontal synchronizing signal sH, are phase-compared, and the comparison output is used to control the variable frequency oscillator 1.
oscillation frequency is controlled.

The interval between the reproduced horizontal synchronizing signals sH becomes longer, and the states of the reproduced horizontal synchronizing signals sH and the first counter 2 become as shown in FIG. When the signal Sy is obtained with a delay of the pulse width, one output SOK of the detection circuit 10 does not become rOJ in the "1" section of the output Sw, and the monostable multivibrator 15 is triggered in the circuit 14. First, since the output sM, that is, the J input of the JK flip-flop circuit 16, is "1" at the time of the fall of the output Sw, the output SJ of the circuit 16 becomes "1" at this point, and the counter 2 is forced to hold. state.

Then, when the signal Sy is obtained after the horizontal synchronization signal sH, its falling edge causes the JK flip-flop circuit 16 to
The output sJ returns to "0" and the forced halt state is released.

That is, as shown in the figure, the counter 2 is held in the state r4095J from the fall of the output Sw to the fall of the signal Sy.

Then, the other output sNG of the detection circuit 10 becomes "0" in the section of the signal SY, and the rise of this output SNG forces the counter 2 to be loaded to the state of "2724", and its output SCH becomes "0". Become.

Furthermore, due to the rise of this output SNG, the monostable multivibrator 6 is forcibly reset and its output SD
R falls.

Therefore, the fall of the output SCH of the counter 2 and the fall of the output SDR of the monostable multivibrator 6 are forced to coincide, and the phase comparison circuit γ
The output voltage does not change, and the phase comparison operation substantially stops.

At this time, the initial state of counter 2 is “2” as described in
Since it is loaded to l-2724,j 7 forces und before 731J, the rtJ section of the next output Sw, that is, the window pulse, appears at a position delayed by 7 forces und, and the center position of the window pulse As is clear from the figure, the state of counter 2 at
If the interval is normal, the next horizontal synchronization signal sH
At this point, the signal Sy now exists within the "1" section of the output Sw, and once again one output S of the detection circuit 10
OK becomes rOJ, and the phase comparison operation is performed in the same way as in the case of FIG. 2 (see FIG. 5C).

The interval between the reproduced horizontal synchronizing signals sH becomes shorter, and the states of the reproduced horizontal synchronizing signals sH and the first counter 2 become as shown in FIG. 4 C and A.
When a state like this occurs and the signal Sy is obtained earlier than the interval in which the output Sw should be 11'', the output SNG of the detection circuit 10 becomes rOJ in the interval of the signal Sy, and this output S
When NG goes low and goes low, the counter 2 is forcibly loaded to the state of "2724" and its output SCH becomes r.
Becomes O.J.

Furthermore, due to the fall of this output SNG, the monostable multivibrator 6 is forcibly reset and its output SD
R stands up.

Therefore, as in the case of FIG. 3, the output SC of counter 2
Falling edge of H and output S of monostable multivibrator 6
The falling points of DH are forced to coincide, the output voltage of the phase comparison circuit 7 does not change, and the phase comparison operation is substantially stopped.

At this time, since the counter 2 will never reach a state of 14080j or higher, the output Sw will never be 1-1" and will not be 0, that is, no window pulse will be obtained.

Therefore, the counter 2 is not forced to hold.

In this case as well, if the interval at the next horizontal synchronizing signal sHt is normal, at the next horizontal synchronizing signal sH, the signal Sy will exist within the 11'' section of the output Sw, and again One output SOK of the detection circuit 10 becomes rOJ, and a phase comparison operation is performed in the same way as in the case of FIG.
(See Figure 5C).

In this way, the oscillation frequency of the variable frequency oscillator 1 is prevented from being disturbed by dropouts or stews.

The stable frequency oscillation pulse SCP from the variable frequency oscillator 1 is then supplied to the second counter 3 and frequency-divided into .

As shown by the arrow in FIG.
, the output SNG of the detection circuit 10 becomes rOJ.
As a result, the counter γ is reset to rlJ and its output SA becomes "0", and the dropout disappears and the output SOK of the detection circuit 10 becomes "0" three times in a row.
”, the output SA becomes “1”.

Then, the output SOK continues in this way for more than 3M [
-〇'' and the output SA of the counter 7 is ``1'', the output sR of the NAND circuit 18 becomes ``O'' at the signal Sy (see Fig. 6), and the counter 3 outputs ``2731''.
J is forcibly reset, and its output Sc becomes "0".

However, since the counter 3 is not forcibly reset by the output SNG, in the section where the output SA is "O", the output Sc becomes rOJ at a certain interval when the counter 3 returns from r4095J to "2731". Become.

Then, the monostable multivibrator 19 is triggered when the output Sc becomes "0", thereby obtaining a horizontal synchronization signal SOH without the influence of dropout.

As shown by the arrow in FIG. 5B, when the interval between the reproduced horizontal synchronization signals SH becomes momentarily longer due to skew (in the case of FIG. 3), the output SOK becomes 1-0 three times in a row. Count 3 is not reset during this period, and therefore the signal SOH deviates from the reproduced horizontal synchronization signal SH, but
When the output SOK reaches rOJ three times in a row, counter 1
When the output SA of 7 becomes "1", the counter 3 is forcibly reset at the signal Sy, and thereafter the signal SO
H becomes synchronized with the reproduced horizontal synchronizing signal sH.

As shown by the arrow in FIG.
The same applies to the case shown in FIG. 4).

In this way, the output signal SOH of the monostable multivibrator 19 is not affected by dropout at all, and the effect of skew is limited to only a few horizontal periods, making it continuous.

As described above, according to the present invention, it is possible to easily obtain a horizontal synchronization signal from a reproduced horizontal synchronization signal that is completely free from the influence of dropout and in which the influence of skew is minimized.

[Brief explanation of the drawing]

FIG. 1 is a system diagram of an example of the present invention, and FIGS. 2 to 6 are waveform diagrams for explaining the same. 1 is a variable frequency oscillator, 2 and 3 are first and second counters, 5 is a horizontal synchronizing signal separation circuit, 6 is a monostable multivibrator, γ is a phase comparison circuit, 10 is a detection circuit, 17
is a counter, and 19 is a retrigger type monostable multivibrator.

Claims (1)

[Scope of utility model registration request] a monostable multivibrator triggered by a horizontal synchronization signal; a variable frequency oscillator; first and second counters for frequency dividing the output of the variable frequency oscillator;
a phase comparison circuit for controlling the oscillation frequency of the variable frequency oscillator by comparing the phases of the output of the counter and the output of the monostable multivibrator; and the output of the first counter and the output of the variable frequency oscillator. a window signal forming circuit that forms a window signal; a synchronization signal forming circuit that forms these synchronization signals from the output of the variable frequency oscillator and the horizontal synchronization signal; It has a detection circuit that detects whether the interval between horizontal synchronization signals is within a certain range, and a third counter that counts the detection output of this detection circuit, and the detection output of the detection circuit detects the horizontal synchronization. When the interval between the signals falls within the above-mentioned certain range, the phase comparison operation in the phase comparison circuit is stopped, and a predetermined value is loaded into the first counter, and the interval between the horizontal synchronizing signals falls within the above-mentioned certain range. , the third counter detects a section in which this continues for a predetermined number of times or more;
A frequency control circuit configured to reset the second counter using the detection output and the synchronization signal to obtain a new horizontal synchronization signal from the second counter.