JPS58161199A - Inspecting method of read-only memory device - Google Patents
Inspecting method of read-only memory deviceInfo
- Publication number
- JPS58161199A JPS58161199A JP57042690A JP4269082A JPS58161199A JP S58161199 A JPS58161199 A JP S58161199A JP 57042690 A JP57042690 A JP 57042690A JP 4269082 A JP4269082 A JP 4269082A JP S58161199 A JPS58161199 A JP S58161199A
- Authority
- JP
- Japan
- Prior art keywords
- test
- double selection
- cell
- output
- expected value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 6
- 238000012360 testing method Methods 0.000 claims abstract description 14
- 238000007689 inspection Methods 0.000 claims abstract description 9
- 230000006870 function Effects 0.000 abstract description 2
- 230000001066 destructive effect Effects 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000011990 functional testing Methods 0.000 description 2
- 241000272201 Columbiformes Species 0.000 description 1
- 241000270666 Testudines Species 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
本脅−＋ｔｍ出し専用メ峰り装置、轡にλＯＭ（Ｒ＠ａ
ｄ ０ｎｌｙ Ｍｅｍｏｒｙ）の検査方法に閤するもの
であ番・
ＲＯＭでは、本体メ４１Ｊ七ルに書き込んで検査するこ
とが出きないため、検査用ダミーセルパターンがワード
ツイン及びピッシラインＥｔ８って。[Detailed description of the invention] This threat-+tm output exclusive measuring device, λOM (R@a
Since it is not possible to test the ROM by writing to the main body memory, the dummy cell pattern for testing is Word Twin and Pisciline Et8.
もうけられている、従来は、この検査用パターンの配置
を、アドレスが変わると出力が切り蜜わるようにし曵い
た＊１１ｔＫ従牽の検査パターンな示す。従来はこの検
査パターンを選択することで機能試験及び交ｔ１１ＩＩ
Ｉ作試験を行なっていた。しかし、ＲＯＭの不良原因と
して配鐘関のシ冒−トが大きな開会をしめている。そこ
で、ウェハー状園の段階でこの不良ｖＩＩｊＬ９除く必
要があろ、そこで、検査パターンを用いて検査すること
が考えられるわけであるが、従来の検査パターン（第１
ｌｌ）では、例えばＪ、と４．がシ１−トしている場合
、機能試験を行なうことで、Ｍ、の出力は期待値の＠１
ｍとなるがＭ４の出力は期待値の“０”でなく１１２と
なり、検出することができる。しかし、Ｊ、と１ｓ又は
Ｊａと４．のような場合、隣とシ、−）１．ていても期
待値通りの出力となるため配−間のシｌ−トは検出でき
ない。Conventionally, this test pattern is arranged in such a way that the output changes sharply when the address changes. Conventionally, by selecting this inspection pattern, the function test and the
I was conducting an I-writing test. However, the blank sheet of the bell is widely considered to be the cause of the ROM failure. Therefore, it is necessary to remove this defect vIIjL9 at the wafer stage, and it is possible to perform inspection using an inspection pattern.
ll), for example, J, and 4. If M is sheeting, by performing a functional test, the output of M will be the expected value @1.
However, the output of M4 is not the expected value of "0" but 112, which can be detected. However, J, and 1s or Ja and 4. In a case like, the neighbor and the -)1. Even if the output is set as expected, the output will be the same as the expected value, so the sheet between the wires cannot be detected.
本発明は、上記のような問題を解決し、配−間のシ冒−
ト及び２重選択不良を検出することができる検査方法ｖ
ＩＩＩ供するものである。The present invention solves the above-mentioned problems and improves the wiring interface.
Inspection method capable of detecting faults and double selection defectsv
III.
本発明は、上記目的にもとづき、検査パターンを１”、
“０”交互に配列することにより、機能試験を行なうこ
とによって、７１−トした部分があったり、２重選択が
あれば、確実に検出できることを％像としている。Based on the above object, the present invention has an inspection pattern of 1",
By arranging "0" alternately and performing a functional test, it is possible to reliably detect if there is a 71-cut portion or double selection.
本発明によれば、検査用セルの配置を、例えば接合破壊
式Ｐ −ＲＯＭ （Ｐｒｏｇｒａｍａｂｌｅ −Ｒｅａ
ｄＯｎｌｙ Ｍ＠ｍｏｒｙ ）では、トランジスタとダ
イオードを交互に配置することにより配−関のシ１−ト
やメモリセルの２重選択などの不良を検出できるように
し、他のＲＯＭ全般のデバイスでは、ハイ及び掌つレベ
ルの情報が交互に並ぶようメモリセルを配置することに
より、上記のような効果が得られるようにしている。According to the present invention, the arrangement of the test cells can be changed to, for example, a junction-destructive P-ROM (Programmable-Rea).
dOnly M@mory) uses alternating arrangement of transistors and diodes to detect defects such as allocation sheets and double selection of memory cells. By arranging the memory cells so that information at a palm-level level is arranged alternately, the above-mentioned effects can be obtained.
第２図は、本発明の具体的な実施例を示すものである６
Ｍ１〜Ｍ・はトランジスタとダイオードを交互に配置し
たテストセルである。上記各セルからの出力を比較器に
入れ、他方上記各セルに対応する期待値を上記比較器に
入れこれらを比較する。ことにより、不良箇所を検出す
る０例えば、Ｊ亀とＪｔがシ冒−トシていた場合、Ｍ電
を選択すれば”１”で期待値と一致するが、鳩を選択す
ると、期待値１０”ではな（”１″Ｖ出力する。このよ
５に、トランジスタとダイオードが交互になっていれば
、シーートしている場合、必ず期待値と真なる出力が検
出され比較Ｉ！によって期待値と比較され不良箇所が検
出される。それによって、配曽関シ冒−ト及び２重選択
の不良を象り除くことができる。尚、１′、〜１′、は
期待値が出力されるビットラインである。FIG. 2 shows a specific embodiment of the present invention.6
M1 to M. are test cells in which transistors and diodes are alternately arranged. The output from each cell is input into a comparator, and the expected value corresponding to each cell is input into the comparator and compared. For example, if J turtle and Jt are in conflict, if M electric is selected, the expected value will be 1, but if pigeon is selected, the expected value will be 10. Well then (outputs "1" V. 5) If the transistors and diodes are alternated, if they are seated, the expected value and true output will be detected and compared with the expected value using comparison I! The defective location is detected.Thereby, it is possible to eliminate assignment errors and double selection defects.Note that 1' and ~1' are the bit lines where the expected value is output. It is.
同様に、第３図で示すヒ５−ズ方式の場合も、配線間に
シ璽−トがあったり、２重選択不良であった場合、期待
値と異なっている情報を得た場合不良であると判定でき
る。Similarly, in the case of the fuse method shown in Figure 3, if there is a mark between the wires, if there is a double selection defect, or if information different from the expected value is obtained, it is considered defective. It can be determined that there is.
本発明により、これまで組立ててから書き込まないと検
出できなかった配−シ雪−ト及び１重選択不良を、プロ
ーブ検査の段階で検出することが出き、製品コストの低
減に非常に大きな効果を与える・また、製品の市場にお
ける信頼性の陶土に有効となる。ｔた、検査パターンも
（１０１０１０・・・・・・）と単純化できる。The present invention makes it possible to detect layout defects and single-layer selection defects, which previously could only be detected after assembly, at the probe inspection stage, which has a significant effect on reducing product costs. It also gives the product credibility in the market and makes it effective. Furthermore, the inspection pattern can also be simplified to (101010...).
第１図は従来の接合破壊方式Ｐ−ＲＯＭの検査パターン
の回Ｉ８図である。８１２図は本発明の１重施例による
検査パターンの回路図である。また、第３図は本発ｖ４
ｖヒ、−ズ方式に応用した検査パターンの回路図である
。
なお、図面に示された符号において、も〜Ｊ−゛はビッ
トライン、Ｍ１〜Ｍ、及びＨ２〜Ｈ６線テストセルであ
る。
代理人 弁理士 薄 １）利 幸 。
・、 ・）
ｒ
第 １ 図
口
θＵＴ
第 ２ 図
第 ３ 図
口
５５１FIG. 1 is a diagram illustrating a test pattern of a conventional junction destruction type P-ROM. FIG. 812 is a circuit diagram of a test pattern according to a single embodiment of the present invention. Also, Figure 3 shows the main version v4
FIG. 2 is a circuit diagram of a test pattern applied to the v-hi, -z method. In addition, in the reference numerals shown in the drawings, J-' is a bit line, M1-M, and H2-H6 line test cells. Agent Patent Attorney Susuki 1) Toshiyuki.・, ・) r 1st drawing exit θUT 2nd drawing 3rd drawing exit 551
Claims (1)
レベルとが交互に得られるよ５に構成したメモリセル列
を検査用ダイ−パターンとして用いこの検査用セルから
の出力を期待値と比較することによりセルＫｉｌ続され
る配−関のシ層−ト叉は２重選貰不良を検出するよ５Ｋ
したことを轡像とする貌出し専用メ篭り装置の検査方株
。1. Compare the output from the test cell with the expected value using a memory cell array configured in 5 as a test die pattern so that low level and high level are alternately obtained as the expected output from each bit. 5K to detect double selection failures or double selection failures in the allocation layer connected to the cell.
This is an inspection method of a special method for revealing the image of what happened.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57042690A JPS58161199A (en) | 1982-03-19 | 1982-03-19 | Inspecting method of read-only memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57042690A JPS58161199A (en) | 1982-03-19 | 1982-03-19 | Inspecting method of read-only memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58161199A true JPS58161199A (en) | 1983-09-24 |
Family
ID=12643029
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57042690A Pending JPS58161199A (en) | 1982-03-19 | 1982-03-19 | Inspecting method of read-only memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58161199A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01296500A (en) * | 1988-05-23 | 1989-11-29 | Mitsubishi Electric Corp | Semiconductor memory |
| JPH03134888A (en) * | 1989-10-20 | 1991-06-07 | Fujitsu Ltd | Semiconductor memory device |
| JP2006147024A (en) * | 2004-11-18 | 2006-06-08 | Takashi Oshikiri | Semiconductor memory and test method of semiconductor memory |
-
1982
- 1982-03-19 JP JP57042690A patent/JPS58161199A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01296500A (en) * | 1988-05-23 | 1989-11-29 | Mitsubishi Electric Corp | Semiconductor memory |
| JPH03134888A (en) * | 1989-10-20 | 1991-06-07 | Fujitsu Ltd | Semiconductor memory device |
| JP2006147024A (en) * | 2004-11-18 | 2006-06-08 | Takashi Oshikiri | Semiconductor memory and test method of semiconductor memory |
| US8090958B2 (en) | 2004-11-18 | 2012-01-03 | Takashi Oshikiri | Semiconductor memory and method of testing semiconductor memory |
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